From patchwork Mon Jan 22 08:29:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 764802 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1EAC38386; Mon, 22 Jan 2024 08:30:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705912217; cv=none; b=qgslJjqK6hX3o8s2doLF7av4QY/N9EnpRL0o9QHAgTCW2xGCms4xlwPE3GMlDE4nPQQSD0NarL9WjuoziRoIvJRyb127kTdDCx3zxkrpnUjnU2PSxrJl96lDZrRlNNis7b6PAzWKctY5DVc0YsDkFqRTrb9z8C4vO2UnNyOEZek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705912217; c=relaxed/simple; bh=Rf5MI82lZHhYGSDhwKtyN1xGV0ZqSdRkhIta/II4uNE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BVE72F1WWVp+kbfJEowWWEOPGTlHYQVr/iNl+paKNGHqkl1ObgXiSDMT6/zOYeMZ2dMgPajVun3wVJ6vi4xLBt8fJUEWwNMl9LoDHVXXIf2BnxlYzqRsqDp+FluAgfY69iKyl+FMH/Cr9ZObrlls2Tz7CFVTc7iLTPiHv+/F9fM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Ms03aeg4; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Ms03aeg4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1705912215; x=1737448215; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rf5MI82lZHhYGSDhwKtyN1xGV0ZqSdRkhIta/II4uNE=; b=Ms03aeg47J/n5pf0XBWeuT9dbvr5sf3ru0WJHdAIPi3LZW+WFEF8oiBX DG45oUCKc2rODgCKrrt7Z+Yn+85Y4ArPt0NZRwvjpdLBv0UP+rjRBMuwZ ETOJxRkk2AQP2vAfmM2NwDKJe7FydCBiNKxUSy0iysnbrCG17ytMrBkmm 9CqAB3j3DjdM7w7rIzlnxRf2FtvnJ0QhljBIOOgbp1/eTFR4FPVTXgfYi zd1lHXP7WUmki4Qn9QioWiCOMklu3n/yX6l94779D6xOrnXBkV5DthlQl c2IomLIDC9HG7x6dOzvNjjK+mJioQNwcd4YmNXKJBrvb2/RNipXFLcqHl w==; X-CSE-ConnectionGUID: C6zQ2Iq3QDa7pYOudyjy+g== X-CSE-MsgGUID: iDsarLzDRj6WJ7QX1eoRtg== X-IronPort-AV: E=Sophos;i="6.05,211,1701154800"; d="scan'208";a="15086355" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 22 Jan 2024 01:30:14 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 22 Jan 2024 01:30:04 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 22 Jan 2024 01:29:57 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 1/3] dt-bindings: display: bridge: add sam9x7-lvds compatible Date: Mon, 22 Jan 2024 13:59:45 +0530 Message-ID: <20240122082947.21645-2-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240122082947.21645-1-dharma.b@microchip.com> References: <20240122082947.21645-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the 'sam9x7-lvds' compatible binding, which describes the Low Voltage Differential Signaling (LVDS) Controller found on Microchip's sam9x7 series System-on-Chip (SoC) devices. This binding will be used to define the properties and configuration for the LVDS Controller in DT. Signed-off-by: Dharma Balasubiramani --- .../display/bridge/microchip,sam9x7-lvds.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.yaml new file mode 100644 index 000000000000..8c2c5b858c85 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/microchip,sam9x7-lvds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAM9X7 LVDS Controller + +maintainers: + - Dharma Balasubiramani + +description: | + The Low Voltage Differential Signaling Controller (LVDSC) manages data + format conversion from the LCD Controller internal DPI bus to OpenLDI + LVDS output signals. LVDSC functions include bit mapping, balanced mode + management, and serializer. + +properties: + compatible: + const: microchip,sam9x7-lvds + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral Bus Clock + + clock-names: + items: + - const: pclk + - const: gclk + minItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + lvds-controller@f8060000 { + compatible = "microchip,sam9x7-lvds"; + reg = <0xf8060000 0x100>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "pclk"; + }; From patchwork Mon Jan 22 08:29:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 764801 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3A4739AC5; Mon, 22 Jan 2024 08:30:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705912249; cv=none; b=t434mdWazaJ/luaxQ32NSMgCo2nortCAkW4DQIfMrWHpw++60uJwk1KpbDxZJncNDDUejqFX168v3ywnJYBExuY8AHfpoXHUjQhqb8ysUj4Dj7hs2UxSd13t2jWg4QpU8rccvouk2LSBLIrOdr2XfwbxwERrOCBVrdk+AJpjEac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705912249; c=relaxed/simple; bh=Ia2hVk9eM5wQHbe/b7mdo2yOfz17oFqWIhOV8eIVvmI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a6HP1KHn+9YIIJMF/ToR+hKNWzN9S9xlCL3Pkn5c0Qp0kd2Dc4kX2bH+ZB0llJH+KxRRZBtjsMJr/yG+ad+OL7rOIxgusKaWkqiTU8RZ28cwOkH2BJAs+SO9Xn4zuB5B9mfpSa7GxqwYuS1aCCD/97kviZftneMYIIf59DfB3Ks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=kaSXSEE9; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="kaSXSEE9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1705912248; x=1737448248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ia2hVk9eM5wQHbe/b7mdo2yOfz17oFqWIhOV8eIVvmI=; b=kaSXSEE9PqDNnQO3LWR697LJnXT+wu9ztHyRY7EOa5FDbCH3i9aCvONu qixbczHWPayL5jQ7KnAdJOEEiU6e2+NozpfWCg2oDaWNqroV9fgQZkmiX OC9R/ExoHCn+Ur0562GaKAup+PLmB4rAWkFsdRVS8R2cPz3XqvmcntWB4 14qyoaGOZ/5JBZVTxA3gFybijc6l7dVpz517eyQOWO8bIsnpG1DNeGrp0 1UkAXtBcBmkqcLXmrAMOKaufTJuq6tFO8CMjQOEkso1gz4nek6w6T/l4f CivhyDIQWWscfki8imjJ5Z68hRgrMNM/rGvByCpPnjeXLmNt88bN4zBQI A==; X-CSE-ConnectionGUID: 3jDV5insTnecMVYu3SUMmw== X-CSE-MsgGUID: tePGqSCBQ5mxl/OALj4PUg== X-IronPort-AV: E=Sophos;i="6.05,211,1701154800"; d="scan'208";a="15568768" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 22 Jan 2024 01:30:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 22 Jan 2024 01:30:19 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 22 Jan 2024 01:30:12 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 3/3] MAINTAINERS: add SAM9X7 SoC's LVDS controller Date: Mon, 22 Jan 2024 13:59:47 +0530 Message-ID: <20240122082947.21645-4-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240122082947.21645-1-dharma.b@microchip.com> References: <20240122082947.21645-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the newly added LVDS controller for the SAM9X7 SoC to the existing MAINTAINERS entry. Signed-off-by: Dharma Balasubiramani --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a7c4cf8201e0..24a266d20df6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14230,6 +14230,14 @@ S: Supported F: Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml F: drivers/power/reset/at91-sama5d2_shdwc.c +MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER +M: Manikandan Muralidharan +M: Dharma Balasubiramani +L: dri-devel@lists.freedesktop.org +S: Supported +F: Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.yaml +F: drivers/gpu/drm/bridge/microchip-lvds.c + MICROCHIP SOC DRIVERS M: Conor Dooley S: Supported