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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id u11-20020a056402110b00b00558aa40f914sm14810435edv.40.2024.01.23.00.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 00:21:42 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Russell King , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Matthias Brugger , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 1/3] dt-bindings: arm: mediatek: convert hifsys to the json-schema Date: Tue, 23 Jan 2024 09:20:58 +0100 Message-Id: <20240123082100.7334-2-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240123082100.7334-1-zajec5@gmail.com> References: <20240123082100.7334-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Rafał Miłecki This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Documented "#reset-cells" property 3. Adjusted "reg" in example Signed-off-by: Rafał Miłecki --- .../bindings/arm/mediatek/mediatek,hifsys.txt | 26 --------- .../arm/mediatek/mediatek,mt2701-hifsys.yaml | 54 +++++++++++++++++++ 2 files changed, 54 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt deleted file mode 100644 index 323905af82c3..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt +++ /dev/null @@ -1,26 +0,0 @@ -Mediatek hifsys controller -============================ - -The Mediatek hifsys controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-hifsys", "syscon" - - "mediatek,mt7622-hifsys", "syscon" - - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" -- #clock-cells: Must be 1 - -The hifsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -hifsys: clock-controller@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml new file mode 100644 index 000000000000..7c7b7b7b1142 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt2701-hifsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek hifsys controller + +description: + The Mediatek hifsys controller provides various clocks and reset outputs to + the system. + +maintainers: + - Matthias Brugger + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt2701-hifsys + - const: syscon + - items: + - enum: + - mediatek,mt7623-hifsys + - const: mediatek,mt2701-hifsys + - const: syscon + - items: + - const: mediatek,mt7622-hifsys + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a000000 { + compatible = "mediatek,mt2701-hifsys", "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; From patchwork Tue Jan 23 08:21:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= X-Patchwork-Id: 765431 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1431857306; Tue, 23 Jan 2024 08:21:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705998110; cv=none; b=nAUKH3GdnpDVkWLLh9Unif5Od8E0E2jkZdl4ycAVj/HOHty36ItusdAVoono64jQ6jofHgz43bCpoKCHB7gMCc7KiR3jdUfkDvfwOsiQeMq3W6W/oRG0KytALN+Ofb3qOXiYQ4L/dJ8D72XkkVDMWAGLUAiJzvdwPFp6LqBRvzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id u11-20020a056402110b00b00558aa40f914sm14810435edv.40.2024.01.23.00.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 00:21:46 -0800 (PST) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Russell King , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Matthias Brugger , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 3/3] dt-bindings: arm: mediatek: convert SSUSBSYS to the json-schema Date: Tue, 23 Jan 2024 09:21:00 +0100 Message-Id: <20240123082100.7334-4-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240123082100.7334-1-zajec5@gmail.com> References: <20240123082100.7334-1-zajec5@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Rafał Miłecki This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Adjusted "reg" in example Signed-off-by: Rafał Miłecki --- .../mediatek/mediatek,mt7622-ssusbsys.yaml | 47 +++++++++++++++++++ .../arm/mediatek/mediatek,ssusbsys.txt | 25 ---------- 2 files changed, 47 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-ssusbsys.yaml delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-ssusbsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-ssusbsys.yaml new file mode 100644 index 000000000000..7a5343e4fcf4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-ssusbsys.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-ssusbsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SSUSBSYS controller + +description: + The MediaTek SSUSBSYS controller provides various clocks to the system. + +maintainers: + - Matthias Brugger + +properties: + compatible: + items: + - enum: + - mediatek,mt7622-ssusbsys + - mediatek,mt7629-ssusbsys + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt deleted file mode 100644 index 7cb02c930613..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek SSUSBSYS controller -============================ - -The MediaTek SSUSBSYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-ssusbsys", "syscon" - - "mediatek,mt7629-ssusbsys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The SSUSBSYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -ssusbsys: ssusbsys@1a000000 { - compatible = "mediatek,mt7622-ssusbsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -};