From patchwork Fri Jan 26 10:00:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 767636 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B87E5A0FE for ; Fri, 26 Jan 2024 10:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263240; cv=none; b=bfZT82n067pZgJZcuynscT78bND+SAgao8/GVOv5oeRCm1UkQ74ALqicr327JJUbZ9F61AQwWSjjdFNHryTctVbK5DxejqTQtyyL5gmZUx9kHudXjSsh41LeDjOudhGtlza7xIn3wOFxc2WcN5aUOXI3NTqCj86DYBmaiLr/GBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263240; c=relaxed/simple; bh=hGwGcRNAY6z3nEOXAcPO/GTMblUWuls97b52uwcWv44=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BGRfcqLk1gaJYK5H7MpWXiHsXkKPHWeA4b8Fy8Mlc/ddOERXYSYPYNgF3cDEcQmWPlp5UTYP8Titx3YksmjcA751ndDB3I19ISde9aZDS4QkwE7QSkmk0LDk1zP1RM++9AGfEfp0ROyupaKqiJfMQTBuZh7ILSnDs93NVaFurnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=L3Rb+7AY; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="L3Rb+7AY" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-a2f22bfb4e6so72472266b.0 for ; Fri, 26 Jan 2024 02:00:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263236; x=1706868036; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NpWk+gUI1kF8qhFNhkLXzIkhTvjq9VbD2XVbc33Jwiw=; b=L3Rb+7AYp6fseBIkpUcMBpYwGDIlM7KgZlw/F+tFHj9xuDcCu97euCi4HKId2rMwOC xzr3Z7L3sUbO2pVmt8SONMk/h+zicQyfJbyicjSWQNWfYdhalhEGc0a/3ZaB/Va7Kdkp KCDCYXp7y8BacIaF9mQI2ZLJe4BPWxRlJx8HFxLWyCuE2loGfOHskSiuBmJFOqOvCRdk jHJDKShwyF5H3v9/O98AfrJOOOqgOxIfYtGsn/xu1jCdvkQLp6z2xxD9bUHc++FIIEAb kRiIgJr9XMR8qhbhBOY/qXE1i3B0e2CAyGoqpjHzmPJSFlda9IhvNXqrwWhdw7T8zVU0 +XTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263236; x=1706868036; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NpWk+gUI1kF8qhFNhkLXzIkhTvjq9VbD2XVbc33Jwiw=; b=mS7avKUzxPgO8VXgOA4YJfYkxE2e4/MTd6lcswtTwzKRgRrNLVqJ2zF3GpzcK3nxLg PGVlsoRlwAPPdhljwOmcr7CswFi0H+ekIkQqU/8/kfchoq1vYfsyXxclQ0OO5UutMiys 7k+LPzovwHxcdYtXERUxYBxuKMwloyxFL22Yj7iKMS001sisf+OijbPRaxlpxKeC2j1R 1Qg1ALOqU0q71tfg4tBDfDjGcWhPY5lTEsrn/uegyXBaQ4ZoDyxZuX4shFOFmZUQ/hqm dPfGMF/1MGmbtGEAirdiPem3ctXw4wkQKr9G/96WUxK1tq/tUcajHNduHjWTjOlystZO HZKg== X-Gm-Message-State: AOJu0YzRUpRcMQRf0GE8cku2i1vxdahje+H/cXIYStMysgU7gImuiRJ5 EUGZZoUeq538m88mvPFRVyRz8XFyucK024jVkQryplwy4EDwHAtdF6ija3fEvEA= X-Google-Smtp-Source: AGHT+IGgnS007fuhkWbrHOY8Hm5PLg+DpOviLmtfweXOzv1lV1sobHAbMGr6R5wK3iXJ1ewfKwLObg== X-Received: by 2002:a17:907:1115:b0:a31:29fc:6ef2 with SMTP id qu21-20020a170907111500b00a3129fc6ef2mr992557ejb.41.1706263236319; Fri, 26 Jan 2024 02:00:36 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:35 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:12 +0200 Subject: [PATCH v5 01/11] arm64: dts: qcom: x1e80100: Add IPCC node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-1-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1078; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=E0uYI6lqGwCrH+pcr7C1xTC5esqpTyDE5ExbYCu6A1E=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K1TYBkgTqwXrEbqeXg+Aim5DHszSSJjyvT/ vI1lD8swOmJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCtQAKCRAbX0TJAJUV VtwWD/9VIqizRIjQQSw+larObbTg/pxfL+o9U624XWEa2/X+wdwFhL7nUWhuZtGJ+wUWQm5nAQL 7bCiKDtmV4mpNHQWAQHIt7EGd02B4ah9nxi+KmMv3/2kiO6/88LyzCI/e9Y2BZMJ3iSk7t/UmsG 80db9iB+I5OIo94D8QD7Vb0V67G39bHqpkntfXCJAhMMB0mxASMa2meG8nXtV7sXhMc2RIAbSsG UZ9y8UUs5fVdUvfSeKgOfEZxPx29HULmPJSf5mbAYTqVP2OvcSdRZ1H1OV8oH6kN8ToGVr6RAmW Lmm7vAT2KZnEy6tRpkGxzrCUYnPPwsuZ6coKYngCQvu9bJtNC71Qwjlv1DZFjUQA3EsXA3y9M3r W0t2HIGPhO8Qxqa0zcz7NHW122BodBVG/i1WhxadhfVftHfkqZ6dzJ4bvwhFJcxEIt3Js8ToRQ6 osvlZ5EzTPvtJMQu14nNDQ6y4gGuaihDmDmUCviB9fNws/fkuLEFPqqsiNu5kbLmu6/RgAQMY6c vutSOA+a/M+IS/kCu6dTFiyQs4XcEmr/B0PNhyd12zchDqNg2YuVtY29Cl09bxUy7vPWl3yjmrW TbQ8XcktUHfjHBOrsS//1TEKSEqsap/pIAImiJjmn58iwYnxqwv/QisTk02Wepp/yMeFqFK5Bp2 sedXaybzQHUudSQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE From: Sibi Sankar Add the IPCC node, used to send and receive IPC signals with remoteprocs. Signed-off-by: Sibi Sankar Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 6f75fc342ceb..954f2bd9b1de 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -691,6 +691,17 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + ipcc: mailbox@408000 { + compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; From patchwork Fri Jan 26 10:00:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 767635 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 659C35A784 for ; Fri, 26 Jan 2024 10:00:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263242; cv=none; b=Cxgxyws06LntLXGYicUiX8AzmH8BAYBpBBdyDb69CGvQPpvSondvtqe19J2MCxWPFq2+2cSuvySS/A2LOOP+RDFukjE3sGOyZ/eJf3b2WGXumN2t5c96R4NMnbY+cBO9P4dJ9V9P6SZbw6XTZiWoqRz1JhKGoltvWWTQFomhgQU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263242; c=relaxed/simple; bh=AVtgRWF4IVOkUGVH/tXix06fZG32DEgHg3PWnXYoMsY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PttFQLILuPGXkpAsDBTv9hDhVBqZnLmzuceJmJP+jI/dTAi+aJ2ntMnHpAfCiZqQKYh8czu/AWzUub0eFmRYL3Th7MewZ4igwePf/n5rSLtj7v1ky8YEdEB33HKrEUAj6gFTI0uIFy2GpHedWSz7j+11KJlkTEddbNY8UaoWzlM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=duVI07l8; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="duVI07l8" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-55a5e7fa471so151338a12.1 for ; Fri, 26 Jan 2024 02:00:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263237; x=1706868037; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MQbi0jsaceor2m1l5UXb1GXMtF9OCnFgnWE+RJJAt/A=; b=duVI07l8yVmEnb8oUYRz8O5fl+LBID9vc/3VKd1vni8S1uCrDrnTQGhXAvkZqewU6S D5VIRYN09xTMFXrotrbfP0ShgjhVY266i6Nf/IXDfy9ozd22MgtB7tpt2S4OcMuGIVgH AylDMYfRDydzd7vI6NAeIpjB7dSKjLkL4ZhmLrmtijb0bfE06dSj9DjnA9T/6tsgqY3N JiRJEFMNxRzWr9yNwT1PcagPITzaIPF4H9kMVRV3shzTz8QIqy+uy6xMeGhESOsRh7sY ZhQ+S3dcnIHZxbH/FQO7bKi9B4u6NbpIHF9yzizXnn7FXGT9FMOSElcOdBUfzW4eyUhS CINw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263237; x=1706868037; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MQbi0jsaceor2m1l5UXb1GXMtF9OCnFgnWE+RJJAt/A=; b=L1cyKWZhNTin0fU/r0gXj+lo4XfqXpI8D3HwqhB90EF/VY/2Irpg2fIlXqeu/F+E9S 9pE/rWqPVif4zaaV7i3aFraWb4X2ZDXd2A7/hXwqjvNFM0F3+ioNvIR69TryGvfZhvcS y4f+y3aIMGX/WHJC790TUYhGu6jgj5z0mvekRw8MtxjLM8cYr7PIznM6L1xnaWt3iiGw vMWgjGsj1ZtH8SUhzYPCT+qStX6+3MVD3OaY60ArJUFDYfO2Cx0wGzsOQZ1SWsiXoFLi kmZEa1Ljp6BhQ4vF4XBQFf5prJBP09mNuZ4RopZr9NkbIDtGwcjv6M/6duZPB1w2C9/P r59Q== X-Gm-Message-State: AOJu0YwlcrxU/mZHuILhkWwK4QCSSzctETwoM9qEoakkA0qGFTS36wkb befJm4SudT9CURSKgBYRuM3pHtLG2us8j50+nMEEZXjzyjkn/ep2iu7n2kC6WcQ= X-Google-Smtp-Source: AGHT+IE3qBN7zrigKY1o48sOXFj6NazOEvWePa1CM8jV4KDsLmnlStSqXIuqgEl+Qb4McDA/yBIewg== X-Received: by 2002:a17:906:fc07:b0:a30:3863:333d with SMTP id ov7-20020a170906fc0700b00a303863333dmr610647ejb.75.1706263237511; Fri, 26 Jan 2024 02:00:37 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:37 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:13 +0200 Subject: [PATCH v5 02/11] arm64: dts: qcom: x1e80100: Add SMP2P nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-2-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2334; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=k1gnvHRfVSoGERtnk8fkV8vtL7EyKZdKEihjsBB0+sY=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K2lod1b0R/2xgXwTJVUjVbgMqCAmpiDfCT2 5MyqFRdtS2JAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCtgAKCRAbX0TJAJUV VnEzEACGzkDeqtek8q7253w9e5rEFdhrcy2FTl9pXQaVExq7zvri1XR2vZHgEEetvENsdYjgapI J4HRMXRn64o0o9w9LaPJ7MCbwKrAlqec01tm17vBNyeOuWfA+/6FMtN/nd55MO21kxDNQDKPjZz /g39aWg8jibd2yy4C4X3AAWXX1Cb6vup6uZWJ/SoiMkgsTZ8uaH0IlUFHJMKj6vVhqaPLjFC4HU x6JcAtAJFWZdfNNk/FD1J7UhmG45n9TlljosaJygYq38PQ7XxOlkRYGLfpkpS/ECftQoY/S9zkR DQap1d+ntk6blseDaam/GXNDYskN8HeqxK13RB8V5MStQMBAw1oSaf2r62tQbYV6eIicfL09v4J LSSOVoVGdMfDlohvvuFSwA+IMID8t9IOltLQQQp3whfi8dXPauJh1qdTQp20R245b+igPuqNhOw AA89id+CjlbI9oPWk4GYnbQ/dHvjgS5zMuCzjxGc6RVeNuEzBf1ZLpHSwNQek/4aOpakB+hl0zK o4xtUShpulRL/9tWTmTv5fN/phxQ6dyNJJ8i9qEyd5eAltAllSdKwSGz7GobiwyHmXVyuwgdK+W 4UB3wpgRGWausAwSjs1IiyXDd5/Kj2zEMmgYsPgBUmEgrVDR6YAt52zTbXqyXDlAMKJmfWS/jIb G3l8K3DdKJ3zCBw== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE From: Sibi Sankar SMP2P is used for interrupting and being interrupted about remoteproc state changes related to the audio, compute and sensor subsystems. Signed-off-by: Sibi Sankar Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 53 ++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 954f2bd9b1de..1210351b6538 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -662,6 +663,58 @@ smem_mem: smem@ffe00000 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; From patchwork Fri Jan 26 10:00:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 766460 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 747FD5A7A2 for ; Fri, 26 Jan 2024 10:00:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263242; cv=none; b=Wh5KjXGr0jrpl3OAjzliAbQQ9xMO+97WMiXmRosnta2L+1KGN0c0ktQDlZpXqiQ/6ipMxdy9ZZuBAWRMe9huj04hs7/aBQrHy7eNU1Fsa5mYe2UG0ew9fzNp1Fs4BiR5mLBSO7iAALHaUdw4Gp3uibXjQ3RypmN0iaEOsfDoqPw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263242; c=relaxed/simple; bh=TcSH6PTQ+XJnw7PPfCZDpuCKVk8yXAt9SaMXMBrCZkA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HCerv0p23bKjall5YFoY3k2wDNbtYpD/TMPoVHkQYt/4wgGS34vi76CDT5Oi59jfoQ/SKL+9qHir7j7L5djEEWV0d1LHCuNkxR9aR8rq/5Mm4WVUJOQoFfT1PP1zC+yO83koSkrM7P5X50bvqH1yhQcotoT4xTtnROHT644+0r8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=s3p4HPI9; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="s3p4HPI9" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-338aca547d9so242263f8f.0 for ; Fri, 26 Jan 2024 02:00:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263239; x=1706868039; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tYDA92LfZ0itUlh8YMaZwnv54pbCjg8ilHywXWo7zrM=; b=s3p4HPI9B4d1cXAZPvM6ee1j8GxOdB9eI2yJRz2ZUuWhSASNYHZ65swKKGCbGcaRY0 c9cvlYTjAnk7hrP2MSZwseHwGP4zISj6UVR0BTcgfHbtidu2JcG9NmUmjlbW6w2+CWys khJux/CngqyUY2VzappiqD9Kk2eu4AFDA3z0syDK5JlhrvZVcNPwULotax1UJ6jToizm Fo6vRCnzWhiCEBxhZLRTt0H421VGP3LlBBsFXI8DjuhbVyzlVUgmPe2YDM6b70mz5kLg r/DqPRKFFKo+J9ouycFLB68tK+ERkQIVGZsj2poWBG44otelEpLGfF/tuD0ekxdLh3GS fEJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263239; x=1706868039; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tYDA92LfZ0itUlh8YMaZwnv54pbCjg8ilHywXWo7zrM=; b=btzD+44mRaAwt2Ilj5MLm5w9KyVoa0l/1jTRS2jcBWVnpFFGnzgdy7fecp6gLxQbDC HIB+i5+YhB3vUfZ30sybuz3aZ29sRbyEsVDLYOQwhIAdE0eyM6/QFUVwKbziLEKfmbqX CrQ5vVXgoTjaYXRLvWO2gziTqAf1PRDgNSpbWZ9H0TTztBN/N34Ue9I7ZLam5WJBC29b Em8CnEmIju1KwcH4QaM8Swr+UxHgSPZRiN03sFYyrHAepmYCmDtbfpBEpsJu9Jz7My4H W4Ory5vyhZaEKvfVbi6GvSgYqh3Qe96EH606j0kNQKJdpupNmNGunGnu4lM9pD72Odsm F5ow== X-Gm-Message-State: AOJu0YyRfMutn2hYNn9doKSHN0Y2+/Lr3LSHxXM9xwJvuKieYAdRUpCh MGXg2lJBK2DZ0ChAyio0GUeGauuQm5uRhWhmljpEOej5vSupY4rzicx/0B5CyiA= X-Google-Smtp-Source: AGHT+IEWWv/d4nCExMUHtpqA/aJuSEywjj24celrCXAl1Bgnt2mFeYuxEb+GZk+LmXItVgkejkpsBA== X-Received: by 2002:a5d:510e:0:b0:336:7c62:9ba with SMTP id s14-20020a5d510e000000b003367c6209bamr346553wrt.25.1706263238661; Fri, 26 Jan 2024 02:00:38 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:38 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:14 +0200 Subject: [PATCH v5 03/11] arm64: dts: qcom: x1e80100: Add QMP AOSS node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-3-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1127; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=Q8J4vtmwt2/riBkSH8HC4PZAyD7bl2d1ez2isASmfa0=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K3nkuAJXVmtKDkvftmuiPxe3YYj5p2WgIxb fGrlnnBPAGJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCtwAKCRAbX0TJAJUV Vul4D/9Cxl6T+2Ggl+PMi3ZGp9FMslPiT3feAS5fL7kvprSlOfBKGDygza/pMkjJ65C8MZdvsBZ 9fSBD84eKS0v/PYqcdb2DGsYPYo2GRj+F/A4go9EmmfG+m4VbuFF4mn2cOeYwcRUNrpiCJz2JL8 MiQBlwE2qOAhYRTHa4XeD6yXaNbc+5h74UX7+uSyfe3PbiNVHyjuG1XcxlF6Rx2DAieLHuFdRE2 ogetuCycLPOeZk0p+dkv/V/3lOSBdVWk255RsS+wypBX5vmF8IwlxNEtXqNUZ3VvvoJ5deMKDPl blGBtOis54eaWJ3GBKMPlVMkEhX3579SuuYawOjOaPFZy4MauZPfv/KSw5YpzooHundypCTY+6p f/mOsGF5qCf6Q9DGOtQjkvgfrqK6AUiB+PpJ0Ca9BHmvEWMzQ0mteMcKlagrcve9/BZTkdo+tLZ JquNOYQljG46y392fO7M1Rk7q0bxiAENF4y8/tkcSZIjcobb3hSRCjQgJC419FIVqoI5fjTW5Eg M25V3qIuAa86lcHgMEyEFqEnjZ6sCo48MUxSwxFNmSTt9yk0WV6c8k9dU+0Gh0h9tz8ClOEupnT YGr5wKXxaxrI7bypaOzonMzuLlYZAOeV6haVYrxTsm340jgl/99PZz4KRLzb19sWvhfoC6TASyf tp1bsO4roHXoPCQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE From: Sibi Sankar Add a node for the QMP AOSS. Signed-off-by: Sibi Sankar Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 1210351b6538..3790d99eb298 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2663,6 +2663,18 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + tlmm: pinctrl@f100000 { compatible = "qcom,x1e80100-tlmm"; reg = <0 0x0f100000 0 0xf00000>; From patchwork Fri Jan 26 10:00:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 766459 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 936605B202 for ; Fri, 26 Jan 2024 10:00:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263243; cv=none; b=HElYrCHj5jC0pX8zPr5ZcUzMKwzgsroR6nXYiYGkCbI9D54NzzN5yBGZyuSVgOcboH5RmbY27gV8xqEh51WzJRaDgzB5BaK77MawHcxjVHrDaLueKDFQfCkIi9GehHk6QJVDEX3KCOS/q4XKOj7s0mteSePwu74rw0WW+eD+f8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263243; c=relaxed/simple; bh=9lrK39yGWz+mMVNX3fo7mSMQqmbiZ6p21a+lgh38MTs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aDZ8PY5/K7WHl22mszjlZtTBEpMh4LgxQyhkMTDHDtczjJyCOHiQELbvwIwWUZbPEY0EQHA+UsyBbF6wvdZq5FEaIg5/CEp6okJ50QU9CHM4PFzN3vuN/8V/CIWVfzq1H7IGbbx7D0BTiep/uJwYfTifkGa72lwluRUcOkQq6vk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=oSsS4Hg5; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oSsS4Hg5" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-a31914e7493so23802666b.3 for ; Fri, 26 Jan 2024 02:00:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263240; x=1706868040; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EOMNM1cIuCUaGhFmJAiF8twDPA35g39fPAYJ946kJ00=; b=oSsS4Hg5tiNdjlELaIW98B1nKkcmFTaPlpNPmegu0diqlsTDZJKcPNnBuBgigkVWJv fRZar/ktnEqf2QQOfNlnaChyP/HcCVJX85s+CzfMjs4cctcyfGSIHneugr3qxTcMMeNr tiU5TDgu2NLRAy4nhL4lzE2VUjcTJRaPrL9mbliYdtxTKyl1dqnU56r0/ZZIXI6pdQRW F2ELBqUPYhzE+VkbF5Nqyl2tb+MhsGd57c3tXyed1miZQaqzclKJOmbL517CdmocJfrX 9qJNQ1qbSIax0uCNiPs8vi/X9UYrIcHSztPtZAZNqbdDgmiMtNdLGOlQ8vKeNzleYp+K EPUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263240; x=1706868040; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EOMNM1cIuCUaGhFmJAiF8twDPA35g39fPAYJ946kJ00=; b=j/Pm4heydlu1R0wt3mKrYyDMCHMHtRoVN2FCcHOLh1xJgxazIfWXelSNNYmQDZ2196 SYVn/IlwZYk9UMWZxc3bBBpYE3E5eX1tGE7Em5LHrayVBI0PDyl6a6qr+jNoWddbSPvh f97aYwjsulyT64wynxsV7JXlGe7dJvq/BWmsyKsddGMTxiAPs05KoCWt+sIk1arLC+Q5 QrZlrIds81WgWJfLhZoAn8S8yhvHfD0b0y+P5dA+kxeC9e6c1vHgcDKrCuq50yhMOFIj o+nDnlC63FgsowUJBKqv+u1jPzqHFaH6/mawOhS7MYtuEdZlAcf3zckopDrgFnJFrJ5R p9Vg== X-Gm-Message-State: AOJu0YwaTukEUAOpGZRnhlBEET1ygLG84BOWxr5Lkir8KTFSJxt+Y2vd +DrcYMCArlLbQ3XUv4ir6Xpb6qMBkPf2cY9nkDo8TiJnoDlMPztaW5kUFg1hPY0= X-Google-Smtp-Source: AGHT+IHSuLkgeI7QkxXZVmksxECG2VmFCOGDlb2DX2o1Nrvx1R4dxJ8UsQan0cdBGX9tZomIMzj/4A== X-Received: by 2002:a17:906:13ca:b0:a2f:1466:a3e4 with SMTP id g10-20020a17090613ca00b00a2f1466a3e4mr496034ejc.25.1706263239779; Fri, 26 Jan 2024 02:00:39 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:39 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:15 +0200 Subject: [PATCH v5 04/11] arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-4-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3499; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=RU2sVakWDTM6FIOT1mP+9fDqahd9wnJzAdPildXmazk=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K5hG4IiZx1wFkmb8aGH0l3jcqhrzb4XSnVC KVJEroux/iJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCuQAKCRAbX0TJAJUV VpxEEACktQWla4CcYyg90/64lfyIAzceYv7OdU3+sRNHB0sreUYRIh/1dThfAFB0JVZWBRBzSOS 2aHzxusCvIlVZ0zsPRQ8wy32w10xDDZYQDNCsChp+5qJadlUZqkY2EbU4GlHPf0dFKunT8fNyke E8Pxqy7oW8Fc+78QmiEWLbo6QP4mWyknnPMgi3FrrxBziQPpY/uxTiOwUbo8g4qGzA2tXIW9u49 X2SY4gLOrHWzgXZBup7/LLpxeVBr6DNBvU10T2QRdDWbXxEK1Z9EeQX2gizZeeznkd5ryeeSgUr r0kHB8bgdQ4HmPOvn2nNkhu7qdiyLUJrTuuSu4OiOOGuIVpWNmI6PlisFqLg7OJxyuB3C6uRlKx s5YMl27hL0ydg1cbGTvC3/IAlZBfg+lF+Wl70oSXDgSlJuyYDYMioNzlyb1kRWp0jd/sHL/o5ri njXLqj+0l0JHXg01QQRRRm0LYiPfWc+GXCC8GNYIVW6ZdDVAJOsd+BYwqoIktlUARZ6cSQ2t0Me MXCmLkotTWcX7eH8hpbE1z3RHR9ZkhOhBghsOFo+Ge8ygFroYYJYtJG9Ekjk1cnLxoL7ReUheza Bvfl18JRuX57dsQ+ODkZiwSUbesXfkvuP4uPDn87Ezw2AVXOjiYiDIMoIFfh4kHGDknXtNh68um K7lEOp7TOuoAaaA== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE From: Sibi Sankar Add ADSP and CDSP remoteproc nodes on X1E80100 platforms. Signed-off-by: Sibi Sankar Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 98 ++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 3790d99eb298..be69e71b7f53 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3590,6 +3590,104 @@ system-cache-controller@25000000 { "llcc_broadcast_base"; interrupts = ; }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,x1e80100-adsp-pas"; + reg = <0 0x30000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, + <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,x1e80100-cdsp-pas"; + reg = <0 0x32300000 0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&cdsp_mem>, + <&q6_cdsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + }; + }; }; timer { From patchwork Fri Jan 26 10:00:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 767634 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0C4C5B5C6 for ; Fri, 26 Jan 2024 10:00:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263244; cv=none; b=jKMPQsRvkhZY55GrMIIs7tUug20cgrhlL8JTpheO4luTwbgpx0WWhGerT2mVPLLc7ZI1w1tZO91rv+9BSK4kXMDQubemTmqSY3haLejxf9DYOAcLodDmgXTGnAUDpPLMbP7b7T3XSBjaeA4P69aUNcP8WB5hBaE8HZMO3/6Mg+g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263244; c=relaxed/simple; bh=Z42Q6xkOTrQTsmOLrP2Z5e9O464q2Y3rJZ2PkdjxS0o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UkSPO5wVMLdEvRkQ5rfL92mBF7NK2RRqAeDlhpg9oO1ep2EOlvRHHYX2Ey9qMdgK7bq7Vpxw0mFuA5Ha2Xnyg3HfCDN6yY+3aW/K7srhlNMabxOnOK+NsDDgMCsk5kMnicGd1iE9ETPWnxMRlzRxJrOrhHxMJnRZofHAHs6qpbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=d7YvYV34; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="d7YvYV34" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-40ea5653f6bso2934175e9.3 for ; Fri, 26 Jan 2024 02:00:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263241; x=1706868041; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+nSUoAEGodpT/nnxbj3AEPT4VUq3C0Xk/xRQ9kzlaI4=; b=d7YvYV34bdx+tYZ8um+e9KreHkK1NpO6GIyEW2TMGwjhPVNXb9gGuso2b+GpuWx3yP K9SX8ZfkUoHJARB2JOZgs7cHjCo3qF62CYfTqvQNKdJrrNO+lH9X/q3Ek8UZ9V9jCeAv 4eEi7R9Slsn+8bV/utXkFp+baJXQJP92be/uI3NQ1pFzRZf7qQwjVMNTvlv0oJfmsp+j ZJa7zFpxunduEFFfAW8udFYXAXMG1MWmNN6Ny+Xqk+PdmGxV0HJjLfgTmiLmAWfy2TTi GgLQpmtj2RWY5Shn8qyOCMQL4z59G83Rl3hyzktHOUuRYsNA0E5Dg2jx8TWx3ASuOpBC F8SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263241; x=1706868041; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+nSUoAEGodpT/nnxbj3AEPT4VUq3C0Xk/xRQ9kzlaI4=; b=DwS/O3AR3MEOPtNWwZTqfDChIkOPBtI96zSnkMAjIlF0/B9KBrLd3FQCaMLQUR+AtB 5b5/qqKndOrO5E17Ilzvt4SgaC0YwaYizxYnGixi1DLyzOvUKZGGnKS9vzS/+Z+mecjx QpxOZqd/EBoeZopOsXhnlipRetbqyGz+s3zmf1cMN9Bp2+3R7NiLkFTuTopQr7u0CUCR ifmwvV3qQeau2JuEdXFAYEOZKesShYrziktN0PQ+HRzhZUGf/F6i++5U0OpxWk8kOn4X 6Y75gmB0MzkX+LT7BX545xHssEUEvxe4ktjLLsyTFin4OyCngbKDqCOrgHbTlO6vVkXd 2VTA== X-Gm-Message-State: AOJu0YxSTEnAlOx8EaZ0KaGMX+XhvfHhcP5lZiZo9tLbMQPp/UfVBZzu /wVaJObb8VM4pcZHS1g/uP4r+wnamiyn5mTYIvaieYRsb34LEemcld/u9Q9b2JU= X-Google-Smtp-Source: AGHT+IGF0lh/BjMDFjwiqlnPgjhfikFTSXO4GdmEqRz8dfIT3DB12kx4UNfvScOsh5Fxki4u97IH3Q== X-Received: by 2002:a05:600c:3b23:b0:40e:50f8:9acb with SMTP id m35-20020a05600c3b2300b0040e50f89acbmr628167wms.134.1706263241035; Fri, 26 Jan 2024 02:00:41 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:40 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:16 +0200 Subject: [PATCH v5 05/11] arm64: dts: qcom: x1e80100: Add TCSR node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-5-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=873; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=Z42Q6xkOTrQTsmOLrP2Z5e9O464q2Y3rJZ2PkdjxS0o=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K6dFCNim0hLeFcmf4Sff0uy0/G75koMej3a X9yuODi/5eJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCugAKCRAbX0TJAJUV VmVID/439CcXx93PwIgmZjVpz2rzxQTOTof1jy22jFQr36ThZwRBwDVZFrtNDPdhwboUfXOfgv4 KMzF1JsuMaUVRyHhFV4t31s/WqbwZDViHNkbLauhmPpK2IeO00IuTouNj3cdpNxCq8B7KxME4uJ t5hjgjm0lpwREBUVMmojJO9dkptzRTjzwpZCsCPYzP5eLdKq2xdQn9QkiTvMMdpITEJx8kWG2Em bi8YLRQFiTzeykGgP4nZbUP04l+l9ngiFJtyzo7Yt+tS2JXOVpjV28Mlo7ipeIsgik/fjpOLsBp lSKt3Z7dX7mgTPnbbl2w7+EadxL7nM4yomTxX1JUrFBzZPo6EP3vu+ilrNiTlvwJPViNZurdhD+ 6dJy6Ok8AnB4q5py6vQ3hBIat2e8/zFqu6yJsmKFUOAZH6Nrn131lxvsAGPgwPvYbzBpo4tK2Zc +mEG2FyFxjyAUcf58vd4EGJatyibJJdM5wQjaUezbojnMHpLpwX5fI/8QQ7cCerIpNF6L5efIlW kATfminZl8gEF4GM346L7TC9VG1SmZIMHu76+CcNqWfAJNWj/6QdqiDbMsnYO9CvSyP8Tz1F2Hb jc/bgxmyGhe1ayl0+E3uu/8hFqYVCImSEYY4U4cexkJvL/bVObGAInM9+EQA9c/j9FxWXVKNQbP n68y/rEHzH/h8zw== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add the TCSR clock controller and register space node. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index be69e71b7f53..2b6c55a486b2 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2606,6 +2606,14 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + tcsr: clock-controller@1fc0000 { + compatible = "qcom,x1e80100-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + gem_noc: interconnect@26400000 { compatible = "qcom,x1e80100-gem-noc"; reg = <0 0x26400000 0 0x311200>; From patchwork Fri Jan 26 10:00:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 766458 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DF1E5BADB for ; Fri, 26 Jan 2024 10:00:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263246; cv=none; b=QoQNOnmlyls3OjQk8AdJCV7vDKPLZ+9i2hm0iZJAYXG97ArLczOiYpgB5I7GWBhqCCj71E8Kmjt0Bub33UBUxQyZggnGf86Yboz5c+5z8RRgzGxsXxNw1BKjyuU9L2tlP1Dm7AjALd1hUTBkZsqaryvIZR7FT5oKygUFZcxoY1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263246; c=relaxed/simple; bh=DshW4j3Ktyit77GTVVUiuEOOwTL+lBbJ5E5pv8ACsYI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ri1j3qEdfwltvgVpMaYaEG/Jz2IkKMlmFFDtCLDUiVh47XG5kB3o2myBaknwqpsQK9JQc3KNPQoOmNQV8E//4HbQ42/9e6D51ECnw5bdMJm9pqfYYiQeqBHStjar+CGG0EI12r29TDc0yipiE3Hjo8zjr0LPl53Zq8cciQppsAk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=W55Ko++Z; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="W55Ko++Z" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a29c4bbb2f4so16802966b.1 for ; Fri, 26 Jan 2024 02:00:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263242; x=1706868042; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Zh7j3OqaaRH9Np+0YzNoUQKfCzodISxdPy07TfhXVjI=; b=W55Ko++ZOqgVtN+uAM8n5/b83X2ywUJUWVbf7PM5RkICdEfpt6uqM3m6QAPIFou3+2 XRUxW9NJbmFxy/Rj2QXU2dsVqMYctaDYoxO/2/T+GxxwHiOkSzCp1AQbu0Zaqv60FdOW XkD6l0k0E7dSPvYPhH81HPWdZVabeCjw75euvNKwIVAvmIDF+sgVQdeVDahef+wPYY3h bQmPz7qhay0vi5Nqin1tIll/56Eno+ylStjD1MAtoXVxlgOGU+KALRzsQH0zbDlzBswD kPnHV98B2qSTL69b9XhSssySnMG0u1rMLG6/qt/lNbaixITX5QdP4oQhD8FH7KR21JpL 0oNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263242; x=1706868042; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zh7j3OqaaRH9Np+0YzNoUQKfCzodISxdPy07TfhXVjI=; b=YoIceWo6CO1P1iZVpjwVt4XHhAzcYpAViGd2kAcMZlX8vmM1FpWZwbOOZoU8hcWCm9 k690FsCeKzNb8yMIh1xA64Osugj3BdMmHCI8u4GmYN/AxrcXi5dJWGQcFy5aS75jF+io o1Ppsme6ds8xZsJMZ/VQ5eHl15xr4OEqJfB3FkvAAQIWpQ6nWU55Wzb56+GWmo553U69 ihc+R0XuokJIkMcZAZqbcJQzAliGcYElQNw0A9/OBIKaLwm704/F9QJslBEh2fjtdunZ g+YXZ4xPRhImklOyr5nuyX3ymwvStLun3diq3qwLc7yi8tvv11eJxUpc4qPFkAf835qF Tv5Q== X-Gm-Message-State: AOJu0YypAyk5OQvBnbCGvE0or31igJBNr4ZbH9KRKh87xVNG78GqBw1o GW8mVqMakO3eOz6TTgoUrYV8ZCrT/vMRv9m6c/Nrojz76TrXaQaNmpEphZLii+gDffS3crMVcmA B X-Google-Smtp-Source: AGHT+IEmfcqIpYafZ21tgrU9dn+5E9kir8ijdUpiL1X4GWihAFXlWLTj/kkEiBDWjReqsMa9p57afA== X-Received: by 2002:a17:906:e090:b0:a35:103e:3619 with SMTP id gh16-20020a170906e09000b00a35103e3619mr32565ejb.32.1706263242205; Fri, 26 Jan 2024 02:00:42 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:41 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:17 +0200 Subject: [PATCH v5 06/11] arm64: dts: qcom: x1e80100: Add USB nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-6-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=14263; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=DshW4j3Ktyit77GTVVUiuEOOwTL+lBbJ5E5pv8ACsYI=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K7Giw68am0LdKiUExT5/eiMne5HRDE1HsNu C7WHvRgrnaJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCuwAKCRAbX0TJAJUV Vo60D/49naVkteH9P4FU1d9dF0hnk7jdFl2jFDrMoM7EShWz3jE8nDV9bI/VJ6/ScXiV/RlSUFq mmgdv86jbyfoF5JOkxdHQ5qhnVvQY4RISqDdJYBRia9Vvf+h7Q5lJZ/2t64V9ECHoQK+zPPqTfr nDn0y2JiQhBV042K3CmnZqU9dDAtTBd1zoNjjinJ1vT7XYnOCBA/jnzKc85JhOeryCM12qj5mRC BgJIMaCTbyobwY9+f6KfDx5c/Zeo2gbTXOCwSHwyavRPe6kphiFkpLdk3OigIAJ73BFw66vozOM WGoGOHP/xYnu5M2xexLi0c9ETgNOxzshSiGcC8vWbb73iGeIqhArGSjmDTz/wTgos6hhQuk9FnE UsSnECHCKhsnvrgSGfdf7gW63i8SGwYmbG+aqDEZRRxwqhLPNBiBuUs8bhRwxgOIZpZ/nHZsFvb 3bhlWSS9/R6Zt5U8wuTc2fX3/Vb3W9b8uC7bi+4Iwi7FsIOM11e7QjbzmcCb0XfxwZzbmUbCC9D KzJIEZcO4Y3qquRRDJdbcikKDWHJ1OyRF6F7kdVKFARiuwyGjyY39Udb6Ir0X2lnx4pH1G/EsWP 0K5lCTL+tlmBAEZK1aFgXQ/VgQgIVnemnoa407vf5Mkhe1OOROPwLDBkCm/Je1yZJfXOgbM8XEK CW/CMYtE46G75QQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add nodes for all USB controllers and their PHYs for X1E80100 platform. Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Rajendra Nayak Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 453 ++++++++++++++++++++++++++++++++- 1 file changed, 450 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 2b6c55a486b2..ddf2e6e44e7e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5,11 +5,13 @@ #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -734,9 +736,9 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <0>, - <0>, - <0>; + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; @@ -2492,6 +2494,126 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, }; }; + usb_1_ss0_hsphy: phy@fd3000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fd3000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_1_ss0_qmpphy: phy@fd5000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fd5000 0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_0_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1_ss1_hsphy: phy@fd9000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fd9000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status = "disabled"; + }; + + usb_1_ss1_qmpphy: phy@fda000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fda000 0 0x4000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1_ss2_hsphy: phy@fde000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x00fde000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status = "disabled"; + }; + + usb_1_ss2_qmpphy: phy@fdf000 { + compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; + reg = <0 0x00fdf000 0 0x4000>; + + clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + power-domains = <&gcc GCC_USB_2_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,x1e80100-cnoc-main"; reg = <0 0x1500000 0 0x14400>; @@ -2659,6 +2781,331 @@ lpass_lpicx_noc: interconnect@7430000 { #interconnect-cells = <2>; }; + usb_2_hsphy: phy@88e0000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e0000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status = "disabled"; + }; + + usb_1_ss2: usb@a0f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a0f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&pdc 58 IRQ_TYPE_EDGE_BOTH>, + <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dm_hs_phy_irq", + "dp_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_TERT_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_TERT_BCR>; + + interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss2_dwc3: usb@a000000 { + compatible = "snps,dwc3"; + reg = <0 0x0a000000 0 0xcd00>; + + interrupts = ; + + iommus = <&apps_smmu 0x14a0 0x0>; + + phys = <&usb_1_ss2_hsphy>, + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss2_role_switch: endpoint { + }; + }; + }; + }; + + usb_2: usb@a2f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a2f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 50 IRQ_TYPE_EDGE_BOTH>, + <&pdc 49 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + power-domains = <&gcc GCC_USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a200000 { + compatible = "snps,dwc3"; + reg = <0 0x0a200000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x14e0 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + + port { + usb_2_role_switch: endpoint { + }; + }; + }; + }; + + usb_1_ss0: usb@a6f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 61 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dm_hs_phy_irq", + "dp_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss0_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + + interrupts = ; + + iommus = <&apps_smmu 0x1420 0x0>; + + phys = <&usb_1_ss0_hsphy>, + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss0_role_switch: endpoint { + }; + }; + }; + }; + + usb_1_ss1: usb@a8f8800 { + compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_EDGE_BOTH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "dm_hs_phy_irq", + "dp_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_ss1_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + + interrupts = ; + + iommus = <&apps_smmu 0x1460 0x0>; + + phys = <&usb_1_ss1_hsphy>, + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + + dma-coherent; + + port { + usb_1_ss1_role_switch: endpoint { + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,x1e80100-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; From patchwork Fri Jan 26 10:00:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 767633 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4057D5C5E9 for ; Fri, 26 Jan 2024 10:00:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263247; cv=none; b=DDQHH5QgHseayIDgYZwPFYa5LSk0FxR6N4VbXyPaNuso2SU0ECSmEnyKGKJCvv90e4+v1XeWs9Wa0vnq1Tnoya3T6ZthEsrgqTkl0TyPVeLAVSKc7+KgJznR2Shpl0zrH2B0wlN32QZL/L4G2SSILIieBltSDplpIe88yv+AnRQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263247; c=relaxed/simple; bh=C+kyR7l7a6HR2OGK95PrX0eZepqv9KsgpOrW2UZtSBA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Rf2r56bUn7uhwb4a1shuXqUAulJVR4eeaXzV0wSecs7b1Z+wEfJ7hScJFv/mFgFctjvdd4fY+ctCC1lWax2OvS0zYMZHIqVADFHuLusb7wkjcFyXhdDK/68Lywjvzce+ifwmEOJ5XNNugEgHdCQYbUHY/YdH0b17UC72n5ldMpk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=k8HNnxZp; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="k8HNnxZp" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-a2a17f3217aso30625866b.2 for ; Fri, 26 Jan 2024 02:00:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263243; x=1706868043; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=DoLr9okIEwV2u/vnDBp17r8Rcfq4WtHXtpq5Shlfi4M=; b=k8HNnxZp2YMSYOJmhIRrln8TWX7X4p2MCevabd1JVVOeP9E98l0AIoNO5mjczuBi6U BDOcD8kKSb8ptILg8Y9tYMihM/QkmTDhTn4C2CZLJUSVNRWZmqHV2Am4Ri3BTo/QyQ8R yBEILHBCLYY1cvNoItNAW+NcFuAieNu1jXnjq/zDDfcN1vgSkrbhhZJa+XSnfwz8GYl2 1wboqolAXAWL5FuNQ6miiFOcyX+5V/bwoCyquZvZ1RIdIj7DU/0Xnui+i9nwGPcBBR6a CnUvky7ERZdzlmV2sUMag6yQnqBS6rCl+MXnLBz2DiKzlxfUjR2dzaJQDo2jQn0zka+P PTUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263243; x=1706868043; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DoLr9okIEwV2u/vnDBp17r8Rcfq4WtHXtpq5Shlfi4M=; b=kvB+0fotREZnvoPkg9P8Pqd7w+gc5uI5LEaebHgrumLKVjp/sV+nVcDFlvPsrQFFIi gYC9ya1KYlcz6BAGSR5CfZHzVvkmBvY6RORYWM+Q72/M8VuCt3ZvTbIBalRONm/RI1hY 8jldL3QBLM0hCf7OFW7gO9TN1gOu46VoELKVyU4avFwJIc1FDEesb713M4GFz8DOMi1y 1NAag31ucDMg6/8r6jcWp9hmTUH6i4D0BhvJPZRfXuo4/CQ/juy0ehy7OH1rkBdJM5Zv FAbAQ0c1xj5OVV06IWmSXiHNiMLyM4icu4WGxiBS+ohORq8dE7oUZbsOEUONAT6/9nDr xitQ== X-Gm-Message-State: AOJu0Yzs8nQu7sx9/YgfYR7v1BXl7gQvnhQ/SIRH68whQBqHK9kxXjEn XZhgFsvZUkoSFNeCNMu4rDQyUcAa1EA1WhuOjPsYasHsBqillDWp5/lY7HqnVmI= X-Google-Smtp-Source: AGHT+IGK6N87utCu+pvoyvaOtbLf/A7inD+fmad4qsX6qP/9yuS/c0FsYK54+Py6IFrEDbL/ubaAYQ== X-Received: by 2002:a17:906:168f:b0:a30:fb95:9387 with SMTP id s15-20020a170906168f00b00a30fb959387mr1086791ejd.75.1706263243425; Fri, 26 Jan 2024 02:00:43 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:43 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:18 +0200 Subject: [PATCH v5 07/11] arm64: dts: qcom: x1e80100: Add PCIe nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-7-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=7290; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=C+kyR7l7a6HR2OGK95PrX0eZepqv9KsgpOrW2UZtSBA=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K8zUECQIHIBXWs3bpidH/HopHIEitB/T3o9 BsmzDQXTKqJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCvAAKCRAbX0TJAJUV Vja0D/43QRBdRT+td5KKR/dkpFQ34i3mXTAODDzdBB/iUwO++URFynZ8q0qLPqTNX3QI8+30nDs Txp80mHPszl48txCVtQl0yR2ZcB/TN4ssHhzpaXRKPZgv1vDCFBUa4jkJj8vLjsmbiof5grpjLl sP/XjupvWaLhapO25x3/RQq2tIYz8tCybolv8YrHjUykZrIp06dGAb1JzyqMUCKaD8Hg5UqGjXF OsHBSLcXEK4EHNPOP3Q085EjeaOS8HIhLgM+QTtMRVbkxi7Feoh7lZf9wgz3rm7HB5l/8mt7W78 jrW93tXZPnIVvxUCpvf2+ZdvsU1N6JX3UPxY0KAU9LqESSIp1UYP6qLTGJmkAINpDvYv4sEP8T3 yCxgYWOG8SQ+jGqS2Wv+gDcWUu2LeqpCqfH2p8eCFuenUi9sScI+WXSh670tEez8FYwNEALCFo9 ezvmaESrxRl8rS4hi4DoSt7qX1u9E8tPN5gYD039PmAQEqeevP+bfUSy6mZlH32lzxJJn50nbkJ N7i6RBX4YQiAdvTuUlEB1AmVF0wi7MV1k8u7RRpZKY8Mpv7uKci9CqIPSE6kJJ1IUnD68JkajBW iitfjVtuqYIhunIqr3im1dp2ikDg5JC7OcJbGohm9GQVp5FyCWqPDW8O2I8aQ+O9nvu1WW9Xl5/ Q2wR2CfnXD0S4lw== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add nodes for PCIe 4 and 6 controllers and their PHYs for X1E80100 platform. Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Rajendra Nayak Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 214 ++++++++++++++++++++++++++++++++- 1 file changed, 212 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index ddf2e6e44e7e..b06577b66a86 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -732,9 +732,9 @@ gcc: clock-controller@100000 { clocks = <&bi_tcxo_div2>, <&sleep_clk>, <0>, + <&pcie4_phy>, <0>, - <0>, - <0>, + <&pcie6a_phy>, <0>, <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, @@ -2722,6 +2722,216 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; + pcie6a: pci@1bf8000 { + device_type = "pci"; + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01bf8000 0 0x3000>, + <0 0x70000000 0 0xf1d>, + <0 0x70000f20 0 0xa8>, + <0 0x70001000 0 0x1000>, + <0 0x70100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, + <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; + bus-range = <0 0xff>; + + dma-coherent; + + linux,pci-domain = <7>; + num-lanes = <2>; + + interrupts = ; + interrupt-names = "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, + <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr_south_sf"; + + assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_6A_BCR>, + <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_6A_GDSC>; + + phys = <&pcie6a_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie6a_phy: phy@1bfc000 { + compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; + reg = <0 0x01bfc000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, + <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_6A_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_6A_PHY_BCR>, + <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie6a_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie4: pci@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x7c000000 0 0xf1d>, + <0 0x7c000f40 0 0xa8>, + <0 0x7c001000 0 0x1000>, + <0 0x7c100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, + <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <5>; + num-lanes = <2>; + + interrupts = , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr_south_sf"; + + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_4_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_4_GDSC>; + + phys = <&pcie4_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie4_phy: phy@1c0e000 { + compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_4_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie4_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; From patchwork Fri Jan 26 10:00:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 766457 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F69C5D90A for ; Fri, 26 Jan 2024 10:00:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263248; cv=none; b=uuUxc8ANogPrDp1NQkzg/HpsvaM+p1GYo1qgupjNOccZ/xy0r01ogNuYANZ95grnZ0dljte8fR1fjHd+PQNdRtpwc7xtHFXdPPGc0VKas8aw2906mxqr5NU0mwBsljYG7O66fHmlDtCy9CafZh2MwgV8e/lx0f3ryeVFvSyCnF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263248; c=relaxed/simple; bh=J1OkgtEMZsGiE/1ICvO0GwDAFXiRxqpiwuX0XSW5d/c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gYSThFxNGZbCuIsYgw7tcIOf52EpM+S+r1tPqF0bKAGip6jDoO4DsE2egl4jjF1btNlrymW750yegwo5Bq/La7IlqvzxqXjrt+Yson+9Bqnw26LtSCHdLqPS7RqJmkstKT2vzYdi9F8ZdXanXn7dPQQmZXK/9VhPrUajJZr9gWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=chFTsHob; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="chFTsHob" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-a28a6cef709so19190666b.1 for ; Fri, 26 Jan 2024 02:00:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263245; x=1706868045; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ixu9SgGIcETW85Sb8ALOm13sLeF2OVz6s0RBcUfoUDY=; b=chFTsHobvCFPArZoVHWJt/BAuY090tbCWYEsNq6AFmFYg0jgb57gmba8O5ubLMN5KE 11w7fe3sVcUgv7s/K4za7At3nX4igUrfUM5su3abbL4DxUIGFKTb14AknLInlK7xdirG g+wEOSzqqBXkfFkisPmbfFVsvw3FqwKW+PAYA96lZgxpx3kBqjY4Wvdux6+wiRIf474Z eK28fJkFJPSPmdQelAVNOLt6xiDofD8rtfi/M/eK5hRzWf9wiVL/ajsnJ0OLRwqBqbXh bxrvRZnF6Z7GyjKSnfvTt2U5nJmHDCdKNPoaCU/mhrqgFRc33K+sOBMdILZin7VZnFD3 jYzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263245; x=1706868045; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ixu9SgGIcETW85Sb8ALOm13sLeF2OVz6s0RBcUfoUDY=; b=r1MWRmlsRS0vmyUs7aqvZbdTCR8xCr/uNCStVAy1k48DtXBtwJkD8MrZuY7mXcjbM3 E1Apl/xtkee+nQyKh0NAVRl9ov6+7zUrBZKGxPIazQxMdjQyK8hY5Oim2Zu/drIykyEP eC7aLREBb+/DpiImN8W0sXNye8Laz07fhGn0RVCdQ8imtCChieqbgrmh+5TW+5Rqufze UipEmWjkzvtC/Q2sn4xo1GCQPKpGwYDqQV7tfSvLFNjllN3mCAppaW97nPcwAK7e6wIr UM2rAa4uXpDioADABLkWJI1LexF+wzz680s/xzX2G3SEkzr97TLXDrAdn/vfzx72gvCc Etng== X-Gm-Message-State: AOJu0YwytMXc0fkXrRxY7OljAADvbPr5+pHlW68IGopgtZlHukh3oAy+ CFv28yAp8JmNPthKTway8T9p9mi/MDfbSITkEotuap2DpWMIgvvmrRmFPsx8nMQ= X-Google-Smtp-Source: AGHT+IH5lMW5C+oHEoeCi+C4GLP2/p2svUjFGzeed3PfwF1rXz0r551BLACUD1WiVKcThvU3IOyAlA== X-Received: by 2002:a17:907:9873:b0:a30:2690:5c48 with SMTP id ko19-20020a170907987300b00a3026905c48mr512968ejc.8.1706263244612; Fri, 26 Jan 2024 02:00:44 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:44 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:19 +0200 Subject: [PATCH v5 08/11] arm64: dts: qcom: x1e80100: Add display nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-8-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=14354; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=J1OkgtEMZsGiE/1ICvO0GwDAFXiRxqpiwuX0XSW5d/c=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K9uNqcfQQ6QufaMMIA3pseL8oiwO9GbX5Sc 46svGbv5LyJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCvQAKCRAbX0TJAJUV VsZhD/wI9IEp+ipz+OW5oMDYoKNXS6n4mBNNh1gzAZ8WzUKwr01dz75hjd+B93iOT4diw3iHEd8 SkjYtrjSG1QYg3fhda0vYtvBRlTNhz8KZqVReo+UIRAcLvr89pZKg0dhafGiCoreWcwBJTDezdT VhmGyeAaH2j/xeihBsBRdUX7k0kvEpLtnK7hrzVwl0O7oDSAJszAHyJstCF//t3OMRz/FygDQKu ZQpFPtr0iA1+IO3qcbgXI1/105mIzJddh+y0N39yhCuhqZdqn1mxyimh5QPr1twg9HVVd0nDDMO UZRNOncfQGReQT6XUoAf9OZbMeNXc3pf1Mks8yCgCVUuUn5qJkm6eRcTpGFf13l8ijhD1DrMM+8 7JPYDc7W90uyJDkRH1+ZuO8J5/vl5+93JWLH70b8gUKnbUEhSKVhqnBofe60n8ZxzRbrQ4OP8mv D349YOWGi5bQyje+GeHGfbYmyqCnzW7ccRYP4kuuOenRii036e14UbG2FXdhhmZy0LezfN7iocU hEPWsdvW7PeYTsniVoPRhM79MDDd75iUAI34vi2/b7hWuaosD5avDoagHEMpsG2ZDbPxmcxubv8 FtSgCrdzK5ZjjkvwuaxM5KGIDZMj2hDd4q5sJa2y+J3cQixC91CuOrIIlZeLn3vADiiuCLJiOod y+JFHsNFcF7oS0w== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Add the required nodes to support display on X1E80100. Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Rajendra Nayak Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 519 +++++++++++++++++++++++++++++++++ 1 file changed, 519 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index b06577b66a86..282901dab265 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -3316,6 +3317,524 @@ usb_1_ss1_role_switch: endpoint { }; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,x1e80100-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,x1e80100-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,x1e80100-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&mdss_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@ae98000 { + compatible = "qcom,x1e80100-dp", "qcom,sm8350-dp"; + reg = <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae99000 0 0x400>, + <0 0xae99400 0 0x400>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp1_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + }; + }; + }; + + mdss_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp2: displayport-controller@ae9a000 { + compatible = "qcom,x1e80100-dp", "qcom,sm8350-dp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9b000 0 0x400>, + <0 0xae9b400 0 0x400>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp2_phy 0>, + <&mdss_dp2_phy 1>; + + operating-points-v2 = <&mdss_dp2_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp2_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp3: displayport-controller@aea0000 { + compatible = "qcom,x1e80100-dp", "qcom,sm8350-dp"; + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0x600>, + <0 0xaea1000 0 0x400>, + <0 0xaea1400 0 0x400>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp3_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + + link-frequencies = /bits/ 64 <8100000000>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + }; + + mdss_dp2_phy: phy@aec2a00 { + compatible = "qcom,x1e80100-dp-phy"; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xec>, + <0 0x0aec2600 0 0xec>, + <0 0x0aec2000 0 0x1c8>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp3_phy: phy@aec5a00 { + compatible = "qcom,x1e80100-dp-phy"; + reg = <0 0x0aec5a00 0 0x19c>, + <0 0x0aec5200 0 0xec>, + <0 0x0aec5600 0 0xec>, + <0 0x0aec5000 0 0x1c8>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,x1e80100-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp2_phy 0>, /* dp2 */ + <&mdss_dp2_phy 1>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,x1e80100-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; From patchwork Fri Jan 26 10:00:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 767632 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 803135FB92 for ; Fri, 26 Jan 2024 10:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263250; cv=none; b=bwWDt37gGp05lY7/CVEbCuHeIT8ZHnx17yGUKyH4JJGack9sD+bOOUg5MvKB61NbB6xRSIdfkO6vAEW1oRuA7MOAX3HPb0fUSj5OQ1/sBitcCnm5ev5gkW9q7SYkTVCLq4VCjEQUnXlT7+bXlkNDFu79Ja8W2kzPkUCVRxoRHdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263250; c=relaxed/simple; bh=ps2ITLtb+wnuPxzAvuaCM3IjDOmZRmy6w8oxvg6tWw0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hnPF/XxhbJOqiFuci93mm5Gc6PppJ6Mxidu4BxF7oLib2AYOdC7+xbLnyrLGFNa0TKYqYsG0Jn0GuYxYDSQ2fiEerN5bJYzEiIjz+p5z7cvF2BspgmhCMy7EuM8dc3R2H56f1aYjdMs3TsvdeE8F2IGhxMOCs7q3ycnEZXWoyEo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ilRto/tD; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ilRto/tD" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-40ed1e78835so2756275e9.2 for ; Fri, 26 Jan 2024 02:00:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263246; x=1706868046; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ro+Hb2iobKdmEbVL0if24hsgyW86TfrhpfzGCL1Ai3A=; b=ilRto/tDc3IexG4tw2pN6J7+l8izus+SsYYiVdywsUebBEAjrmiy+N3vF7fA9Bh9c3 EHj0AKvg1XGma8NFIP/nUkBd2S+DNFB62f7BRqZ0K28rHCRgjeinG9lIVpr9999zhUkh svItuODzWoiJioGL4qLsZGqi1GsU9COqNdvwHAh6O53XxHFo/X+DfsLFT+dP5UNO1SCe 4zMzG2ANYTINweTb8PFpDVTo/ZAFrWe03mxi2Ri2cH96d1g+fRdXo1LWmT1Xe3ZC30jZ VT9YYtCSc5VdlyDxWwSKhTofNFe6Zo8qCa9jk4/C4FQAF8DGxmnvqBLCs0jbd7K7nf29 PLbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263246; x=1706868046; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ro+Hb2iobKdmEbVL0if24hsgyW86TfrhpfzGCL1Ai3A=; b=Tyes6kGSviewMqWKWlmc/N6o1ifrjTdkgwE6fo3XzcJ/9YB6wIeWPiY8MIQGHAGeBU qwPvF6ibMkCO6DR8jNWpRnVHTwg/MEu/KRsCIW1j+YsuBBw71jxsClfGqD07cy0TRHFs nA6MmfdKFUP94vYeDPjWM7mtLzZN1bNEy1IDi9oWoAe6PbdBP3I+JusWu041W7HAxBSf Di11Yr+1zOtGKRBxy/7iGRRnpgebnD9kODN5/njrg2zd1Fnv7Xf1OUWxyHZxa64UJiLr WHnnWVW73GEE9O7Wbq7w9TxujTyT/gogxIMjiKfxh+rS0hhLf9g+sneYX+TYuDEC9l+Q 9Z5Q== X-Gm-Message-State: AOJu0YzfzZX0DKUwLSiRTnD6F9btZkl0MzBVjhUS3u7gLhostxZRUpdJ DjFOXvp/28zd+lZ0vb+15JdG3ft+mNYNnCUVIj+xFaXn0ueEKWunrsWCWKmhXJY= X-Google-Smtp-Source: AGHT+IHVoAb9yzLAsJQZXOv6V6OdxEVIPo1B/6ctTYkTh01MlkLnWCA5cntyxhtdou5bf2h5YXiKdw== X-Received: by 2002:a05:600c:1d07:b0:40e:51e:7295 with SMTP id l7-20020a05600c1d0700b0040e051e7295mr640360wms.82.1706263245813; Fri, 26 Jan 2024 02:00:45 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:45 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:20 +0200 Subject: [PATCH v5 09/11] arm64: dts: qcom: x1e80100-crd: Enable more support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-9-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4648; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=ps2ITLtb+wnuPxzAvuaCM3IjDOmZRmy6w8oxvg6tWw0=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K+czcZNS3lD4y/7Hy9uMx4Lc3Dk4r/itrsY 4+TWMvhmkyJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCvgAKCRAbX0TJAJUV VnsbEADEErWAWyuSqwXr/J+oVbDTRi5w2sv2uep1I0fRSEShd+YuM16ZBic6BVUQDIWx7h+jgoL yPY+7zSE3YyAJHzewcR6DATSIqr7fKc0dmR5jpvS5impkM6d94tsEkqFA0+xSCKabSyKL+MmwVN 7XY3B8Kbq984hmo5JIBr9W0CqIY9eOQ34ugW9WD26Y3P6ZxFWpzfzo3c4d6zHgC5i558nVVzo1y mqha7N5GEqvqr40BpXfTIt2oOeSOudWj7bPSF8yGjX7UA6NrNHoSzv/rP6iP468FaqsthdsZg72 AOFwDRhSOfaTCPNaaDwIoyhNGP1dG8bi7/tcxQPW+S3la1mdYNdssGDvub9/9SH8PA4xmFthLjb veFGkFefI54DHMj1eCvN1VqlxLgZ1MAzv83JKTnG+ORnhDx+8CL53rVh7v2TtkqrQGdVxyP5nbm m/IfRNLmEQwkBdZECTYsmANSwM99/wK/Z8a3nWjVx3uS/W2/wdJxkkKZHGLq49It2ZnQvomi2tq avmV3Tqa2qQZV7ZLc2mj2wDy65f5ZqxELaASXeTFHUt9IaiU4nh7KE5Zk8hHSEPLpdX2TcKMMSU +Cl5kJjLO0kyf7t6+DnSFkJxNtZf4hYFuKGdqV5RtTQCod9zasxT08yXlAs3Jl8/+09DlWNr9Gj gwfBmvhUGL9ZERQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Enable touchscreen, touchpad, keyboard, display, pcie and usb support. Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Rajendra Nayak Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 222 ++++++++++++++++++++++++++++++ 1 file changed, 222 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 7532d8eca2de..7e7cc8e43f87 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -401,10 +401,145 @@ vreg_l3j_0p8: ldo3 { }; }; +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + &qupv3_2 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <34 2>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -416,9 +551,96 @@ edp_reg_en: edp-reg-en-state { drive-strength = <16>; bias-disable; }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; }; &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; }; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; From patchwork Fri Jan 26 10:00:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 766456 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE0855FF1D for ; Fri, 26 Jan 2024 10:00:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263251; cv=none; b=CkowP3UO84y7QmGBPnLNWh7MvQ9sl6v8MkMg1SuPZrMfRql1LjGnoK1/OeY5Kfdb1J6wPaZI2iMKIo5s+6sJ24lWV3lOK9BVQxEePU8nBFH3BtZJBysfBe1Mg9CtjoAxt81yhwwUJBOXXnjxhR3MdncMlHesDjnmwXDI2fM33Tc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263251; c=relaxed/simple; bh=b5me84CBLvNcqpO40KkAROvLnJP/DZ8uuhWcZAxxBlk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fAtwUp6i8N15UTxGuVFXSDltqUkIIloHaYtiMGrj76vcrbe5AmtBN5vzqh8nhAgB8bDQ6R9wCBWVrxu6muocAyKsLZRhwDjYhbYoRe2M2hj1rnscr7D9ZSxAY8P927LjlO/miJ+HZj/AIMwdhNkSq2x5BAQIFw2k8GHXX0V+MMg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=kLYCHBAg; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="kLYCHBAg" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-339289fead2so207462f8f.3 for ; Fri, 26 Jan 2024 02:00:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263247; x=1706868047; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FHRWIZ6AIyJhvIjYmGETHUbdnTVzo35SA3ucS7gN62w=; b=kLYCHBAgRAfNI8f97sAZDUONXZuiXD/b9CjY1IYWsT+Bj5y2s5fedQbR+jLAHjhPpE 8pLh1ynqpS400B6XLoRhj0BsIBQyEBqCiTcp8ZLgUhXHsXGWUyqeHCp8UaJ7HLaraHVw beUOeSwcgs556ykSm+i9lvFiweCqJY5xpOpiH3wyHfT/SEj/Dc/1lvDYMWWp7xIQISWj hDSznEzNjlZDTLixDM+ABnPyXJtGMF8E4vn2fJXbY8tk3oxBri38J7czxkLfDnVtIG9P eASPGqMGMIaUtF8C1sfwYULmjYqsNpTlPcwDMF52VU9MaFtJI0+B+5cA2WQpnn9qskZc CzHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263247; x=1706868047; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FHRWIZ6AIyJhvIjYmGETHUbdnTVzo35SA3ucS7gN62w=; b=HG1pPrjFiYF6JedpVoEw9kLq2IxKou7o0m7CnWUNtVCAM37HazxRSmTco8pT9J/vXD yvTRrNVdFssDeckZP3wPY1Y3b1IpEEyawU+deDA9Kp35One+B7sLM9+aimqPpzxoeqmG 7OhD0Cmc6ALBIBXzl104e4AlEnEe9dRPbtrbfNh/PDLFCiywHWiAWTrCrNDt3rpFGehu D8QDxesqj7Lck2yaGtW2wgs8AlQta+E7d65A3T8H5awXkXVZKbXBnNLKbZ4Ex7+e0Vw+ 2t9wa8SDnN+PVGfpqpuu1WtpJowEsCdFtGoIxHwd8GCyV8dSb9LA8nkYu66hMpyijE+D 0e1Q== X-Gm-Message-State: AOJu0YwMVkEoKX5vMKT7D/CIhVBGj72zq4fM7RDxTT8nVS31XAkUgNkh d9b8n2X18R1Oxbh1qhtgJnkWwasKcsFN9bXM0djvKaYxLHy8QtIIDcgI1nGNysA= X-Google-Smtp-Source: AGHT+IGApKbZoEuNOWIxn6/v7hwnWpXN4QzFLkiRzV9l+mW3S6kEfn5JbjI6SXrXajypXZoALUr7uA== X-Received: by 2002:a05:600c:3d97:b0:40e:4398:25e7 with SMTP id bi23-20020a05600c3d9700b0040e439825e7mr650150wmb.209.1706263246942; Fri, 26 Jan 2024 02:00:46 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:46 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:21 +0200 Subject: [PATCH v5 10/11] arm64: dts: qcom: x1e80100-qcp: Enable more support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-10-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3993; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=b5me84CBLvNcqpO40KkAROvLnJP/DZ8uuhWcZAxxBlk=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4K/lsJt6H7wxMhDuiVTa7aA6DlbWsbotJ7Qv B1908w71JOJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCvwAKCRAbX0TJAJUV VuVJEACRAzyCTauKPMR4nwNKZF/Z3LYM4TaYFt9MJerwvjFmxAbLOXaTqN8J2E5t8TVt3T2HyKC 2XK/x7ALAYnD1TWYYL4yQwNJ5P8GYR9sAiNMggU4Aa9p2/3QAZ1gDRWueASiSUbx4AxNABTaI1A nOBp94cGbB3J4Tr/SjnTlm+T4UohKpLW6KqxE3rryfUZ6d5JKl7it3Mgjx5w+JukQFvYaacyuJ4 66N7NgkxCWB7RSbuZlbDpXBFc6PXLvbe69SpHMm3DPhywHREzBgkDIGluGe0EQJ3KlNmf2M1xPG Ea+4JQzaC8hBlAdDKoqw8SbgGjfn6RP/Z15115Uo7tmyMBlF2ciDqVrFLyR3twznDOFU8CNmW73 BqB0LhXYGuqS1FUNovYJ5RjJB37uIidsWwjw4fOVKitnwVD4ZA85txC5tzSnh0zJJX1gNz3S6ap pNCPefT3EpFtBQW3wOXdp03rm+ZcfOll61dGXe7latdEdHDTYcDHDpZweBg/6ylu62HH6vfxgW0 1V2Vjueahl3KzlGVkcVeZwxK20IIJPj7pBOAb7A8iUrwkSIUygHfMeWLXStgohEf9GhE76AB7S+ UOGbRuHog0H7Y5og2m4/PNcqnKdPvtiVbL0H0+7/SnRNB6nAHks81RTa+h0tcebR37AaIrrSvMX e4GgBo6ZjTsIjZg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Enable display, pcie and usb support. Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Rajendra Nayak Signed-off-by: Rajendra Nayak Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 171 ++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index a37ad9475c90..8dbf6d0eaac3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "x1e80100.dtsi" @@ -31,6 +32,23 @@ vph_pwr: vph-pwr-regulator { regulator-always-on; regulator-boot-on; }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; }; &apps_rsc { @@ -383,17 +401,170 @@ vreg_l3j_0p8: ldo3 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + &qupv3_2 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; &uart21 { compatible = "qcom,geni-debug-uart"; status = "okay"; }; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; + usb-role-switch; +}; From patchwork Fri Jan 26 10:00:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 767631 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08420604B5 for ; Fri, 26 Jan 2024 10:00:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263251; cv=none; b=h/PPPVQh2IzcYBT6adUPDQ1kM5CKDiAYlzsa60c+dUpCiMcyl/uN99dPcWmtVcQDaXwkDW6D0DL6CnQ4vC+tUVJ4BW75hhWKLCx2xGohnqSHKo3OYRjULswV8jNvv88H8OtQV8tJhisLw7m/nGJBuix4hNwuCZSRArNUN0AF+nU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706263251; c=relaxed/simple; bh=MAe7tKW2o5NmhX/EToIcX2pFwZbjxHgt/coTrFipYAE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FcxMxd9RFygVbkkl6jWRXnXio39YH/5m3RrSfTGKhr8A1T+Xo8Teslzvmv0ZocdTUWUd421liTLDJdVAp2iXfSl7UYxcej5HR2n4vmGc84eSmMbhb9f0JOcM/UvOleK9BAEIX2CxMX/wm0moNguitNCS2nb7xWEdcYCQX8fXuSA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=yFCATLBQ; arc=none smtp.client-ip=209.85.208.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yFCATLBQ" Received: by mail-lj1-f169.google.com with SMTP id 38308e7fff4ca-2cf1524cb17so2144731fa.2 for ; Fri, 26 Jan 2024 02:00:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706263248; x=1706868048; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9LloJ96MTPtfEA9aMbD8AKrSCBSBCtvDbDb6GMMRvUs=; b=yFCATLBQiAq32LXUuCCsZ++SyMOSTEb+gCm/6epn/Xj/FN7Zcy/jJ1z2gXdS0t53bT JE8CCXPzeHKkthXVVOKcJSWtuUUfyCmPDJg7Bov2q3fYaDstmQsSpDIqyww8mYv9ycj8 lSRKYaP4PXakJRBnSV/peMrUEmZkzBl9Lv5vf1zuvqnmBhaFgyomqrg+RR9z0inPOTX4 7TRwExzMoXSWeTGuQgcDcafLjKJKWP60lwYp+5IwQvYFwJIRuG3Q/3UNo59sSNG8hdWF xCIrtrbtQygh06jrY/65rj9oor32EDNGIM0xqasr0sKdJs7E1sN7+X7o8L7h+yazXghx o4tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706263248; x=1706868048; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9LloJ96MTPtfEA9aMbD8AKrSCBSBCtvDbDb6GMMRvUs=; b=UnT/2cVlMiPTRbBHyC/rjYyldElttbl4h1DhDM/9I6lAt94r8jJX5i9x/QE4uYU6hp HH1hfi0R5PUylJeNYehub2A/6I5Oh0PJjMIK0R9eddBzUTO+k40U2ZciJNvKU6Rm6m/0 OBcJgyl909KU9GYyd3eYhHs1vDrPWOqlIYa+sKIbi3HQL8cWAGDGjHCXDu1XMRtPCoCJ 2x0aICW9/zKSRdfRkRQfQwGKI9KJzP7PLTFL/p6IJwHKMP7j1+QUNztFWJm9xfLfWDRo cc60YKZvavkpQd1mfgQu3vcRxxXsa9cGlMIhuk9u3B/xtLxlyMXlCvc/07AqgXLbhCzP 0Z9A== X-Gm-Message-State: AOJu0YxXc1ZjKxfGDgR34GdqyPokoHrt0InVI9kETkqqulWRLordlG+4 UAGdmVO90sdzsG6lCtSumBUxhpHOzWRhs8e3iZWrfCXJnnnW9Zx+GGOa2xYa9877N+nXubV+pr0 a X-Google-Smtp-Source: AGHT+IHIC5hRclS0207cMJ0Qc5Jf0tDD8roSNv/SlzZAZiaXKhdJZr+PKRul8b259K+iPIHCr7WpxA== X-Received: by 2002:a2e:80c8:0:b0:2cf:3037:2a3a with SMTP id r8-20020a2e80c8000000b002cf30372a3amr611092ljg.18.1706263248085; Fri, 26 Jan 2024 02:00:48 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id ox27-20020a170907101b00b00a3221b95ce8sm448494ejb.77.2024.01.26.02.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 02:00:47 -0800 (PST) From: Abel Vesa Date: Fri, 26 Jan 2024 12:00:22 +0200 Subject: [PATCH v5 11/11] arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-x1e80100-dts-missing-nodes-v5-11-3bb716fb2af9@linaro.org> References: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> In-Reply-To: <20240126-x1e80100-dts-missing-nodes-v5-0-3bb716fb2af9@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1096; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=MAe7tKW2o5NmhX/EToIcX2pFwZbjxHgt/coTrFipYAE=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBls4LAf5TSalEJKQwpC9rsMT5vCFZJFRr/ZXjz9 yggapqpNw+JAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZbOCwAAKCRAbX0TJAJUV VoYmD/9dBQh+7ZuG++cQXckQWo0NttFLdeFWB7qmjG/rSfOb3H+OOhXFebKb203AReoHz008jBi MrNm1XlVHlWIacF0keaCu9f07eapuwsSeNh1s7JWcYUvJEAEsfhaoZqneJWGLzLE67BoHZnonkD lyssAGS4o4tBjBeL06poGm4h9v9NwLK6EGP+hbluXLJZZOpIm1dKb5EjwEPfAjyIwRQHf5LBuHa IJZ9ecSGWjHMElwPrbB5dxC2bf1czLW7z4/mCtZ8DMqWujyowXDrtYek11MSW7qq3lKdYPd52fU 4TLR8EJJjicUgFgjE+jNkP+JZlT3iv0pj8qj/lQ0iZlTYLUotMc8KRkm8VvSTS5Xb6Pj678nvUe UW5hw0lkZtW/1tRhQrCVifiQn82DuzvQiP3hhR6JUvsU3+5CYFfwFwlZ75KsOWjCXb5xZdS/RgG RYucaj7RHRLb0wXybUMdeGFNaI8GMFGaVLYwQfDpQEAMECJ0n0qr1fZLVsgmFGJ9eiGGmmQo5MJ k51nrs9bV4TRBbS8UkLHGGQHkO52ZTIIx8z1WWlSj6lz1dNUQKGr4Eupco61bWn8PfieaL+VpJj FQ6YVeLRF4kUNSXawIXkMbJZqeSdS7HTFfTzeKRTOkMpQUuUnxn4+/EzK1LRD5WnRS37Vov920I TadMiDTgmYM4ubQ== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The LDOs 3E and 2J are actually supplied by SMPS 5J. Fix accordingly. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Acked-by: Konrad Dybcio Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 8dbf6d0eaac3..e76d29053d79 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -261,7 +261,7 @@ regulators-3 { qcom,pmic-id = "e"; vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vph_pwr>; + vdd-l3-supply = <&vreg_s5j_1p2>; vreg_l2e_0p8: ldo2 { regulator-name = "vreg_l2e_0p8"; @@ -367,7 +367,7 @@ regulators-7 { qcom,pmic-id = "j"; vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vph_pwr>; + vdd-l2-supply = <&vreg_s5j_1p2>; vdd-l3-supply = <&vreg_s1f_0p7>; vdd-s5-supply = <&vph_pwr>;