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Fri, 26 Jan 2024 01:38:44 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id se27-20020a170906ce5b00b00a349318ea10sm426768ejb.199.2024.01.26.01.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 01:38:43 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 26 Jan 2024 10:38:30 +0100 Subject: [PATCH v2 1/7] arm64: dts: qcom: sm8150: describe all PCI MSI interrupts Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240126-b4-dt-bindings-pci-qcom-split-dts-v2-1-0bb067f73adb@linaro.org> References: <20240126-b4-dt-bindings-pci-qcom-split-dts-v2-0-0bb067f73adb@linaro.org> In-Reply-To: <20240126-b4-dt-bindings-pci-qcom-split-dts-v2-0-0bb067f73adb@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 761a6757dc26..f7f26fa4a412 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1843,8 +1843,22 @@ pcie0: pcie@1c00000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1934,8 +1948,22 @@ pcie1: pcie@1c08000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom: sm8250: provide additional MSI interrupts"). Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 760501c1301a..decb2e5794ee 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2248,8 +2248,22 @@ pcie1: pcie@1c08000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2349,8 +2363,22 @@ pcie2: pcie@1c10000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Fri Jan 26 09:38:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 766464 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9B4C2554F for ; Fri, 26 Jan 2024 09:38:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706261931; cv=none; b=dE9YjDfu3gSvVZRrLfdua7sbEmah07TLP8jzxCDxMgw8D+W1un2Xmdca4TqO6jxhZagDQ5x3TEfvAyihqg89YPsoPDQUUhffCW9Heo1rCSkzke6/+KSed05uiN/0ITVRI+UrKy47btmrdUd3L5v9ooPSoCKA8hEnP1J7q5XNb0k= ARC-Message-Signature: i=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e78c83a897c2..ad65f6b48e25 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1611,8 +1611,22 @@ pcie1: pcie@1c08000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Fri Jan 26 09:38:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 767638 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCEB92557D for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 06f183ef8c78..034c57ceb0e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1784,8 +1784,22 @@ pcie0: pcie@1c00000 { msi-map = <0x0 &gic_its 0x5981 0x1>, <0x100 &gic_its 0x5980 0x1>; msi-map-mask = <0xff00>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1893,8 +1907,22 @@ pcie1: pcie@1c08000 { msi-map = <0x0 &gic_its 0x5a01 0x1>, <0x100 &gic_its 0x5a00 0x1>; msi-map-mask = <0xff00>; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Tested-by: Neil Armstrong # on SM8550-HDK Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 38 ++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..28cae43eec80 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1713,9 +1713,22 @@ pcie0: pcie@1c00000 { linux,pci-domain = <0>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; - + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1804,9 +1817,22 @@ pcie1: pcie@1c08000 { linux,pci-domain = <1>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; - + interrupts = , + , + , + , + , + , + , + ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Reviewed-by: Dmitry Baryshkov Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 2df77123a8c7..942e602bfc97 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2213,8 +2213,22 @@ pcie0: pci@1c00000 { <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2317,8 +2331,22 @@ pcie1: pci@1c08000 { "atu", "config"; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Other PCIe nodes in SM8250 and SM8350 have one interrupt name per line, so adjust PCIe0 to match the style. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++++++++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++++++++-- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index decb2e5794ee..99fad4f1ad2e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2152,8 +2152,14 @@ pcie0: pcie@1c00000 { , , ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ad65f6b48e25..340147582f0f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1526,8 +1526,14 @@ pcie0: pcie@1c00000 { , , ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */