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Tue, 23 Jan 2024 23:36:48 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.36.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:36:47 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:29 +0530 Subject: [PATCH 01/14] dt-bindings: phy: qcom,ipq8074-qmp-pcie: Drop PCIE_AUX_CLK from pcie_phy node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-1-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This clock is only required by the PCIe controller. Hence drop it from the binding. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index 634cec5d57ea..a953ac197dfd 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -25,11 +25,10 @@ properties: - description: serdes clocks: - maxItems: 3 + maxItems: 2 clock-names: items: - - const: aux - const: cfg_ahb - const: pipe @@ -72,11 +71,9 @@ examples: compatible = "qcom,ipq6018-qmp-pcie-phy"; reg = <0x00084000 0x1000>; - clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, + clocks = <&gcc GCC_PCIE0_AHB_CLK>, <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "pipe"; clock-output-names = "gcc_pcie0_pipe_clk_src"; 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Tue, 23 Jan 2024 23:36:59 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:36:58 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:31 +0530 Subject: [PATCH 03/14] arm64: dts: qcom: ipq8074: Drop PCIE_AUX_CLK from pcie_phy nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-3-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index cf295bed3299..6ae6833e8969 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -201,11 +201,9 @@ pcie_qmp0: phy@84000 { compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; reg = <0x00084000 0x1000>; - clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, + clocks = <&gcc GCC_PCIE0_AHB_CLK>, <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "pipe"; clock-output-names = "pcie20_phy0_pipe_clk"; @@ -224,11 +222,9 @@ pcie_qmp1: phy@8e000 { compatible = "qcom,ipq8074-qmp-pcie-phy"; reg = <0x0008e000 0x1000>; - clocks = <&gcc GCC_PCIE1_AUX_CLK>, - <&gcc GCC_PCIE1_AHB_CLK>, + clocks = <&gcc GCC_PCIE1_AHB_CLK>, <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "pipe"; 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Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 2396a457f9c8..77338184cdb4 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -33,6 +33,7 @@ properties: - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen4x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy @@ -131,6 +132,7 @@ allOf: enum: - qcom,sc7280-qmp-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy From patchwork Wed Jan 24 07:36:35 2024 Content-Type: text/plain; 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Tue, 23 Jan 2024 23:37:20 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:19 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:35 +0530 Subject: [PATCH 07/14] phy: qcom: qmp-pcie: Add a comment to clarify the use of "aux and "phy_aux" clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-7-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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Historically, DTs of those SoCs passed this clock as "aux" clock. But, SA8775P passed PCIE_PHY_AUX_CLK as "phy_aux" and PCIE_AUX_CLK as "aux" mistakenly as the latter is not needed at all. Even though the SA8775P DT got fixed, both of these clocks are kept here for backwards compatibility. So add a comment to make it clear. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 9a220cbd9615..044e3c5ba341 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2328,7 +2328,15 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) readl(base + offset); } -/* list of clocks required by phy */ +/* list of clocks required by phy + * + * PCIe PHY hw on some SoCs require PCIE_PHY_AUX_CLK when the link enters L1SS + * state. Historically, DTs of those SoCs passed this clock as "aux" clock. But, + * SA8775P passed PCIE_PHY_AUX_CLK as "phy_aux" and PCIE_AUX_CLK as "aux" + * mistakenly as the latter is not needed at all. Even though the SA8775P DT got + * fixed, both of these clocks are kept here for backwards compatibility. + */ + static const char * const qmp_pciephy_clk_l[] = { "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", }; From patchwork Wed Jan 24 07:36:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 766534 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20F0017C62 for ; Wed, 24 Jan 2024 07:37:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706081852; cv=none; b=M+be/tK6pky/zm4jteNOJ2XNTtfmcUnXVvqnAbXCSLKimS/sjUO1tCEcQiTlj1a/VzQ+rg7eAYYtnL1mX6Syw7ZzoY0HEG4e4JWgM9BWMQJUqi2DkC3swucu7J1OfBVIMj7HsYwt8Pea+VNZQgKsHCMtV8NXBVhLT5IxctgJ7/8= ARC-Message-Signature: i=1; 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a=openpgp-sha256; l=3664; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=5NPwNoYz985HYek6uHJDI/5wY+uuiyXnKa4opvBCJj8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4EVGO3TtV6DQzvJ/PExud2tothVXBlk9nJc KgeDCk+AGuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+BAAKCRBVnxHm/pHO 9ae/B/45By/VPGVbVxv8n0z7xSGfU/JGiMFrTjUS69Gmsob8PF7fxftlTWwZCLkrUgIuJRBzdkb ZkHzrSGbdR0j2Foxfp/j51A4pVzGBC45wverE1WOVAm7SXjE1RiAe+KFpN70Jnciy0gDs0voIsC I8h+my8LE3a9yTp9A2F0se8GWbdtNlTIXQLB3l5n1QNEohi+6AaJMXKXo2RAZ0T91aPbtOmcn9z tkxrffCFt8jriWYRyJB7Nw1aHfs7LoWB70dND9G+MqYRK9dMhufB9K7BXZgQniBJZ9xkoe29Tzt jJRaUqkSIdQFvvfxsXfrJN5i+O0TgUj8StTbu76AE2zXoRtv X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index febf28356ff8..cc33ef47d5a7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1785,13 +1785,12 @@ pcie4_phy: phy@1c06000 { compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; reg = <0x0 0x01c06000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_4_AUX_CLK>, - <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_4_CFG_AHB_CLK>, <&gcc GCC_PCIE_4_CLKREF_CLK>, <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_4_PIPE_CLK>, <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; @@ -1883,13 +1882,12 @@ pcie3b_phy: phy@1c0e000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, - <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3B_PIPE_CLK>, <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; @@ -1982,13 +1980,12 @@ pcie3a_phy: phy@1c14000 { reg = <0x0 0x01c14000 0x0 0x2000>, <0x0 0x01c16000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, - <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3A_PIPE_CLK>, <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; @@ -2082,13 +2079,12 @@ pcie2b_phy: phy@1c1e000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c1e000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, - <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2B_PIPE_CLK>, <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; @@ -2181,13 +2177,12 @@ pcie2a_phy: phy@1c24000 { reg = <0x0 0x01c24000 0x0 0x2000>, <0x0 0x01c26000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, - <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2A_PIPE_CLK>, <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; From patchwork Wed Jan 24 07:36:39 2024 Content-Type: text/plain; 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Tue, 23 Jan 2024 23:37:41 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:40 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:39 +0530 Subject: [PATCH 11/14] arm64: dts: qcom: sm8450: Drop PCIE_AUX_CLK from pcie_phy node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-11-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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This clock is only required by the PCIe controller. Hence drop it from pcie_phy node. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..1e0091dabaf1 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1830,13 +1830,11 @@ pcie0_phy: phy@1c06000 { compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "ref", "rchng", "pipe"; From patchwork Wed Jan 24 07:36:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 766532 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39D731865B for ; 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Tue, 23 Jan 2024 23:37:51 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:51 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:41 +0530 Subject: [PATCH 13/14] arm64: dts: qcom: sm8650: Drop PCIE_AUX_CLK from pcie_phy node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-13-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1080; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=xR8wvtP+QITH8T8kLA9WFdRX9QC0BEnzA8VfMLDLOeM=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4F9I2jnHfAODN1h6LhID1P5M4ffX5SDTNOK tmbdlVDGn2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+BQAKCRBVnxHm/pHO 9e9HB/9IOUcSo3ViZRQJMCk/7G0FlXlhNFCiC5rUFKMDKuWujGHro13gDGJjTczje/BKnWxULGQ xvxbYT108gLh5mEcp90g5HVfToMp1AArsS3Fqnai8z0TkKnd+2dfxOFFow35x16YJnZmlE502Ae gw/DKa8Yi3+H7Pogj6id8NcfMHlRwkwwzBE6psr1YYv4uIIdIlKAqJvtav8irLGgRCHnD+IfL2L wYgrv/PZB13YCBXxVS2lSTYEgTY9HHM2SpVutjUixxncsHPi+v+Ic0I6Wu5T8Y+f2yaBax3w9Ll E80RfnrBnVFBA/a+DyEiXU1+AXBZ1W0D07uUrZBUR2iYa8GH X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy node. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 2df77123a8c7..b31e60599891 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2276,13 +2276,11 @@ pcie0_phy: phy@1c06000 { compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", + clock-names = "cfg_ahb", "ref", "rchng", "pipe";