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Mon, 29 Jan 2024 06:10:09 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40T6A9J0020660; Mon, 29 Jan 2024 06:10:09 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-vdadhani-hyd.qualcomm.com [10.213.106.28]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 40T6A7ak020632; Mon, 29 Jan 2024 06:10:09 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 4047106) id 0B9615001C1; Mon, 29 Jan 2024 11:40:06 +0530 (+0530) From: Viken Dadhaniya To: andersson@kernel.org, konrad.dybcio@linaro.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, quic_bjorande@quicinc.com, manivannan.sadhasivam@linaro.org Cc: quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com, Viken Dadhaniya Subject: [V2] i2c: i2c-qcom-geni: Correct I2C TRE sequence Date: Mon, 29 Jan 2024 11:40:03 +0530 Message-Id: <20240129061003.4085-1-quic_vdadhani@quicinc.com> X-Mailer: git-send-email 2.17.1 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 2wrUhd0eEdoqHX1vfwnWRRKhWPgRdGNk X-Proofpoint-GUID: 2wrUhd0eEdoqHX1vfwnWRRKhWPgRdGNk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-29_02,2024-01-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2401290042 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: For i2c read operation, we are getting gsi mode timeout due to malformed TRE(Transfer Ring Element). Currently we are configuring incorrect TRE sequence in gpi driver (drivers/dma/qcom/gpi.c) as below - Sets up CONFIG - Sets up DMA tre - Sets up GO tre As per HPG(Hardware programming guide), We should configure TREs in below sequence for any i2c transfer - Sets up CONFIG tre - Sets up GO tre - Sets up DMA tre For only write operation or write followed by read operation, existing software sequence is correct. for only read operation, TRE sequence need to be corrected. Hence, we have changed the sequence to submit GO tre before DMA tre. Tested covering i2c read/write transfer on QCM6490 RB3 board. Signed-off-by: Viken Dadhaniya Fixes: commit d8703554f4de ("i2c: qcom-geni: Add support for GPI DMA") --- v1 -> v2: - Remove redundant check. - update commit log. - add fix tag. --- --- drivers/i2c/busses/i2c-qcom-geni.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index 0d2e7171e3a6..da94df466e83 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -613,20 +613,20 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i peripheral.addr = msgs[i].addr; + ret = geni_i2c_gpi(gi2c, &msgs[i], &config, + &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); + if (ret) + goto err; + if (msgs[i].flags & I2C_M_RD) { ret = geni_i2c_gpi(gi2c, &msgs[i], &config, &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); if (ret) goto err; - } - - ret = geni_i2c_gpi(gi2c, &msgs[i], &config, - &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); - if (ret) - goto err; - if (msgs[i].flags & I2C_M_RD) dma_async_issue_pending(gi2c->rx_c); + } + dma_async_issue_pending(gi2c->tx_c); timeout = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);