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Wed, 31 Jan 2024 23:21:37 +0000 From: "Peng Fan (OSS)" Date: Thu, 01 Feb 2024 07:25:38 +0800 Subject: [PATCH v6 2/4] mailbox: imx: support return value of init Message-Id: <20240201-imx-mailbox-v6-2-76f4f35b403e@nxp.com> References: <20240201-imx-mailbox-v6-0-76f4f35b403e@nxp.com> In-Reply-To: <20240201-imx-mailbox-v6-0-76f4f35b403e@nxp.com> To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dong Aisheng , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706743555; l=3395; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=S0DKuiQSDcYtu53JqBC1+gV1zoHcWj4DjQyGEWhlcnk=; b=W5a6ZzLKxqmgK4UssaJWiqZtbRVbEUDCD8H7KWbWha1f+NbQ5XEjWrNPiUMtG+qlAKot4FgiU avdfd5odp4cDwUC8V7lCYB6bgabets7kNASm2B93Fs9hzB5Jd+BaD1e X-Developer-Key: i=peng.fan@nxp.com; a=ed25519; pk=I4sJg7atIT1g63H7bb5lDRGR2gJW14RKDD0wFL8TT1g= X-ClientProxiedBy: SI1PR02CA0049.apcprd02.prod.outlook.com (2603:1096:4:1f5::18) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|AM8PR04MB7396:EE_ X-MS-Office365-Filtering-Correlation-Id: a483c66f-1bce-488d-3378-08dc22b35f39 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Reviewed-by: Sascha Hauer Signed-off-by: Peng Fan --- drivers/mailbox/imx-mailbox.c | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index 656171362fe9..dced4614065f 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -110,7 +110,7 @@ struct imx_mu_dcfg { int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); - void (*init)(struct imx_mu_priv *priv); + int (*init)(struct imx_mu_priv *priv); enum imx_mu_type type; u32 xTR; /* Transmit Register0 */ u32 xRR; /* Receive Register0 */ @@ -737,7 +737,7 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, return imx_mu_xlate(mbox, sp); } -static void imx_mu_init_generic(struct imx_mu_priv *priv) +static int imx_mu_init_generic(struct imx_mu_priv *priv) { unsigned int i; unsigned int val; @@ -757,7 +757,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) priv->mbox.of_xlate = imx_mu_xlate; if (priv->side_b) - return; + return 0; /* Set default MU configuration */ for (i = 0; i < IMX_MU_xCR_MAX; i++) @@ -770,9 +770,11 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv) /* Clear any pending RSR */ for (i = 0; i < IMX_MU_NUM_RR; i++) imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); + + return 0; } -static void imx_mu_init_specific(struct imx_mu_priv *priv) +static int imx_mu_init_specific(struct imx_mu_priv *priv) { unsigned int i; int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; @@ -794,12 +796,20 @@ static void imx_mu_init_specific(struct imx_mu_priv *priv) /* Set default MU configuration */ for (i = 0; i < IMX_MU_xCR_MAX; i++) imx_mu_write(priv, 0, priv->dcfg->xCR[i]); + + return 0; } -static void imx_mu_init_seco(struct imx_mu_priv *priv) +static int imx_mu_init_seco(struct imx_mu_priv *priv) { - imx_mu_init_generic(priv); + int ret; + + ret = imx_mu_init_generic(priv); + if (ret) + return ret; priv->mbox.of_xlate = imx_mu_seco_xlate; + + return 0; } static int imx_mu_probe(struct platform_device *pdev) @@ -866,7 +876,11 @@ static int imx_mu_probe(struct platform_device *pdev) priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); - priv->dcfg->init(priv); + ret = priv->dcfg->init(priv); + if (ret) { + dev_err(dev, "Failed to init MU\n"); + goto disable_clk; + } spin_lock_init(&priv->xcr_lock); @@ -878,10 +892,8 @@ static int imx_mu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); ret = devm_mbox_controller_register(dev, &priv->mbox); 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Since the driver already supports get TR/RR from Parameter registers, not hardcoding the number, this patch just add the compatible entry to reuse i.MX8ULP S4 cfg data. To use the internal SRAM, need populate its sub-nodes. Signed-off-by: Peng Fan --- drivers/mailbox/imx-mailbox.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index 9e89f773d2f9..5c1d09cad761 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -4,6 +4,7 @@ * Copyright 2022 NXP, Peng Fan */ +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -919,6 +921,8 @@ static int imx_mu_probe(struct platform_device *pdev) if (ret) goto disable_clk; + of_platform_populate(dev->of_node, NULL, NULL, dev); + pm_runtime_enable(dev); ret = pm_runtime_resume_and_get(dev); @@ -1031,6 +1035,9 @@ static const struct of_device_id imx_mu_dt_ids[] = { { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp }, { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 }, { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 }, + { .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp }, + { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 }, + { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 }, { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco }, { },