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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id gz9-20020a170906f2c900b00a3515b35be4sm193052ejb.104.2024.02.12.05.10.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:10:18 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:09 +0100 Subject: [PATCH 1/7] dt-bindings: ASoC: cs35l45: Add interrupts Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240210-topic-1v-v1-1-fda0db38e29b@linaro.org> References: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> In-Reply-To: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> To: James Schulman , David Rhodes , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricardo Rivera-Matos , Bjorn Andersson , Abel Vesa , Sai Prakash Ranjan , Neil Armstrong , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: Marijn Suijten , alsa-devel@alsa-project.org, patches@opensource.cirrus.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707743413; l=694; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=yZBlbkJpD1p3nFnJsrg8uJhSz73a9OCV1t7lzOQKRPY=; b=Typ0ntFsRGIVP8WOd06O4OXyj4D/TojGIZIW2/xa8742w39ZZQnOlVwlytnL69I4HHCDQYYQy lMI+CQBwB8MBNUEP7PJV7F4SEkn4v6myBhYcAd5suogucdMY0QxTzUH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= This chip seems to have an IRQ line, let us describe it. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/sound/cirrus,cs35l45.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs35l45.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs35l45.yaml index 4c9acb8d4c4c..70f6c62aedca 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs35l45.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs35l45.yaml @@ -25,6 +25,9 @@ properties: reg: maxItems: 1 + interrupts: + maxItems: 1 + '#sound-dai-cells': const: 1 From patchwork Mon Feb 12 13:10:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 772103 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BDAC3A1BE for ; Mon, 12 Feb 2024 13:10:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id gz9-20020a170906f2c900b00a3515b35be4sm193052ejb.104.2024.02.12.05.10.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:10:21 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:10 +0100 Subject: [PATCH 2/7] dt-bindings: arm: qcom: Add Xperia 1 V Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240210-topic-1v-v1-2-fda0db38e29b@linaro.org> References: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> In-Reply-To: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> To: James Schulman , David Rhodes , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricardo Rivera-Matos , Bjorn Andersson , Abel Vesa , Sai Prakash Ranjan , Neil Armstrong , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: Marijn Suijten , alsa-devel@alsa-project.org, patches@opensource.cirrus.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707743413; l=706; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=q26xy0RgLyg/jgOoRIiuTBV+Qq9VjOt9WLdRQMJTi4A=; b=KYsGSSNWcJwe5h/iFyeyuB0SBVNLU3N7Eo8waXvmIVKJb2YHFeJiNM4EU9aFNIkrtTVvM28tU CKrhnDmIQi2BSI+XWRZ67t5oEwPB5bMA2wPoetf9mZg1Ml+J6b/fBjF X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Document the SM8550 SONY Xperia 1 V (PDX234) board. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2b993b4c51dc..fada660257ed 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1002,6 +1002,7 @@ properties: - qcom,sm8550-hdk - qcom,sm8550-mtp - qcom,sm8550-qrd + - sony,pdx234 - const: qcom,sm8550 - items: From patchwork Mon Feb 12 13:10:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 772441 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA8633B194 for ; Mon, 12 Feb 2024 13:10:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id gz9-20020a170906f2c900b00a3515b35be4sm193052ejb.104.2024.02.12.05.10.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:10:23 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:11 +0100 Subject: [PATCH 3/7] arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240210-topic-1v-v1-3-fda0db38e29b@linaro.org> References: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> In-Reply-To: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> To: James Schulman , David Rhodes , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricardo Rivera-Matos , Bjorn Andersson , Abel Vesa , Sai Prakash Ranjan , Neil Armstrong , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: Marijn Suijten , alsa-devel@alsa-project.org, patches@opensource.cirrus.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707743413; l=1550; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=OOS7lbYOFBWS9cWYXmiccxamzx9nSjNqu+J04bjACok=; b=H1Bcg2rzFfpWZ+ONZTsv+XotMsPZWzH0sPWJa5fy6xS93138s4pZiqOTYI7h7EjM4AclTuj9G +Ermko5L4yxCW2wmwFkyuUOJYChewCVx9fjKmkcNEtaHvWwgWA+efNV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= These peripherals are DMA-coherent on 8550. Mark them as such. Interestingly enough, the I2C master hubs are not. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index b8f1c7f97e48..d696ec6c6850 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -812,6 +812,7 @@ gpi_dma2: dma-controller@800000 { dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; + dma-coherent; status = "disabled"; }; @@ -823,6 +824,7 @@ qupv3_id_1: geniqup@8c0000 { clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1322,6 +1324,7 @@ gpi_dma1: dma-controller@a00000 { dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; + dma-coherent; status = "disabled"; }; @@ -1335,6 +1338,7 @@ qupv3_id_0: geniqup@ac0000 { iommus = <&apps_smmu 0xa3 0>; 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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id gz9-20020a170906f2c900b00a3515b35be4sm193052ejb.104.2024.02.12.05.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:10:26 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:12 +0100 Subject: [PATCH 4/7] arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240210-topic-1v-v1-4-fda0db38e29b@linaro.org> References: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> In-Reply-To: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> To: James Schulman , David Rhodes , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricardo Rivera-Matos , Bjorn Andersson , Abel Vesa , Sai Prakash Ranjan , Neil Armstrong , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: Marijn Suijten , alsa-devel@alsa-project.org, patches@opensource.cirrus.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707743413; l=787; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=kq5j5a44u0i4ZLViq4Vc2kh0Xc0OOLzaeXziNYe3I+w=; b=4KH+YyPNIYKyi1m0IBMqd9biATcIsevmXT8PvZFoSkc51AMiOSoCBGOHDuTdwZFHd4B9pthVR 6L3X0T8uOeUAwa1aXYa1+fwU//8FX/p328x8Ieq5xfqSZC1Ge94bOb9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Like on earlier flagship Qualcomm SoCs, the SMMU is dma-coherent. Mark it as such. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d696ec6c6850..868d48b85555 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3934,6 +3934,7 @@ apps_smmu: iommu@15000000 { , , ; + dma-coherent; }; intc: interrupt-controller@17100000 { From patchwork Mon Feb 12 13:10:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 772440 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A6AD3BB3A for ; Mon, 12 Feb 2024 13:10:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id gz9-20020a170906f2c900b00a3515b35be4sm193052ejb.104.2024.02.12.05.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:10:29 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:13 +0100 Subject: [PATCH 5/7] arm64: dts: qcom: sm8550: Add missing DWC3 quirks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240210-topic-1v-v1-5-fda0db38e29b@linaro.org> References: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> In-Reply-To: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> To: James Schulman , David Rhodes , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricardo Rivera-Matos , Bjorn Andersson , Abel Vesa , Sai Prakash Ranjan , Neil Armstrong , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: Marijn Suijten , alsa-devel@alsa-project.org, patches@opensource.cirrus.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707743413; l=1404; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BYxMMgnfl6Vo3FvICtt90++r+JIBRmHZBJczJMyhSwk=; b=BVfXqO9pGrNZlcLW0yoUdDXyI3lwhL79E0y5sKgoORe9P1VUu8jT9h9S437tWRb7sucOC99Un AjovaL1EEYHB/X+0xku+/Crr4sQF+pNyJPi2ZtBEhDgXAfmCPQHRuRd X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= As expected, Qualcomm DWC3 implementation come with a sizable number of quirks. Make sure to account for all of them. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 868d48b85555..925e56317fb0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3193,12 +3193,20 @@ usb_1_dwc3: usb@a600000 { reg = <0x0 0x0a600000 0x0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x40 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; 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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id gz9-20020a170906f2c900b00a3515b35be4sm193052ejb.104.2024.02.12.05.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:10:31 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:14 +0100 Subject: [PATCH 6/7] arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240210-topic-1v-v1-6-fda0db38e29b@linaro.org> References: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> In-Reply-To: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> To: James Schulman , David Rhodes , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricardo Rivera-Matos , Bjorn Andersson , Abel Vesa , Sai Prakash Ranjan , Neil Armstrong , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: Marijn Suijten , alsa-devel@alsa-project.org, patches@opensource.cirrus.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707743413; l=756; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=MgGMsg8PJAMVkpQQ8WXu4KK3GFUd7QqW2NVKRDqIWlU=; b=omHcjQyuLjkm+7U15GBNGZL8yj2dbtXdzfMhbPh1XOM6zq40Am+Hcqlnla6o2fLA7Ae+BdUTV XcSScpA7kLEBoOeZwRrM+CkmUYtkSr6XbmwfRW86Q1Xy29GfuKwNj77 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= In a fairly new development, Qualcomm somehow made the DWC3 block cache-coherent. Annotate that. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 925e56317fb0..e845c8814fb9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3207,6 +3207,7 @@ usb_1_dwc3: usb@a600000 { snps,usb2-lpm-disable; snps,has-lpm-erratum; tx-fifo-resize; + dma-coherent; ports { #address-cells = <1>; From patchwork Mon Feb 12 13:10:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 772439 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 117543A1CE for ; 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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id gz9-20020a170906f2c900b00a3515b35be4sm193052ejb.104.2024.02.12.05.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 05:10:34 -0800 (PST) From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:15 +0100 Subject: [PATCH 7/7] arm64: dts: qcom: Add SM8550 Xperia 1 V Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240210-topic-1v-v1-7-fda0db38e29b@linaro.org> References: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> In-Reply-To: <20240210-topic-1v-v1-0-fda0db38e29b@linaro.org> To: James Schulman , David Rhodes , Richard Fitzgerald , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ricardo Rivera-Matos , Bjorn Andersson , Abel Vesa , Sai Prakash Ranjan , Neil Armstrong , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: Marijn Suijten , alsa-devel@alsa-project.org, patches@opensource.cirrus.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1707743413; l=21987; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RKTKSpnq7umb+4fU+UBs7880UjfiZvFKMpd6xVM+qMs=; b=n80aZUcqcoyBgIg9eJD2vDXcrnfKyj/yR9bB4HnAHKOhFsfFsPkmtlMJOKVILVrZPktBymQCi 603ICmpAMWZBWkX0yVjbR257zY4oXTCmAw28KK12CeFhyI+tBycQjpo X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Add support for Sony Xperia 1 V, a.k.a PDX234. This device is a part of the SoMC SM8550 Yodo platform. This commit brings support for: * Remoteprocs (sans modem for now) * Flash LED (the notification LED is gone :((((() * SD Card * USB (*including SuperSpeed*) + PMIC_GLINK (it's funky, requires a replug with an cable flip sometimes..) * Most regulators * Part of I2C-connected peripherals (notably no touch due to a driver bug) * PCIe0 (PCIe1 is unused) Do note display via simplefb is not supported, as the display is blanked upon exiting XBL. To create a working boot image, you need to run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8550-sony-xperia-\ yodo-pdx234.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 2 \ -o boot.img-sony-xperia-pdx234 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system \ vbmeta_system.img fastboot flash boot boot.img-sony-xperia-pdx234 fastboot erase vendor_boot fastboot erase recovery fastboot flash dtbo emptydtbo.img fastboot erase init_boot // ? I don't remember if it's necessary, sorry fastboot continue Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 779 +++++++++++++++++++++ 2 files changed, 780 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f7c5662213e4..9bbea531660d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -237,6 +237,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts new file mode 100644 index 000000000000..85e0d3d66e16 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +/* TODO: Only one SID of PMR735D seems accessible? */ + +/delete-node/ &hwfence_shbuf; +/delete-node/ &mpss_mem; +/delete-node/ &rmtfs_mem; +/ { + model = "Sony Xperia 1 V"; + compatible = "sony,pdx234", "qcom,sm8550"; + chassis-type = "handset"; + + aliases { + i2c0 = &i2c0; + i2c4 = &i2c4; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c16 = &i2c_hub_2; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + pinctrl-names = "default"; + + key-camera-focus { + label = "Camera Focus"; + linux,code = ; + gpios = <&pm8550b_gpios 8 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + mpss_mem: mpss-region@89800000 { + reg = <0x0 0x89800000 0x0 0x10800000>; + no-map; + }; + + splash@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg = <0x0 0xe6440000 0x0 0x2dd000>; + no-map; + }; + + rmtfs_mem: memory@f8b00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8b00000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + + ramoops@ffd00000 { + compatible = "ramoops"; + reg = <0x0 0xffd00000 0x0 0xc0000>; + console-size = <0x40000>; + record-size = <0x1000>; + pmsg-size = <0x40000>; + ecc-size = <16>; + }; + + rdtag-store-region@ffdc0000 { + reg = <0x0 0xffdc0000 0x0 0x40000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + pm8550_bob1: bob1 { + regulator-name = "pm8550_bob1"; + regulator-min-microvolt = <3416000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + /* TODO: bob2 @ 2.704-3.008V doesn't fall into the vreg driver constraints */ + + pm8550_l1: ldo1 { + regulator-name = "pm8550_l1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l2: ldo2 { + regulator-name = "pm8550_l2"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + /* L4 exists in cmd-db, but the board seems to crash on access */ + + pm8550_l5: ldo5 { + regulator-name = "pm8550_l5"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + pm8550_l6: ldo6 { + regulator-name = "pm8550_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l7: ldo7 { + regulator-name = "pm8550_l7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l8: ldo8 { + regulator-name = "pm8550_l8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l9: ldo9 { + regulator-name = "pm8550_l9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l10: ldo10 { + regulator-name = "pm8550_l10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l11: ldo11 { + regulator-name = "pm8550_l11"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + pm8550_l12: ldo12 { + regulator-name = "pm8550_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l13: ldo13 { + regulator-name = "pm8550_l13"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + pm8550_l14: ldo14 { + regulator-name = "pm8550_l14"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + pm8550_l15: ldo15 { + regulator-name = "pm8550_l15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l16: ldo16 { + regulator-name = "pm8550_l16"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + pm8550_l17: ldo17 { + regulator-name = "pm8550_l17"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + pm8550vs_0_l1: ldo1 { + regulator-name = "pm8550vs_0_l1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pm8550vs_0_l3: ldo3 { + regulator-name = "pm8550vs_0_l3"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + pm8550vs_1_l1: ldo1 { + regulator-name = "pm8550vs_1_l1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + /* L3 exists in cmd-db, but the board seems to crash on access */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + pm8550vs_2_s4: smps4 { + regulator-name = "pm8550vs_2_s4"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_s5: smps5 { + regulator-name = "pm8550vs_2_s5"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l1: ldo1 { + regulator-name = "pm8550vs_2_l1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l2: ldo2 { + regulator-name = "pm8550vs_2_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <968000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l3: ldo3 { + regulator-name = "pm8550vs_2_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + pm8550ve_s4: smps4 { + regulator-name = "pm8550ve_s4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + pm8550ve_l1: ldo1 { + regulator-name = "pm8550ve_l1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550ve_l2: ldo2 { + regulator-name = "pm8550ve_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550ve_l3: ldo3 { + regulator-name = "pm8550ve_l3"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + pm8550vs_3_s1: smps1 { + regulator-name = "pm8550vs_3_s1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s2: smps2 { + regulator-name = "pm8550vs_3_s2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s3: smps3 { + regulator-name = "pm8550vs_3_s3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s4: smps4 { + regulator-name = "pm8550vs_3_s4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s5: smps5 { + regulator-name = "pm8550vs_3_s5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s6: smps6 { + regulator-name = "pm8550vs_3_s6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l1: ldo1 { + regulator-name = "pm8550vs_3_l1"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l2: ldo2 { + regulator-name = "pm8550vs_3_l2"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l3: ldo3 { + regulator-name = "pm8550vs_3_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + /* TODO: Unknown PMIC @ k, l, PM8010 @ m, n */ +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&i2c_hub_2 { + clock-frequency = <400000>; + status = "okay"; + + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&pm8550vs_g_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&cam_pwr_a_cs>; + pinctrl-names = "default"; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <1000000>; + status = "okay"; + + /* NXP NFC @ 28 */ +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + /* LX Semi SW82907 touchscreen @ 28 */ +}; + +&i2c10 { + clock-frequency = <1000000>; + status = "okay"; + + /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ +}; + +&i2c11 { + clock-frequency = <1000000>; + status = "okay"; + + cs35l41_l: speaker-amp@30 { + compatible = "cirrus,cs35l45"; + reg = <0x30>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,asp-sdout-hiz-ctrl = <(CS35L45_ASP_TX_HIZ_UNUSED | CS35L45_ASP_TX_HIZ_DISABLED)>; + #sound-dai-cells = <1>; + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x2>; + }; + }; + + cs35l41_r: speaker-amp@31 { + compatible = "cirrus,cs35l45"; + reg = <0x31>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,asp-sdout-hiz-ctrl = <(CS35L45_ASP_TX_HIZ_UNUSED | CS35L45_ASP_TX_HIZ_DISABLED)>; + #sound-dai-cells = <1>; + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x2>; + }; + }; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&pm8550vs_2_l1>; + vdda-pll-supply = <&pm8550vs_2_l3>; + + status = "okay"; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; + +&pm8550_gpios { + vol_down_n: volume-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio12"; + function = "normal"; + power-source = <1>; + bias-pull-down; + output-disable; + input-enable; + }; +}; + +&pm8550b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio7"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550vs_g_gpios { + cam_pwr_a_cs: cam-pwr-a-cs-state { + pins = "gpio4"; + function = "normal"; + power-source = <0x01>; + drive-push-pull; + output-low; + qcom,drive-strength = ; + }; +}; + +&pm8550b_eusb2_repeater { + qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>; + qcom,tune-usb2-amplitude = /bits/ 8 <0xf>; + qcom,tune-usb2-preem = /bits/ 8 <0x7>; + vdd18-supply = <&pm8550_l15>; + vdd3-supply = <&pm8550_l5>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/Sony/yodo/adsp.mbn", + "qcom/sm8550/Sony/yodo/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/Sony/yodo/cdsp.mbn", + "qcom/sm8550/Sony/yodo/cdsp_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&pm8550_l9>; + vqmmc-supply = <&pm8550_l8>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&pm8550vs_2_l1>; + vdda12-supply = <&pm8550vs_2_l3>; + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&pm8550vs_2_l3>; + vdda-pll-supply = <&pm8550ve_l3>; + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +};