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This avoids hardcoded constants in device tree sources. Signed-off-by: Michael Riesch Acked-by: Rob Herring --- include/dt-bindings/media/video-interfaces.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h index 68ac4e05e37f..02d8239c2038 100644 --- a/include/dt-bindings/media/video-interfaces.h +++ b/include/dt-bindings/media/video-interfaces.h @@ -13,4 +13,8 @@ #define MEDIA_BUS_TYPE_PARALLEL 5 #define MEDIA_BUS_TYPE_BT656 6 +#define MEDIA_PCLK_SAMPLE_FALLING_EDGE 0 +#define MEDIA_PCLK_SAMPLE_RISING_EDGE 1 +#define MEDIA_PCLK_SAMPLE_DUAL_EDGE 2 + #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ From patchwork Tue Feb 20 09:39:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 774424 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2128.outbound.protection.outlook.com [40.107.21.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6988660DD8; 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Add a new header file with port definitions to avoid hardcoded constants in device tree sources. Signed-off-by: Michael Riesch --- include/dt-bindings/media/rockchip-cif.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/dt-bindings/media/rockchip-cif.h b/include/dt-bindings/media/rockchip-cif.h new file mode 100644 index 000000000000..37364ee1f7bc --- /dev/null +++ b/include/dt-bindings/media/rockchip-cif.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2023 Michael Riesch + */ + +#ifndef __DT_BINDINGS_MEDIA_ROCKCHIP_CIF_H__ +#define __DT_BINDINGS_MEDIA_ROCKCHIP_CIF_H__ + +#define MEDIA_ROCKCHIP_CIF_DVP 0 +#define MEDIA_ROCKCHIP_CIF_MIPI 1 + +#endif /* __DT_BINDINGS_MEDIA_ROCKCHIP_CIF_H__ */ From patchwork Tue Feb 20 09:39:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 774759 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2128.outbound.protection.outlook.com [40.107.21.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5B260EDE; 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Document the property iommus in order to support the former case. Signed-off-by: Michael Riesch Acked-by: Rob Herring --- Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml index 6af4a9b6774a..675a1ea47210 100644 --- a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml @@ -36,6 +36,9 @@ properties: - const: hclk - const: pclk + iommus: + maxItems: 1 + resets: items: - description: AXI From patchwork Tue Feb 20 09:39:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 774423 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2128.outbound.protection.outlook.com [40.107.21.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46A94612FE; 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Signed-off-by: Michael Riesch --- .../bindings/media/rockchip,px30-vip.yaml | 58 ++++++++++++++-------- 1 file changed, 37 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml index 675a1ea47210..7168f166798c 100644 --- a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml @@ -24,32 +24,16 @@ properties: interrupts: maxItems: 1 - clocks: - items: - - description: ACLK - - description: HCLK - - description: PCLK - - clock-names: - items: - - const: aclk - - const: hclk - - const: pclk + clocks: true + + clock-names: true iommus: maxItems: 1 - resets: - items: - - description: AXI - - description: AHB - - description: PCLK IN + resets: true - reset-names: - items: - - const: axi - - const: ahb - - const: pclkin + reset-names: true power-domains: maxItems: 1 @@ -85,6 +69,38 @@ required: - clocks - ports +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,px30-vip + then: + properties: + clocks: + items: + - description: ACLK + - description: HCLK + - description: PCLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: pclk + + resets: + items: + - description: AXI + - description: AHB + - description: PCLK IN + + reset-names: + items: + - const: axi + - const: ahb + - const: pclkin + additionalProperties: false examples: From patchwork Tue Feb 20 09:39:15 2024 Content-Type: text/plain; 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Signed-off-by: Michael Riesch --- .../bindings/media/rockchip,px30-vip.yaml | 45 +++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml index 7168f166798c..06d49f591efd 100644 --- a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml @@ -16,7 +16,9 @@ description: properties: compatible: - const: rockchip,px30-vip + enum: + - rockchip,px30-vip + - rockchip,rk3568-vicap reg: maxItems: 1 @@ -35,6 +37,11 @@ properties: reset-names: true + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to general register file used for video input block control. + power-domains: maxItems: 1 @@ -100,6 +107,42 @@ allOf: - const: axi - const: ahb - const: pclkin + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-vicap + then: + properties: + clocks: + items: + - description: ACLK + - description: HCLK + - description: DCLK + - description: ICLK + + clock-names: + items: + - const: aclk + - const: hclk + - const: dclk + - const: iclk + + resets: + items: + - description: ARST + - description: HRST + - description: DRST + - description: PRST + - description: IRST + + reset-names: + items: + - const: arst + - const: hrst + - const: drst + - const: prst + - const: irst additionalProperties: false From patchwork Tue Feb 20 09:39:16 2024 Content-Type: text/plain; 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Store the information in the private data of the driver in order to make it accessible. Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/cif/cif-common.h | 1 + drivers/media/platform/rockchip/cif/cif-dev.c | 11 +++++------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/cif-common.h b/drivers/media/platform/rockchip/cif/cif-common.h index 89ed9dd6f36d..34da800a0504 100644 --- a/drivers/media/platform/rockchip/cif/cif-common.h +++ b/drivers/media/platform/rockchip/cif/cif-common.h @@ -108,6 +108,7 @@ struct cif_device { struct media_device media_dev; struct v4l2_async_notifier notifier; struct v4l2_async_connection asd; + struct v4l2_fwnode_endpoint vep; struct cif_remote remote; struct cif_stream stream; diff --git a/drivers/media/platform/rockchip/cif/cif-dev.c b/drivers/media/platform/rockchip/cif/cif-dev.c index 660e28397916..923831827be4 100644 --- a/drivers/media/platform/rockchip/cif/cif-dev.c +++ b/drivers/media/platform/rockchip/cif/cif-dev.c @@ -79,9 +79,7 @@ static int cif_subdev_notifier(struct cif_device *cif_dev) struct v4l2_async_notifier *ntf = &cif_dev->notifier; struct device *dev = cif_dev->dev; struct v4l2_async_connection *asd; - struct v4l2_fwnode_endpoint vep = { - .bus_type = V4L2_MBUS_UNKNOWN, - }; + struct v4l2_fwnode_endpoint *vep = &cif_dev->vep; struct fwnode_handle *ep; int ret; @@ -92,12 +90,13 @@ static int cif_subdev_notifier(struct cif_device *cif_dev) if (!ep) return -ENODEV; - ret = v4l2_fwnode_endpoint_parse(ep, &vep); + vep->bus_type = V4L2_MBUS_UNKNOWN; + ret = v4l2_fwnode_endpoint_parse(ep, vep); if (ret) goto complete; - if (vep.bus_type != V4L2_MBUS_BT656 && - vep.bus_type != V4L2_MBUS_PARALLEL) { + if (vep->bus_type != V4L2_MBUS_BT656 && + vep->bus_type != V4L2_MBUS_PARALLEL) { v4l2_err(&cif_dev->v4l2_dev, "unsupported bus type\n"); goto complete; } From patchwork Tue Feb 20 09:39:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 774757 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2128.outbound.protection.outlook.com [40.107.21.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC05264CC6; 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No functional change. Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/cif/cif-capture.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/cif-capture.c b/drivers/media/platform/rockchip/cif/cif-capture.c index 2c7716684de0..c80a52028a21 100644 --- a/drivers/media/platform/rockchip/cif/cif-capture.c +++ b/drivers/media/platform/rockchip/cif/cif-capture.c @@ -273,8 +273,8 @@ cif_input_fmt *get_input_fmt(struct v4l2_subdev *sd) return NULL; } -static struct -cif_output_fmt *find_output_fmt(struct cif_stream *stream, u32 pixelfmt) +static struct cif_output_fmt *find_output_fmt(struct cif_stream *stream, + u32 pixelfmt) { struct cif_output_fmt *fmt; u32 i; From patchwork Tue Feb 20 09:39:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 774421 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2128.outbound.protection.outlook.com [40.107.21.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92B22651AE; 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Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/cif/cif-dev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/rockchip/cif/cif-dev.c b/drivers/media/platform/rockchip/cif/cif-dev.c index 923831827be4..c4282449a93d 100644 --- a/drivers/media/platform/rockchip/cif/cif-dev.c +++ b/drivers/media/platform/rockchip/cif/cif-dev.c @@ -7,6 +7,7 @@ * Copyright (C) 2023 Mehdi Djait */ +#include #include #include #include @@ -85,7 +86,8 @@ static int cif_subdev_notifier(struct cif_device *cif_dev) v4l2_async_nf_init(ntf, &cif_dev->v4l2_dev); - ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), + MEDIA_ROCKCHIP_CIF_DVP, 0, FWNODE_GRAPH_ENDPOINT_NEXT); if (!ep) return -ENODEV; From patchwork Tue Feb 20 09:39:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 774756 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2128.outbound.protection.outlook.com [40.107.21.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8863F657CB; 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Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/cif/cif-common.h | 3 +++ drivers/media/platform/rockchip/cif/cif-dev.c | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/media/platform/rockchip/cif/cif-common.h b/drivers/media/platform/rockchip/cif/cif-common.h index 34da800a0504..ae8fedeadd1c 100644 --- a/drivers/media/platform/rockchip/cif/cif-common.h +++ b/drivers/media/platform/rockchip/cif/cif-common.h @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -96,6 +97,7 @@ static inline struct cif_stream *to_cif_stream(struct video_device *vdev) struct cif_match_data { struct clk_bulk_data *clks; int clks_num; + void (*grf_dvp_setup)(struct cif_device *cif_dev); }; struct cif_device { @@ -103,6 +105,7 @@ struct cif_device { int irq; void __iomem *base_addr; struct reset_control *cif_rst; + struct regmap *grf; struct v4l2_device v4l2_dev; struct media_device media_dev; diff --git a/drivers/media/platform/rockchip/cif/cif-dev.c b/drivers/media/platform/rockchip/cif/cif-dev.c index c4282449a93d..b75b76508793 100644 --- a/drivers/media/platform/rockchip/cif/cif-dev.c +++ b/drivers/media/platform/rockchip/cif/cif-dev.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -103,6 +104,9 @@ static int cif_subdev_notifier(struct cif_device *cif_dev) goto complete; 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Add a variant specific input format list to account for this. Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/cif/cif-capture.c | 154 +--------------------- drivers/media/platform/rockchip/cif/cif-common.h | 2 + drivers/media/platform/rockchip/cif/cif-dev.c | 147 +++++++++++++++++++++ 3 files changed, 154 insertions(+), 149 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/cif-capture.c b/drivers/media/platform/rockchip/cif/cif-capture.c index c80a52028a21..b26e6023c2b0 100644 --- a/drivers/media/platform/rockchip/cif/cif-capture.c +++ b/drivers/media/platform/rockchip/cif/cif-capture.c @@ -109,154 +109,10 @@ static struct cif_output_fmt out_fmts[] = { } }; -static const struct cif_input_fmt in_fmts[] = { - { - .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, - .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | - CIF_FORMAT_YUV_INPUT_ORDER_YUYV, - .fmt_type = CIF_FMT_TYPE_YUV, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, - .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | - CIF_FORMAT_YUV_INPUT_ORDER_YUYV, - .fmt_type = CIF_FMT_TYPE_YUV, - .field = V4L2_FIELD_INTERLACED, - }, { - .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8, - .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | - CIF_FORMAT_YUV_INPUT_ORDER_YVYU, - .fmt_type = CIF_FMT_TYPE_YUV, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8, - .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | - CIF_FORMAT_YUV_INPUT_ORDER_YVYU, - .fmt_type = CIF_FMT_TYPE_YUV, - .field = V4L2_FIELD_INTERLACED, - }, { - .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, - .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | - CIF_FORMAT_YUV_INPUT_ORDER_UYVY, - .fmt_type = CIF_FMT_TYPE_YUV, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, - .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | - CIF_FORMAT_YUV_INPUT_ORDER_UYVY, - .fmt_type = CIF_FMT_TYPE_YUV, - .field = V4L2_FIELD_INTERLACED, - }, { - .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8, - .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | - CIF_FORMAT_YUV_INPUT_ORDER_VYUY, - .fmt_type = CIF_FMT_TYPE_YUV, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8, - .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | - CIF_FORMAT_YUV_INPUT_ORDER_VYUY, - .fmt_type = CIF_FMT_TYPE_YUV, - .field = V4L2_FIELD_INTERLACED, - }, { - .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_8, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_8, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_8, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_8, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_10, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_10, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_10, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_10, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_12, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_12, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_12, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_12, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_RGB888_1X24, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_Y8_1X8, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_8, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_Y10_1X10, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_10, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - }, { - .mbus_code = MEDIA_BUS_FMT_Y12_1X12, - .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | - CIF_FORMAT_RAW_DATA_WIDTH_12, - .fmt_type = CIF_FMT_TYPE_RAW, - .field = V4L2_FIELD_NONE, - } -}; - -static const struct -cif_input_fmt *get_input_fmt(struct v4l2_subdev *sd) +static const struct cif_input_fmt *get_input_fmt(struct cif_device *cif_dev, + struct v4l2_subdev *sd) { + const struct cif_input_fmt *in_fmts = cif_dev->match_data->in_fmts; struct v4l2_subdev_format fmt; u32 i; @@ -264,7 +120,7 @@ cif_input_fmt *get_input_fmt(struct v4l2_subdev *sd) fmt.pad = 0; v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt); - for (i = 0; i < ARRAY_SIZE(in_fmts); i++) + for (i = 0; i < cif_dev->match_data->in_fmts_num; i++) if (fmt.format.code == in_fmts[i].mbus_code && fmt.format.field == in_fmts[i].field) return &in_fmts[i]; @@ -550,7 +406,7 @@ static int cif_start_streaming(struct vb2_queue *queue, unsigned int count) sd = cif_dev->remote.sd; - stream->cif_fmt_in = get_input_fmt(cif_dev->remote.sd); + stream->cif_fmt_in = get_input_fmt(cif_dev, sd); if (!stream->cif_fmt_in) goto runtime_put; diff --git a/drivers/media/platform/rockchip/cif/cif-common.h b/drivers/media/platform/rockchip/cif/cif-common.h index ae8fedeadd1c..84a7545422e1 100644 --- a/drivers/media/platform/rockchip/cif/cif-common.h +++ b/drivers/media/platform/rockchip/cif/cif-common.h @@ -97,6 +97,8 @@ static inline struct cif_stream *to_cif_stream(struct video_device *vdev) struct cif_match_data { struct clk_bulk_data *clks; int clks_num; + const struct cif_input_fmt *in_fmts; + int in_fmts_num; void (*grf_dvp_setup)(struct cif_device *cif_dev); }; diff --git a/drivers/media/platform/rockchip/cif/cif-dev.c b/drivers/media/platform/rockchip/cif/cif-dev.c index b75b76508793..fb80e8f8dcab 100644 --- a/drivers/media/platform/rockchip/cif/cif-dev.c +++ b/drivers/media/platform/rockchip/cif/cif-dev.c @@ -132,9 +132,156 @@ static struct clk_bulk_data px30_cif_clks[] = { { .id = "pclk", }, }; +static const struct cif_input_fmt px30_in_fmts[] = { + { + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_RGB888_1X24, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_Y8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_Y12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + } +}; + static const struct cif_match_data px30_cif_match_data = { .clks = px30_cif_clks, .clks_num = ARRAY_SIZE(px30_cif_clks), + .in_fmts = px30_in_fmts, + .in_fmts_num = ARRAY_SIZE(px30_in_fmts), }; static const struct of_device_id cif_plat_of_match[] = { From patchwork Tue Feb 20 09:39:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 774755 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2128.outbound.protection.outlook.com [40.107.21.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 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Subject: [PATCH 11/14] media: rockchip: cif: make scaler support variant specific Message-Id: <20240220-v6-8-topic-rk3568-vicap-v1-11-2680a1fa640b@wolfvision.net> References: <20240220-v6-8-topic-rk3568-vicap-v1-0-2680a1fa640b@wolfvision.net> In-Reply-To: <20240220-v6-8-topic-rk3568-vicap-v1-0-2680a1fa640b@wolfvision.net> To: Mehdi Djait , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708421995; l=2344; i=michael.riesch@wolfvision.net; s=20230803; h=from:subject:message-id; bh=GB4WBeer0yHTCcaF3Iic4k4romkbTfe6QlJh2+daQM8=; b=SHZ3lQBcHxWUyTWCGHGvLKxIwBok1VxgYrIGqHAVLuRY1y4GwI0PJHWEm1IfQXJaDX0D9YZXe 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X-OriginatorOrg: wolfvision.net X-MS-Exchange-CrossTenant-Network-Message-Id: 7a234b08-1930-4e5d-6b24-08dc31f7f2fd X-MS-Exchange-CrossTenant-AuthSource: DU0PR08MB9155.eurprd08.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2024 09:40:18.3847 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: e94ec9da-9183-471e-83b3-51baa8eb804f X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Wv2d/9lCYFsPXsR/cp93EfQWyJrewqqE0Tk7TR35KsNYshZq5YvHSH6YzoU/lQ2pB6znpVbhMMVPm7DaKd8xr9rT2fvhiZwBaV/472BMTeM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6763 Not all variants of the Rockchip CIF feature a scaler unit. Add variant specific Boolean variable to account for this. Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/cif/cif-capture.c | 8 +++++--- drivers/media/platform/rockchip/cif/cif-common.h | 1 + drivers/media/platform/rockchip/cif/cif-dev.c | 1 + 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/cif-capture.c b/drivers/media/platform/rockchip/cif/cif-capture.c index b26e6023c2b0..dd5c45f28cdd 100644 --- a/drivers/media/platform/rockchip/cif/cif-capture.c +++ b/drivers/media/platform/rockchip/cif/cif-capture.c @@ -365,9 +365,11 @@ static int cif_stream_start(struct cif_stream *stream) cif_write(cif_dev, CIF_FRAME_STATUS, CIF_FRAME_STAT_CLS); cif_write(cif_dev, CIF_INTSTAT, CIF_INTSTAT_CLS); - cif_write(cif_dev, CIF_SCL_CTRL, (fmt_type == CIF_FMT_TYPE_YUV) ? - CIF_SCL_CTRL_ENABLE_YUV_16BIT_BYPASS : - CIF_SCL_CTRL_ENABLE_RAW_16BIT_BYPASS); + if (cif_dev->match_data->has_scaler) + cif_write(cif_dev, CIF_SCL_CTRL, + (fmt_type == CIF_FMT_TYPE_YUV) ? + CIF_SCL_CTRL_ENABLE_YUV_16BIT_BYPASS : + CIF_SCL_CTRL_ENABLE_RAW_16BIT_BYPASS); ret = cif_init_buffers(stream); if (ret) diff --git a/drivers/media/platform/rockchip/cif/cif-common.h b/drivers/media/platform/rockchip/cif/cif-common.h index 84a7545422e1..e5500705eee2 100644 --- a/drivers/media/platform/rockchip/cif/cif-common.h +++ b/drivers/media/platform/rockchip/cif/cif-common.h @@ -100,6 +100,7 @@ struct cif_match_data { const struct cif_input_fmt *in_fmts; int in_fmts_num; void (*grf_dvp_setup)(struct cif_device *cif_dev); + bool has_scaler; }; struct cif_device { diff --git a/drivers/media/platform/rockchip/cif/cif-dev.c b/drivers/media/platform/rockchip/cif/cif-dev.c index fb80e8f8dcab..e7b5ae5804ca 100644 --- a/drivers/media/platform/rockchip/cif/cif-dev.c +++ b/drivers/media/platform/rockchip/cif/cif-dev.c @@ -282,6 +282,7 @@ static const struct cif_match_data px30_cif_match_data = { .clks_num = ARRAY_SIZE(px30_cif_clks), .in_fmts = px30_in_fmts, .in_fmts_num = ARRAY_SIZE(px30_in_fmts), + .has_scaler = true, }; static const struct of_device_id cif_plat_of_match[] = { From patchwork Tue Feb 20 09:39:22 2024 Content-Type: text/plain; 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Modify the cif_{read,write} methods in order to support variant specific register offsets Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/cif/cif-common.h | 26 ++++++++++++- drivers/media/platform/rockchip/cif/cif-dev.c | 17 +++++++++ drivers/media/platform/rockchip/cif/cif-regs.h | 47 ++++++++++-------------- 3 files changed, 61 insertions(+), 29 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/cif-common.h b/drivers/media/platform/rockchip/cif/cif-common.h index e5500705eee2..7ecdc820171e 100644 --- a/drivers/media/platform/rockchip/cif/cif-common.h +++ b/drivers/media/platform/rockchip/cif/cif-common.h @@ -19,6 +19,8 @@ #include #include +#include "cif-regs.h" + #define CIF_DRIVER_NAME "rockchip-cif" #define CIF_MAX_BUS_CLK 8 @@ -101,6 +103,7 @@ struct cif_match_data { int in_fmts_num; void (*grf_dvp_setup)(struct cif_device *cif_dev); bool has_scaler; + unsigned int regs[CIF_REGISTERS_MAX]; }; struct cif_device { @@ -121,14 +124,33 @@ struct cif_device { const struct cif_match_data *match_data; }; -static inline void cif_write(struct cif_device *cif_dev, unsigned int addr, +static inline unsigned int cif_get_addr(struct cif_device *cif_device, + unsigned int index) +{ + if (index >= CIF_REGISTERS_MAX) + return CIF_REGISTERS_INVALID; + + return cif_device->match_data->regs[index]; +} + +static inline void cif_write(struct cif_device *cif_dev, unsigned int index, u32 val) { + unsigned int addr = cif_get_addr(cif_dev, index); + + if (addr == CIF_REGISTERS_INVALID) + return; + writel(val, cif_dev->base_addr + addr); } -static inline u32 cif_read(struct cif_device *cif_dev, unsigned int addr) +static inline u32 cif_read(struct cif_device *cif_dev, unsigned int index) { + unsigned int addr = cif_get_addr(cif_dev, index); + + if (addr == CIF_REGISTERS_INVALID) + return 0; + return readl(cif_dev->base_addr + addr); } diff --git a/drivers/media/platform/rockchip/cif/cif-dev.c b/drivers/media/platform/rockchip/cif/cif-dev.c index e7b5ae5804ca..929ea39dd832 100644 --- a/drivers/media/platform/rockchip/cif/cif-dev.c +++ b/drivers/media/platform/rockchip/cif/cif-dev.c @@ -283,6 +283,23 @@ static const struct cif_match_data px30_cif_match_data = { .in_fmts = px30_in_fmts, .in_fmts_num = ARRAY_SIZE(px30_in_fmts), .has_scaler = true, + .regs = { + [CIF_CTRL] = 0x00, + [CIF_INTEN] = 0x04, + [CIF_INTSTAT] = 0x08, + [CIF_FOR] = 0x0c, + [CIF_LINE_NUM_ADDR] = 0x10, + [CIF_FRM0_ADDR_Y] = 0x14, + [CIF_FRM0_ADDR_UV] = 0x18, + [CIF_FRM1_ADDR_Y] = 0x1c, + [CIF_FRM1_ADDR_UV] = 0x20, + [CIF_VIR_LINE_WIDTH] = 0x24, + [CIF_SET_SIZE] = 0x28, + [CIF_SCL_CTRL] = 0x48, + [CIF_FRAME_STATUS] = 0x60, + [CIF_LAST_LINE] = 0x68, + [CIF_LAST_PIX] = 0x6c, + }, }; static const struct of_device_id cif_plat_of_match[] = { diff --git a/drivers/media/platform/rockchip/cif/cif-regs.h b/drivers/media/platform/rockchip/cif/cif-regs.h index b8500f0a9ac1..2ce756fde204 100644 --- a/drivers/media/platform/rockchip/cif/cif-regs.h +++ b/drivers/media/platform/rockchip/cif/cif-regs.h @@ -9,33 +9,26 @@ #ifndef _CIF_REGS_H #define _CIF_REGS_H -#define CIF_CTRL 0x00 -#define CIF_INTEN 0x04 -#define CIF_INTSTAT 0x08 -#define CIF_FOR 0x0c -#define CIF_LINE_NUM_ADDR 0x10 -#define CIF_FRM0_ADDR_Y 0x14 -#define CIF_FRM0_ADDR_UV 0x18 -#define CIF_FRM1_ADDR_Y 0x1c -#define CIF_FRM1_ADDR_UV 0x20 -#define CIF_VIR_LINE_WIDTH 0x24 -#define CIF_SET_SIZE 0x28 -#define CIF_SCM_ADDR_Y 0x2c -#define CIF_SCM_ADDR_U 0x30 -#define CIF_SCM_ADDR_V 0x34 -#define CIF_WB_UP_FILTER 0x38 -#define CIF_WB_LOW_FILTER 0x3c -#define CIF_WBC_CNT 0x40 -#define CIF_CROP 0x44 -#define CIF_SCL_CTRL 0x48 -#define CIF_SCL_DST 0x4c -#define CIF_SCL_FCT 0x50 -#define CIF_SCL_VALID_NUM 0x54 -#define CIF_LINE_LOOP_CTR 0x58 -#define CIF_FRAME_STATUS 0x60 -#define CIF_CUR_DST 0x64 -#define CIF_LAST_LINE 0x68 -#define CIF_LAST_PIX 0x6c +enum cif_register { + CIF_CTRL, + CIF_INTEN, + CIF_INTSTAT, + CIF_FOR, + CIF_LINE_NUM_ADDR, + CIF_FRM0_ADDR_Y, + CIF_FRM0_ADDR_UV, + CIF_FRM1_ADDR_Y, + CIF_FRM1_ADDR_UV, + CIF_VIR_LINE_WIDTH, + CIF_SET_SIZE, + CIF_SCL_CTRL, + CIF_FRAME_STATUS, + CIF_LAST_LINE, + CIF_LAST_PIX, + CIF_REGISTERS_MAX, + CIF_REGISTERS_INVALID, +}; + #define CIF_FETCH_Y_LAST_LINE(VAL) ((VAL) & 0x1fff) #define CIF_CTRL_ENABLE_CAPTURE BIT(0) From patchwork Tue Feb 20 09:39:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 774418 Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2110.outbound.protection.outlook.com [40.107.7.110]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 663D567A0E; Tue, 20 Feb 2024 09:40:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.7.110 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708422031; cv=fail; b=OxztmvBOrHV5VE9Zq9tyPOA2tTanKrENQ2wVPd1l3e8Qt4lXbPnH0oUtvWd5pdbb8JLUqfjccTmUFvJCN8FgtyRwA5R4ntFZajG/0WaekQ9ATg9cT6maZJehugNEGOXpmGzsuhwaAQtpCy2MJijNqMKJKUHlk34xeR519ZtWFfM= ARC-Message-Signature: i=2; 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Tue, 20 Feb 2024 09:40:22 +0000 From: Michael Riesch Date: Tue, 20 Feb 2024 10:39:23 +0100 Subject: [PATCH 13/14] media: rockchip: cif: add support for rk3568 vicap Message-Id: <20240220-v6-8-topic-rk3568-vicap-v1-13-2680a1fa640b@wolfvision.net> References: <20240220-v6-8-topic-rk3568-vicap-v1-0-2680a1fa640b@wolfvision.net> In-Reply-To: <20240220-v6-8-topic-rk3568-vicap-v1-0-2680a1fa640b@wolfvision.net> To: Mehdi Djait , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Petazzoni , Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sakari Ailus Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Michael Riesch X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708421995; l=10682; i=michael.riesch@wolfvision.net; s=20230803; h=from:subject:message-id; bh=P9Qxsw9kjyeE5rbxicA+k/0vkgilDJms8XWxah2XXTE=; b=AdirQIj9JolCGpJ3i/cVeTkZRxGso9vf0xUn8Q+zjsuocZy/Fu0BOCXFy3Wtedfi+kye5grBs Jq66aqW0oeDDUBmolBvR6oJconbVU25f+EkswsYTAmOA3ilWVm5LQKf X-Developer-Key: i=michael.riesch@wolfvision.net; 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Signed-off-by: Michael Riesch --- drivers/media/platform/rockchip/cif/cif-capture.c | 6 + drivers/media/platform/rockchip/cif/cif-dev.c | 247 ++++++++++++++++++++++ drivers/media/platform/rockchip/cif/cif-regs.h | 9 + 3 files changed, 262 insertions(+) diff --git a/drivers/media/platform/rockchip/cif/cif-capture.c b/drivers/media/platform/rockchip/cif/cif-capture.c index dd5c45f28cdd..d0e8f3b49d38 100644 --- a/drivers/media/platform/rockchip/cif/cif-capture.c +++ b/drivers/media/platform/rockchip/cif/cif-capture.c @@ -340,6 +340,7 @@ static int cif_stream_start(struct cif_stream *stream) u32 val, fmt_type, xfer_mode = 0; struct cif_device *cif_dev = stream->cifdev; struct cif_remote *remote_info = &cif_dev->remote; + struct v4l2_mbus_config_parallel *parallel; int ret; u32 input_mode; @@ -351,6 +352,11 @@ static int cif_stream_start(struct cif_stream *stream) CIF_FORMAT_INPUT_MODE_NTSC : CIF_FORMAT_INPUT_MODE_PAL; + parallel = &cif_dev->vep.bus.parallel; + if ((parallel->bus_width == 16) && + (parallel->flags & V4L2_MBUS_PCLK_SAMPLE_DUALEDGE)) + xfer_mode |= CIF_FORMAT_BT1120_CLOCK_DOUBLE_EDGES; + val = input_mode | stream->cif_fmt_out->fmt_val | stream->cif_fmt_in->dvp_fmt_val | xfer_mode; cif_write(cif_dev, CIF_FOR, val); diff --git a/drivers/media/platform/rockchip/cif/cif-dev.c b/drivers/media/platform/rockchip/cif/cif-dev.c index 929ea39dd832..3b895b496c45 100644 --- a/drivers/media/platform/rockchip/cif/cif-dev.c +++ b/drivers/media/platform/rockchip/cif/cif-dev.c @@ -302,11 +302,258 @@ static const struct cif_match_data px30_cif_match_data = { }, }; +static const struct cif_input_fmt rk3568_in_fmts[] = { + { + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YUYV, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YVYU, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_UYVY, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_VYUY, + .fmt_type = CIF_FMT_TYPE_YUV, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YUYV | + CIF_FORMAT_INPUT_MODE_BT1120 | + CIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YUYV | + CIF_FORMAT_INPUT_MODE_BT1120, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YVYU | + CIF_FORMAT_INPUT_MODE_BT1120 | + CIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YVYU | + CIF_FORMAT_INPUT_MODE_BT1120, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YUYV | + CIF_FORMAT_INPUT_MODE_BT1120 | + CIF_FORMAT_BT1120_YC_SWAP | + CIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YUYV | + CIF_FORMAT_BT1120_YC_SWAP | + CIF_FORMAT_INPUT_MODE_BT1120, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YVYU | + CIF_FORMAT_INPUT_MODE_BT1120 | + CIF_FORMAT_BT1120_YC_SWAP | + CIF_FORMAT_BT1120_TRANSMIT_PROGRESS, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16, + .dvp_fmt_val = CIF_FORMAT_YUV_INPUT_422 | + CIF_FORMAT_YUV_INPUT_ORDER_YVYU | + CIF_FORMAT_BT1120_YC_SWAP | + CIF_FORMAT_INPUT_MODE_BT1120, + .field = V4L2_FIELD_INTERLACED, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_RGB888_1X24, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_Y8_1X8, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_8, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_10, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, { + .mbus_code = MEDIA_BUS_FMT_Y12_1X12, + .dvp_fmt_val = CIF_FORMAT_INPUT_MODE_RAW | + CIF_FORMAT_RAW_DATA_WIDTH_12, + .fmt_type = CIF_FMT_TYPE_RAW, + .field = V4L2_FIELD_NONE, + }, +}; + +static struct clk_bulk_data rk3568_cif_clks[] = { + { .id = "aclk", }, + { .id = "hclk", }, + { .id = "dclk", }, + { .id = "iclk", }, +}; + +static void rk3568_grf_dvp_setup(struct cif_device *cif_dev) +{ + u32 con1 = RK3568_GRF_WRITE_ENABLE(RK3568_GRF_VI_CON1_CIF_DATAPATH); + + if (cif_dev->vep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_DUALEDGE) + con1 |= RK3568_GRF_VI_CON1_CIF_DATAPATH; + + regmap_write(cif_dev->grf, RK3568_GRF_VI_CON1, con1); +} + +static const struct cif_match_data rk3568_cif_match_data = { + .clks = rk3568_cif_clks, + .clks_num = ARRAY_SIZE(rk3568_cif_clks), + .grf_dvp_setup = rk3568_grf_dvp_setup, + .in_fmts = rk3568_in_fmts, + .in_fmts_num = ARRAY_SIZE(rk3568_in_fmts), + .has_scaler = false, + .regs = { + [CIF_CTRL] = 0x00, + [CIF_INTEN] = 0x04, + [CIF_INTSTAT] = 0x08, + [CIF_FOR] = 0x0c, + [CIF_LINE_NUM_ADDR] = 0x2c, + [CIF_FRM0_ADDR_Y] = 0x14, + [CIF_FRM0_ADDR_UV] = 0x18, + [CIF_FRM1_ADDR_Y] = 0x1c, + [CIF_FRM1_ADDR_UV] = 0x20, + [CIF_VIR_LINE_WIDTH] = 0x24, + [CIF_SET_SIZE] = 0x28, + [CIF_FRAME_STATUS] = 0x3c, + [CIF_LAST_LINE] = 0x44, + [CIF_LAST_PIX] = 0x48, + }, +}; + static const struct of_device_id cif_plat_of_match[] = { { .compatible = "rockchip,px30-vip", .data = &px30_cif_match_data, }, + { + .compatible = "rockchip,rk3568-vicap", + .data = &rk3568_cif_match_data, + }, {}, }; diff --git a/drivers/media/platform/rockchip/cif/cif-regs.h b/drivers/media/platform/rockchip/cif/cif-regs.h index 2ce756fde204..261bc71240f2 100644 --- a/drivers/media/platform/rockchip/cif/cif-regs.h +++ b/drivers/media/platform/rockchip/cif/cif-regs.h @@ -117,4 +117,13 @@ enum cif_register { #define CIF_CROP_Y_SHIFT 16 #define CIF_CROP_X_SHIFT 0 +/* GRF register offsets */ +#define RK3568_GRF_VI_CON0 0x340 +#define RK3568_GRF_VI_CON1 0x344 +#define RK3568_GRF_VI_STATUS0 0x348 + +#define RK3568_GRF_VI_CON1_CIF_DATAPATH BIT(9) + +#define RK3568_GRF_WRITE_ENABLE(x) ((x) << 16) + #endif From patchwork Tue Feb 20 09:39:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR08MB9357 Add the device tree node for the RK356x Video Capture (VICAP) block. Signed-off-by: Michael Riesch --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 45 ++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index c19c0f1b3778..ad61afd84c12 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -593,6 +594,50 @@ gpu: gpu@fde60000 { status = "disabled"; }; + vicap: video-capture@fdfe0000 { + compatible = "rockchip,rk3568-vicap"; + reg = <0x0 0xfdfe0000 0x0 0x200>; + interrupts = ; + assigned-clocks = <&cru DCLK_VICAP>; + assigned-clock-rates = <300000000>; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; + clock-names = "aclk", "hclk", "dclk", "iclk"; + iommus = <&vicap_mmu>; + power-domains = <&power RK3568_PD_VI>; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, + <&cru SRST_I_VICAP>; + reset-names = "arst", "hrst", "drst", "prst", "irst"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + vicap_dvp: port@MEDIA_ROCKCHIP_CIF_DVP { + reg = ; + }; + + vicap_mipi: port@MEDIA_ROCKCHIP_CIF_MIPI { + reg = ; + }; + }; + }; + + vicap_mmu: iommu@fdfe0800 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfdfe0800 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3568_PD_VI>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + vpu: video-codec@fdea0400 { compatible = "rockchip,rk3568-vpu"; reg = <0x0 0xfdea0000 0x0 0x800>;