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Thu, 22 Feb 2024 03:43:17 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h24-20020a19ca58000000b00512d495ef0bsm596857lfj.113.2024.02.22.03.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Feb 2024 03:43:17 -0800 (PST) From: Dmitry Baryshkov Date: Thu, 22 Feb 2024 13:43:17 +0200 Subject: [PATCH] drm/msm/dpu: add support for 4:2:2 and 4:4:4 planar YCbCr plane formats Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240222-fd-dpu-yv16-yv24-v1-1-4aa833cdc641@linaro.org> X-B4-Tracking: v=1; b=H4sIAFQz12UC/x2MuwqAMAwAf0UyG2jjC/wVcag20SwqLYoi/XeLy 8ENdy9EDsoR+uKFwJdG3bcstixgXt22MKrPDmSoNkSE4tEfJz6XbTOoxnYS25AX10kFOTsCi97 /chhT+gBqOi6ZYgAAAA== To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2623; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=/xAIOI0l3dOikmLlNmwn5S6CqFH5sP++nL7ytb94Y1o=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl1zNVL3NFur7GrLWkn3Ro1lU4Hj5863qqgmmdr 6lq1hjhGp+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZdczVQAKCRCLPIo+Aiko 1RdHB/0TkzNYPTo596AbO+BpnR00wJNPQ4vLArU56Pz+y+reGLuC3iBDcNIQboww6FMm/yrfd7H jlA5Fsd76hyTi+gWwm6gE+21WLEmWXVnDlbXHPRvfR2DlqBczYqSf0SO7OpbWAMoF87hYTuUC3n cdHS95WBOUAlXMH4ZCXmFwS0gc5zwR2hCAJqUzTKuETQ6/LixCNzKQM4negckMTpZj467MxX4go rgAv9VNO9gxMg10vb4LiqXODTsF2PxvFpA19RGnILRLPf9mVwW3gYRcsvcZluhsJAvC9L4FGrNY b6FPZBcCUjoxSASo1+8PSrGO+2CS21SSKe0r75UOhD4LnDoE X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The DPU driver provides support for 4:2:0 planar YCbCr plane formats. Extend it to also support 4:2:2 and 4:4:4 plat formats. Signed-off-by: Dmitry Baryshkov --- Full-screen (1080p@60) YV24 gave me underruns on SM8250 until I bumped the clock inefficiency factor from 105 to 117. I'm not sure that it is a correct way to handle it, so I'm sending this as an RFC. If we agree that bumping the .clk_inefficiency_factor is a correct way, I'll send v2, including catalog changes. I had no such issues for the YV16/YU16 formats. --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++++ 2 files changed, 28 insertions(+) --- base-commit: ffa0c87f172bf7a0132aa960db412f8d63b2f533 change-id: 20240222-fd-dpu-yv16-yv24-6bf152dfa7f3 Best regards, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index e366ab134249..1b763cd95e5a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -475,6 +475,30 @@ static const struct dpu_format dpu_format_map[] = { C1_B_Cb, C2_R_Cr, C0_G_Y, false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV, DPU_FETCH_LINEAR, 3), + + PLANAR_YUV_FMT(YUV422, + 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, + C2_R_Cr, C1_B_Cb, C0_G_Y, + false, DPU_CHROMA_H2V1, 1, DPU_FORMAT_FLAG_YUV, + DPU_FETCH_LINEAR, 3), + + PLANAR_YUV_FMT(YVU422, + 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, + C1_B_Cb, C2_R_Cr, C0_G_Y, + false, DPU_CHROMA_H2V1, 1, DPU_FORMAT_FLAG_YUV, + DPU_FETCH_LINEAR, 3), + + PLANAR_YUV_FMT(YUV444, + 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, + C2_R_Cr, C1_B_Cb, C0_G_Y, + false, DPU_CHROMA_RGB, 1, DPU_FORMAT_FLAG_YUV, + DPU_FETCH_LINEAR, 3), + + PLANAR_YUV_FMT(YVU444, + 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, + C1_B_Cb, C2_R_Cr, C0_G_Y, + false, DPU_CHROMA_RGB, 1, DPU_FORMAT_FLAG_YUV, + DPU_FETCH_LINEAR, 3), }; /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ccbee0f40ad7..949c86a44ec7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -195,6 +195,10 @@ static const uint32_t plane_formats_yuv[] = { DRM_FORMAT_YVYU, DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, + DRM_FORMAT_YUV422, + DRM_FORMAT_YVU422, + DRM_FORMAT_YUV444, + DRM_FORMAT_YVU444, }; static const u32 rotation_v2_formats[] = {