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Fri, 23 Feb 2024 13:45:23 -0600 From: Radhey Shyam Pandey To: , CC: , , Subject: [PATCH v2] usb: dwc3: core: enable CCI support for AMD-xilinx DWC3 controller Date: Sat, 24 Feb 2024 01:15:23 +0530 Message-ID: <1708717523-4006664-1-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003442:EE_|PH7PR12MB7212:EE_ X-MS-Office365-Filtering-Correlation-Id: ef0f0f12-f707-4997-526f-08dc34a7fb96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Wn1q26rprMhChTqrbrgAel/NVx/xvOJZG29IqkHHnlIUiVKZW15SCxZ4DBuCwGF/ZjQLNiexUyHXb6gEQpkKiIz4mW/qkgJEz/A779+crxojGao32JmTeBbPMNaaYlLYcsxjUBSX6P5Jg/J1toXV7Qfj8204jXkWDemqGchgqiKob6X2C+tABcGm7DCt0si2u7+MrEqKZaAu6LS4k3ASs1Fc94h8y+VgpR2eTYnCEl2pCFds0a24iYf0yi5JxQ0CBolpKR6fzssdQigecPFPSZms2P0zXwSB+J37PIS6p9ZY9GaWNDY6iqkhNLOceJZ93cx/OezG1sm1vikWfvEsX3+XjOkie2GGVw8k+rlwOsA6WZJw1gmjPr0ksqgH8EjjAb9vYUKSDinI1oCOxC6PM5NYBbJkEJkclVgqQ2DMV128o2tZAQhmfNenPDMW8p64XPhoD50+JvqKxQRs5689rihK/+3wrPT/LIccz/rM9E/B+ZzUrUWT6GiuLjc6yCVnBoZEmxb82Z526iB6mhHx42H0KqrbI6TJP1jxwIXL5ylXet4aFz/mzBKLXUy1RCgvIsYMkaKf2z0PQ4H9WILFknrDGa+416v5DVvMkGn2382IneLkF/mZP/sMLaEvt6clyP9o+bFlaDjg0DicSFU9aA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(36860700004)(46966006)(40470700004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2024 19:45:26.4102 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef0f0f12-f707-4997-526f-08dc34a7fb96 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003442.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7212 From: Piyush Mehta The GSBUSCFG0 register bits [31:16] are used to configure the cache type settings of the descriptor and data write/read transfers (Cacheable, Bufferable/ Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0 cache bits must be updated to support CCI enabled transfers in USB. Signed-off-by: Piyush Mehta Signed-off-by: Radhey Shyam Pandey ---- changes for v2: Make GSBUSCFG0 configuration specific to AMD-xilinx platform. Taken reference from existing commit ec5eb43813a4 ("usb: dwc3: core: add support for realtek SoCs custom's global register start address") v1 link: https://lore.kernel.org/all/20231013053448.11056-1-piyush.mehta@amd.com --- drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 5 +++++ 2 files changed, 31 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 3e55838c0001..3acd4ab3fcca 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -559,6 +560,29 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); } +static void dwc3_config_soc_bus(struct dwc3 *dwc) +{ + if (dwc->dev->of_node) { + struct device_node *parent = of_get_parent(dwc->dev->of_node); + + if (of_device_is_compatible(parent, "xlnx,zynqmp-dwc3") || + of_device_is_compatible(parent, "xlnx,versal-dwc3")) { + if (of_dma_is_coherent(dwc->dev->of_node)) { + u32 reg; + + reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + reg |= DWC3_GSBUSCFG0_DATRDREQINFO_MASK | + DWC3_GSBUSCFG0_DESRDREQINFO_MASK | + DWC3_GSBUSCFG0_DATWRREQINFO_MASK | + DWC3_GSBUSCFG0_DESWRREQINFO_MASK; + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg); + } + } + + of_node_put(parent); + } +} + static int dwc3_core_ulpi_init(struct dwc3 *dwc) { int intf; @@ -1256,6 +1280,8 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_set_incr_burst_type(dwc); + dwc3_config_soc_bus(dwc); + ret = dwc3_phy_power_on(dwc); if (ret) goto err_exit_phy; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 25dc0599345e..bf19a20e240f 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -175,6 +175,11 @@ #define DWC3_LLUCTL 0xd024 /* Bit fields */ +/* Global SoC Bus Configuration Register: AHB-prot/AXI-cache/OCP-ReqInfo */ +#define DWC3_GSBUSCFG0_DATRDREQINFO_MASK GENMASK(31, 28) +#define DWC3_GSBUSCFG0_DESRDREQINFO_MASK GENMASK(27, 24) +#define DWC3_GSBUSCFG0_DATWRREQINFO_MASK GENMASK(23, 20) +#define DWC3_GSBUSCFG0_DESWRREQINFO_MASK GENMASK(19, 16) /* Global SoC Bus Configuration INCRx Register 0 */ #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */