From patchwork Tue Feb 27 09:39:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastien Curutchet X-Patchwork-Id: 776712 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60A691369A0; Tue, 27 Feb 2024 09:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026814; cv=none; b=gllcxbkZktgQ/wxF8vDbhcZ/TnoIvzlNk+pIVx7IiQDLlv2ho6fq6R+0MnmGATyAfkza4VAdj/xQNGvzr2Jcl+FUMmEVyAd7Pu+N4C9YPzkz0sJ+StBz4DSoTPCIb1ayFT1mQAU8zjlhPF/z92klqIcUtEtpuQQuAuyaDcacxuE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026814; c=relaxed/simple; bh=9JjvHERcZ8YVK7b/Q4VF9ZW0OhQYLZLE7HJA4c4oEVs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gwO2nhf6+57jlIi6SJpSEGxGLxVqWLHgd/5CUrm0slzSb3lJNjjOy5X2AF6AiTG/FZ3O2JQwL5JdM4tbXioTSEu1YwD0k2F8WCIZz/tl0YL+l6cThvfRmc/8lr9YTCfUgQc6B43Z2xPXYp4pCyjcMAodM1LyyZjiNYubVxCFfKA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=l/BJeXbo; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="l/BJeXbo" Received: by mail.gandi.net (Postfix) with ESMTPA id 5FCE91BF20C; Tue, 27 Feb 2024 09:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709026804; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lvm6/L2WXUvtdtliXYOUV1u9RT8vkw9obusEbpY4LHk=; b=l/BJeXboAzq1t4BjFnD2es++LHkbZFXWmgrkX0aR4REVIzt4KMJ5FAFxCYspEGps/FbXDy Z3bMV2puAky55syDyN/tQZVqDlJpRTClyqH5iFYlBOJaCZBIX2PJPZmXtg61O8ySCmGKUw aBbY3IjojuuJORbqxR494qk/k86uhWSvZVcMHnTjmsU90YfnEomj6el5YsvqSQchk9Zj5b +jbQkP78Uc3nBa/LDHnV6mqGpCQ8EkU3negzntm/hxKfo1pCZF7KNimfktC50nDvopfo+9 7ndMdXlLbiekglz8oPiJ5u98zOkFZptaU+VIJsYuTXCrhmH+FRzjWWy8RFdmYQ== From: Bastien Curutchet To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pavel Machek , Lee Jones , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Bastien Curutchet Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, Thomas Petazzoni , herve.codina@bootlin.com, maxime.chevallier@bootlin.com, christophercordahi@nanometrics.ca Subject: [PATCH v2 1/6] dt-bindings: net: Add bindings for PHY DP83640 Date: Tue, 27 Feb 2024 10:39:40 +0100 Message-ID: <20240227093945.21525-2-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227093945.21525-1-bastien.curutchet@bootlin.com> References: <20240227093945.21525-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-leds@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: bastien.curutchet@bootlin.com The DP83640 is a PTP PHY. Some of his features can be enabled by hardware straps. There is not binding yet. Add a device tree binding to be able to override the hardware strap configuration when needed. Signed-off-by: Bastien Curutchet Reviewed-by: Conor Dooley --- .../devicetree/bindings/net/ti,dp83640.yaml | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83640.yaml diff --git a/Documentation/devicetree/bindings/net/ti,dp83640.yaml b/Documentation/devicetree/bindings/net/ti,dp83640.yaml new file mode 100644 index 000000000000..db1dc909d5cb --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83640.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Nanometrics Inc +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,dp83640.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DP83640 ethernet PHY + +allOf: + - $ref: ethernet-controller.yaml# + +maintainers: + - Bastien Curutchet + +description: | + The DP83640 Precision PHYTER device is an Ethernet PHY providing PTP + capabilities based on IEEE 1588 standard. + + This device interfaces directly to the MAC layer through the + IEEE 802.3 Standard Media Independent Interface (MII), or Reduced MII (RMII). + + Specifications about the Ethernet PHY can be found at: + https://www.ti.com/lit/gpn/dp83640 + +properties: + reg: + maxItems: 1 + + ti,fiber-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [ disable, enable ] + description: | + If present, enables or disables the FX Fiber Mode. + - disable = FX Fiber Mode disabled + - enable = FX Fiber Mode enabled + Fiber mode enabling can also be strapped. If the strap pin is not set + correctly or not set at all then this can be used to configure it. + + leds: + type: object + $ref: /schemas/leds/common.yaml# + description: | + Describes the three LEDs of the PHY. + +required: + - reg + +unevaluatedProperties: false + +examples: + - | + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + ti,fiber-mode = "disable"; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "activity"; + }; + led@1 { + reg = <1>; + label = "link"; + }; + led@2 { + reg = <2>; + label = "speed"; + }; + }; + }; + }; From patchwork Tue Feb 27 09:39:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastien Curutchet X-Patchwork-Id: 776366 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BAA0137C3E; Tue, 27 Feb 2024 09:40:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026816; cv=none; b=g8BZ4aetZKarkLRkJBKmP+/5a3LCnNlo8DlVugRRSQcx8kYw4cArcbWZOgryX+DgI3oZuhfVteZ7KU8q9Y5C+WCShHxUprSti/ECAMz83z+HA4A61db3i5ikUQ9r1ZNaQsj6u1uRCL2GezYk96CGqyVZ6SfIORiLb3/m8ZWO+3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026816; c=relaxed/simple; bh=MrAC+0ugacDW+NQuPpEBMoPhZSOJdpkLAl75R2nIfps=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=U+vXpyqdsXB03XMtqEdkFFkVvij9BdFy69AoXlWBPKccLs60eFvnVD3t1f37VT/G7VAF4JrudAxzhSlva/GYunDXPEz5KmYDv/gdzJaSZy0PnwBZMkB0OALbf7K85tfNtNO9HDCypiIU1ayk93p5uamrlfhSN7LBlp8VlSXFvOg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Toaf3mwm; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Toaf3mwm" Received: by mail.gandi.net (Postfix) with ESMTPA id 2EC051BF219; Tue, 27 Feb 2024 09:40:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709026806; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DlGBjihIRSEjSd8ST43CRqXi/gW9NM8DXJGmyMeDqgs=; b=Toaf3mwmcXc+zhwAdXDEsfX60JOGqIVKuao1hV1NpjdNWwC3ZVN01Me//rXPGJ+eLYHcfL kSMWLEnDollecV7xJfbPv2hjY6z+lZCSBr1pjiA4HrSa85czOC+xubyPYGRvx3MvRQBV89 eA4qj5Nz6XLAck1HzaOauJm2z5O+0HrUyH1x6H5UVsxRjycEbvcRzFBL5abB6HTMHTkqlU lnRHLFqfTAaQ/cna+QuUQ5NeO/r/EQoSpUcAMQ6O+w91HwmJki6LT7vWy15hf6pyRt0QXq rsqDf+6Po1Bwb5gyuzMfzbb9EUVSIqb/v8/OnU9GA1zMwwXiJk6JrCfj0LuXuA== From: Bastien Curutchet To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pavel Machek , Lee Jones , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Bastien Curutchet Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, Thomas Petazzoni , herve.codina@bootlin.com, maxime.chevallier@bootlin.com, christophercordahi@nanometrics.ca Subject: [PATCH v2 2/6] leds: trigger: Create a new LED netdev trigger for collision Date: Tue, 27 Feb 2024 10:39:41 +0100 Message-ID: <20240227093945.21525-3-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227093945.21525-1-bastien.curutchet@bootlin.com> References: <20240227093945.21525-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-leds@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: bastien.curutchet@bootlin.com Collisions on link does not fit into one of the existing netdev triggers. Add TRIGGER_NETDEV_COLLISION in the enum led_trigger_netdev_modes. Add its definition in Documentation. Add its handling in ledtrig-netdev, it can only be supported by hardware so no software fallback is implemented. Signed-off-by: Bastien Curutchet --- .../ABI/testing/sysfs-class-led-trigger-netdev | 11 +++++++++++ drivers/leds/trigger/ledtrig-netdev.c | 4 ++++ include/linux/leds.h | 1 + 3 files changed, 16 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-class-led-trigger-netdev b/Documentation/ABI/testing/sysfs-class-led-trigger-netdev index a6c307c4befa..fbb2bc1d6108 100644 --- a/Documentation/ABI/testing/sysfs-class-led-trigger-netdev +++ b/Documentation/ABI/testing/sysfs-class-led-trigger-netdev @@ -178,3 +178,14 @@ Description: If set to 1, the LED's normal state reflects the link full duplex state of the named network device. Setting this value also immediately changes the LED state. + +What: /sys/class/leds//collision +Date: Feb 2024 +KernelVersion: 6.8 +Contact: linux-leds@vger.kernel.org +Description: + Signal collision of the named network device. + + If set to 0 (default), the LED's normal state is off. + + If set to 1, the LED's normal state reflects collisions. diff --git a/drivers/leds/trigger/ledtrig-netdev.c b/drivers/leds/trigger/ledtrig-netdev.c index 8e5475819590..5c17b8e27d5c 100644 --- a/drivers/leds/trigger/ledtrig-netdev.c +++ b/drivers/leds/trigger/ledtrig-netdev.c @@ -318,6 +318,7 @@ static ssize_t netdev_led_attr_show(struct device *dev, char *buf, case TRIGGER_NETDEV_FULL_DUPLEX: case TRIGGER_NETDEV_TX: case TRIGGER_NETDEV_RX: + case TRIGGER_NETDEV_COLLISION: bit = attr; break; default: @@ -352,6 +353,7 @@ static ssize_t netdev_led_attr_store(struct device *dev, const char *buf, case TRIGGER_NETDEV_FULL_DUPLEX: case TRIGGER_NETDEV_TX: case TRIGGER_NETDEV_RX: + case TRIGGER_NETDEV_COLLISION: bit = attr; break; default: @@ -410,6 +412,7 @@ DEFINE_NETDEV_TRIGGER(half_duplex, TRIGGER_NETDEV_HALF_DUPLEX); DEFINE_NETDEV_TRIGGER(full_duplex, TRIGGER_NETDEV_FULL_DUPLEX); DEFINE_NETDEV_TRIGGER(tx, TRIGGER_NETDEV_TX); DEFINE_NETDEV_TRIGGER(rx, TRIGGER_NETDEV_RX); +DEFINE_NETDEV_TRIGGER(collision, TRIGGER_NETDEV_COLLISION); static ssize_t interval_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -473,6 +476,7 @@ static struct attribute *netdev_trig_attrs[] = { &dev_attr_tx.attr, &dev_attr_interval.attr, &dev_attr_offloaded.attr, + &dev_attr_collision.attr, NULL }; ATTRIBUTE_GROUPS(netdev_trig); diff --git a/include/linux/leds.h b/include/linux/leds.h index 4754b02d3a2c..8864d6ce8185 100644 --- a/include/linux/leds.h +++ b/include/linux/leds.h @@ -578,6 +578,7 @@ enum led_trigger_netdev_modes { TRIGGER_NETDEV_FULL_DUPLEX, TRIGGER_NETDEV_TX, TRIGGER_NETDEV_RX, + TRIGGER_NETDEV_COLLISION, /* Keep last */ __TRIGGER_NETDEV_MAX, From patchwork Tue Feb 27 09:39:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastien Curutchet X-Patchwork-Id: 776713 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C28A313699F; Tue, 27 Feb 2024 09:40:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026813; cv=none; b=t2osUZE5JD+pDlmGrag5UxONo0ILG/0Gww5g+uJBDFerDK0c1KtJm7ENfaf92jhPvBdbTyDNdkBlTXDaXOJSOEN8YIcLQ50cx/nDIGR4m4Jql6cI8n8HJbVUJ3PZaZCchGnCnjMg73f80omqhG6qamVGAClZqPVdxe3L46PGr8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026813; c=relaxed/simple; bh=uqtJGHKVHC/j4i5cKjZOrsQelhUV4vYr6TiYM/bYruQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aq7Hz5sq0u0JTToxLkV3axBr2EDpYTE0DMeDCHQdzuKzWD9Z+XREv+Y3z9kSuVeI9bNprTOKuCUjqkEJjUABBLMS2u1l6BMnOiZwv2kk6b6gUaesHzXfheKpw349kE7f0n1ikMyapE8FiZI7Le9fj01LaP7Cx8vl5H0sSVVE4BA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LFhQM41E; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LFhQM41E" Received: by mail.gandi.net (Postfix) with ESMTPA id 01A8B1BF212; Tue, 27 Feb 2024 09:40:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709026808; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FpCvRT3LuSD1Mcc/k7iKXm6hU1A4RCeIB4aBNCXWOa0=; b=LFhQM41EcxzoRb4uelw7/FQMFlnzcKBFo75Y8VbXklZMIKxCtW7EgB3D7ah+XlO1xhtmzE E9Mla+lSf+f1RypQ07S60o1BB2k2N0VlH6Zje+yNeKJEcTlhWf6qaE32hmzwuH0VWKL3lw XjLlAxeoVjhAxYEmjYnOpsW0krn/a4v9dQvqI6yQ0cuEl6k3JeJG1mR1fohr8Q6Gsfrgc3 Vgh3nCxajIgBGz/QHnrRsRSJXzA/ZsKZOdKoZtLRU498V/1YX6CnssX3rpp+biOMPkncOs BIhx+bRhb+Lhpf/WuxDLa5VW9CV4WYw2uiJFCyE4/lxXuRmkgozTppFZ3an33A== From: Bastien Curutchet To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pavel Machek , Lee Jones , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Bastien Curutchet Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, Thomas Petazzoni , herve.codina@bootlin.com, maxime.chevallier@bootlin.com, christophercordahi@nanometrics.ca Subject: [PATCH v2 3/6] net: phy: DP83640: Add LED handling Date: Tue, 27 Feb 2024 10:39:42 +0100 Message-ID: <20240227093945.21525-4-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227093945.21525-1-bastien.curutchet@bootlin.com> References: <20240227093945.21525-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-leds@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: bastien.curutchet@bootlin.com The PHY have three LED : Activity LED, Speed LED and Link LED. The PHY offers three configuration modes for them. The driver does not handle them. Add LED handling through the /sys/class/leds interface. On every mode the Speed LED indicates the speed (10Mbps or 100 Mbps) and the Link LED indicates whether the link is good or not. Link LED will also reflects link activity in mode 2 and 3. The Activity LED can reflect the link activity (mode 1), the link's duplex (mode 2) or collisions on the link (mode 3). Only the Activity LED can have its hardware configuration updated, it has an impact on Link LED as activity reflexion is added on it on modes 2 and 3 Signed-off-by: Bastien Curutchet --- drivers/net/phy/dp83640.c | 176 ++++++++++++++++++++++++++++++++++ drivers/net/phy/dp83640_reg.h | 11 +++ 2 files changed, 187 insertions(+) diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c index 5c42c47dc564..c46c81ef0ad0 100644 --- a/drivers/net/phy/dp83640.c +++ b/drivers/net/phy/dp83640.c @@ -59,6 +59,22 @@ MII_DP83640_MISR_SPD_INT |\ MII_DP83640_MISR_LINK_INT) +#define DP83640_ACTLED_IDX 0 +#define DP83640_LNKLED_IDX 1 +#define DP83640_SPDLED_IDX 2 +/* LNKLED = ON for Good Link, OFF for No Link */ +/* SPDLED = ON in 100 Mb/s, OFF in 10 Mb/s */ +/* ACTLED = ON for Activity, OFF for No Activity */ +#define DP83640_LED_MODE_1 1 +/* LNKLED = ON for Good Link, Blink for Activity */ +/* SPDLED = ON in 100 Mb/s, OFF in 10 Mb/s */ +/* ACTLED = ON for Collision, OFF for No Collision */ +#define DP83640_LED_MODE_2 2 +/* LNKLED = ON for Good Link, Blink for Activity */ +/* SPDLED = ON in 100 Mb/s, OFF in 10 Mb/s */ +/* ACTLED = ON for Full-Duplex, OFF for Half-Duplex */ +#define DP83640_LED_MODE_3 3 + /* phyter seems to miss the mark by 16 ns */ #define ADJTIME_FIX 16 @@ -1515,6 +1531,161 @@ static void dp83640_remove(struct phy_device *phydev) kfree(dp83640); } +static int dp83640_led_brightness_set(struct phy_device *phydev, u8 index, + enum led_brightness brightness) +{ + int val; + + if (index > DP83640_SPDLED_IDX) + return -EINVAL; + + phy_write(phydev, PAGESEL, 0); + + val = phy_read(phydev, LEDCR) & ~DP83640_LED_DIS(index); + val |= DP83640_LED_DRV(index); + if (brightness) + val |= DP83640_LED_VAL(index); + else + val &= ~DP83640_LED_VAL(index); + phy_write(phydev, LEDCR, val); + + return 0; +} + +/** + * dp83640_led_mode - Check the trigger netdev rules and compute the associated + * configuration mode + * @index: The targeted LED + * @rules: Rules to be checked + * + * Returns the mode that is to be set in LED_CFNG. If the rules are not + * supported by the PHY, returns -ENOTSUPP. If the rules are supported but don't + * impact the LED configuration, returns 0 + */ +static int dp83640_led_mode(u8 index, unsigned long rules) +{ + /* Only changes on ACTLED have an impact on LED Mode configuration */ + switch (index) { + case DP83640_ACTLED_IDX: + switch (rules) { + case BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX): + return DP83640_LED_MODE_1; + case BIT(TRIGGER_NETDEV_COLLISION): + return DP83640_LED_MODE_2; + case BIT(TRIGGER_NETDEV_FULL_DUPLEX) | + BIT(TRIGGER_NETDEV_HALF_DUPLEX): + return DP83640_LED_MODE_3; + default: + return -EOPNOTSUPP; + } + + case DP83640_SPDLED_IDX: + /* SPDLED has the same function in every mode */ + switch (rules) { + case BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK_100): + return 0; + default: + return -EOPNOTSUPP; + } + + case DP83640_LNKLED_IDX: + /* LNKLED has the same function in every mode */ + switch (rules) { + case BIT(TRIGGER_NETDEV_LINK): + return 0; + default: + return -EOPNOTSUPP; + } + default: + return -EINVAL; + } +} + +static int dp83640_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + int ret; + + ret = dp83640_led_mode(index, rules); + + if (ret < 0) + return ret; + + return 0; +} + +static int dp83640_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + int mode, val; + + mode = dp83640_led_mode(index, rules); + if (mode < 0) + return mode; + + if (mode) { + phy_write(phydev, PAGESEL, 0); + val = phy_read(phydev, PHYCR) & ~(LED_CNFG_1 | LED_CNFG_0); + switch (mode) { + case DP83640_LED_MODE_1: + val |= LED_CNFG_0; + break; + case DP83640_LED_MODE_2: + /* Keeping LED_CNFG_1 and LED_CNFG_0 unset */ + break; + case DP83640_LED_MODE_3: + val |= LED_CNFG_1; + break; + default: + return -EINVAL; + } + phy_write(phydev, PHYCR, val); + } + + val = phy_read(phydev, LEDCR); + val &= ~(DP83640_LED_DIS(index) | DP83640_LED_DRV(index)); + phy_write(phydev, LEDCR, val); + + return 0; +} + +static int dp83640_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + int val; + + switch (index) { + case DP83640_ACTLED_IDX: + phy_write(phydev, PAGESEL, 0); + val = phy_read(phydev, PHYCR); + if (val & LED_CNFG_0) { + /* Mode 1 */ + *rules = BIT(TRIGGER_NETDEV_TX) | BIT(TRIGGER_NETDEV_RX); + } else if (val & LED_CNFG_1) { + /* Mode 3 */ + *rules = BIT(TRIGGER_NETDEV_FULL_DUPLEX) | + BIT(TRIGGER_NETDEV_HALF_DUPLEX); + } else { + /* Mode 2 */ + *rules = BIT(TRIGGER_NETDEV_COLLISION); + } + break; + + case DP83640_LNKLED_IDX: + *rules = BIT(TRIGGER_NETDEV_LINK); + break; + + case DP83640_SPDLED_IDX: + *rules = BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100); + break; + default: + return -EINVAL; + } + + return 0; +} + static struct phy_driver dp83640_driver = { .phy_id = DP83640_PHY_ID, .phy_id_mask = 0xfffffff0, @@ -1526,6 +1697,11 @@ static struct phy_driver dp83640_driver = { .config_init = dp83640_config_init, .config_intr = dp83640_config_intr, .handle_interrupt = dp83640_handle_interrupt, + + .led_brightness_set = dp83640_led_brightness_set, + .led_hw_is_supported = dp83640_led_hw_is_supported, + .led_hw_control_set = dp83640_led_hw_control_set, + .led_hw_control_get = dp83640_led_hw_control_get, }; static int __init dp83640_init(void) diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h index daae7fa58fb8..09dd2d2527c7 100644 --- a/drivers/net/phy/dp83640_reg.h +++ b/drivers/net/phy/dp83640_reg.h @@ -6,6 +6,8 @@ #define HAVE_DP83640_REGISTERS /* #define PAGE0 0x0000 */ +#define LEDCR 0x0018 /* PHY Control Register */ +#define PHYCR 0x0019 /* PHY Control Register */ #define PHYCR2 0x001c /* PHY Control Register 2 */ #define PAGE4 0x0004 @@ -50,6 +52,15 @@ #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */ #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */ +/* Bit definitions for the LEDCR register */ +#define DP83640_LED_DIS(x) BIT((x) + 9) /* Disable LED */ +#define DP83640_LED_DRV(x) BIT((x) + 3) /* Force LED val to output */ +#define DP83640_LED_VAL(x) BIT((x)) /* LED val */ + +/* Bit definitions for the PHYCR register */ +#define LED_CNFG_0 BIT(5) /* LED configuration, bit 0 */ +#define LED_CNFG_1 BIT(6) /* LED configuration, bit 1 */ + /* Bit definitions for the PHYCR2 register */ #define BC_WRITE (1<<11) /* Broadcast Write Enable */ From patchwork Tue Feb 27 09:39:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastien Curutchet X-Patchwork-Id: 776367 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 632031369A2; Tue, 27 Feb 2024 09:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026814; cv=none; b=QaLixcvkyZ6bX3oQ9Du+85Tsf4A3qJMyXGHZgdvWMNzxN9O+nRti09X011uWXz/mhdC4Uc7z4VJVD301NdIC0Fktqpt1A+HmknMeHlj/3AvfEoKEbcGpJwAzIUMs85r8UVzNDx49FHiNKpIeeLz+fuYnZJGwN0wBjunIuj0/tJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026814; c=relaxed/simple; bh=wEhydF0uAkZdVJjRAdGWXmqjpXqyXP1qcx0hncX2AaQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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bh=DImN79hQFdqQ+Xbnqbaw0AlsT0SBJRI+BKdyo30mw/4=; b=BVrfdssOBrbkIODUzKD1+KhDBq7FT8u1tLb8wnnTm4a2+Nn+kyU8jFUS1Az33QCdkRfjKw jIIIZsY+8QqRXgx+7Iisi8pP0/g9j5o5EO5Vks3NOvJq7/Y2wn4Q2ppWA+x+K/lDgKJA98 ZQ18RU4+OywqWsKqc7yFWLp6YcHABJqRsgS1Huc+A/njJkAl7v5J9DAxfY4yt7get/nyzj F/fN1PU4ClotmT8tgoSR5PhUYdml8orinEc3xwsZuhUMTcCbISukv239TDojCnJt+OWdcf 944oZLQrLDYbzTZ9u9i/5Y37714BZk6nManBs93Hw7TC34W/CoAmZh5s/nO2tg== From: Bastien Curutchet To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pavel Machek , Lee Jones , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Bastien Curutchet Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, Thomas Petazzoni , herve.codina@bootlin.com, maxime.chevallier@bootlin.com, christophercordahi@nanometrics.ca Subject: [PATCH v2 4/6] net: phy: DP83640: Add EDPD management Date: Tue, 27 Feb 2024 10:39:43 +0100 Message-ID: <20240227093945.21525-5-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227093945.21525-1-bastien.curutchet@bootlin.com> References: <20240227093945.21525-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-leds@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: bastien.curutchet@bootlin.com The driver does not support enabling/disabling Energy Detect Power Down (EDPD). The PHY itself support EDPD. Add missing part in the driver in order to have this support based on ethtool {set,get}_phy_tunable functions. Signed-off-by: Bastien Curutchet --- drivers/net/phy/dp83640.c | 62 +++++++++++++++++++++++++++++++++++ drivers/net/phy/dp83640_reg.h | 4 +++ 2 files changed, 66 insertions(+) diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c index c46c81ef0ad0..16c9fda50b19 100644 --- a/drivers/net/phy/dp83640.c +++ b/drivers/net/phy/dp83640.c @@ -1531,6 +1531,66 @@ static void dp83640_remove(struct phy_device *phydev) kfree(dp83640); } +static int dp83640_get_edpd(struct phy_device *phydev, u16 *edpd) +{ + int val; + + phy_write(phydev, PAGESEL, 0); + val = phy_read(phydev, EDCR); + if (val & ED_EN) + *edpd = 2000; /* 2 seconds */ + else + *edpd = ETHTOOL_PHY_EDPD_DISABLE; + + return 0; +} + +static int dp83640_set_edpd(struct phy_device *phydev, u16 edpd) +{ + int val; + + phy_write(phydev, PAGESEL, 0); + val = phy_read(phydev, EDCR); + + switch (edpd) { + case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS: + case 2000: /* 2 seconds */ + val |= ED_EN; + break; + case ETHTOOL_PHY_EDPD_DISABLE: + val &= ~ED_EN; + break; + default: + return -EINVAL; + } + + phy_write(phydev, EDCR, val); + + return 0; +} + +static int dp83640_get_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_EDPD: + return dp83640_get_edpd(phydev, data); + default: + return -EOPNOTSUPP; + } +} + +static int dp83640_set_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, const void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_EDPD: + return dp83640_set_edpd(phydev, *(u16 *)data); + default: + return -EOPNOTSUPP; + } +} + static int dp83640_led_brightness_set(struct phy_device *phydev, u8 index, enum led_brightness brightness) { @@ -1692,6 +1752,8 @@ static struct phy_driver dp83640_driver = { .name = "NatSemi DP83640", /* PHY_BASIC_FEATURES */ .probe = dp83640_probe, + .get_tunable = dp83640_get_tunable, + .set_tunable = dp83640_set_tunable, .remove = dp83640_remove, .soft_reset = dp83640_soft_reset, .config_init = dp83640_config_init, diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h index 09dd2d2527c7..bf34d422d91e 100644 --- a/drivers/net/phy/dp83640_reg.h +++ b/drivers/net/phy/dp83640_reg.h @@ -9,6 +9,7 @@ #define LEDCR 0x0018 /* PHY Control Register */ #define PHYCR 0x0019 /* PHY Control Register */ #define PHYCR2 0x001c /* PHY Control Register 2 */ +#define EDCR 0x001D /* Energy Detect Control Register */ #define PAGE4 0x0004 #define PTP_CTL 0x0014 /* PTP Control Register */ @@ -64,6 +65,9 @@ /* Bit definitions for the PHYCR2 register */ #define BC_WRITE (1<<11) /* Broadcast Write Enable */ +/* Bit definitions for the EDCR register */ +#define ED_EN BIT(15) /* Enable Energy Detect Mode */ + /* Bit definitions for the PTP_CTL register */ #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */ #define TRIG_SEL_MASK (0x7) From patchwork Tue Feb 27 09:39:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastien Curutchet X-Patchwork-Id: 776365 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B5521369B5; Tue, 27 Feb 2024 09:40:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026817; cv=none; b=BkbLQhPNx7YrrqbRFUFQTQpUqh+OlrvQeceDCUUn+S3wLMyb4txRUzxH8VPsdyjh3pFhBoq9i9iomNt+RVeyK+85ZhqmELWY1AiisvxvPYjELxpOAdK/KNGFqiK+mWQ0/TRyqOQeAnn/mlt/ExQLlA7blQcT3Yfvukq+CO3Ohs0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026817; c=relaxed/simple; bh=NYYmMCzH7vimTij6Ubq0mii2fz8ZW2rnD23U4YlBxqA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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bh=OxjHn9p9H9NJifATQZkPfSnDEUUsarNIhRN6DP6TGhI=; b=kWckHP8S+V229WSbjHSvoQVhZZJSxhIo6Cx4XFA6WBbIsuRM/rwpU8e2qqTX3IHOSbtaFY XubWCr0zR3q6P5yS/iInceHN8S1Gott/NkhiIpu+AFeqdyH+/ltf7QKq7hUWyscU2xQo4K TWNpsuhPRJ5jA7LuRV+avRLzdZwpOqTf1/tutTEG6s8GNU7THV/Eaizpnq5PEjaMD/qSMf LS6ZcWGFGUic4J8E/KIsZBbLTN7pIjQOTdRTeYtSDtitd7gtNRZtYbEPwVOLr9a9/RKE4V zdrXckJSWqMwjW8tJl60uZ7roThGxnfTxLTImMqdLuQnQvjQOF5YACgwtkxG1g== From: Bastien Curutchet To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pavel Machek , Lee Jones , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Bastien Curutchet Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, Thomas Petazzoni , herve.codina@bootlin.com, maxime.chevallier@bootlin.com, christophercordahi@nanometrics.ca Subject: [PATCH v2 5/6] net: phy: DP83640: Explicitly disabling PHY Control Frames Date: Tue, 27 Feb 2024 10:39:44 +0100 Message-ID: <20240227093945.21525-6-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227093945.21525-1-bastien.curutchet@bootlin.com> References: <20240227093945.21525-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-leds@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: bastien.curutchet@bootlin.com The PHY offers a PHY control frame feature that allows to access PHY registers through the MAC transmit data interface. This functionality is not handled by the driver but can be enabled via hardware strap or register access. Disable the feature in config_init() to save some latency on MII packets. Signed-off-by: Bastien Curutchet --- drivers/net/phy/dp83640.c | 6 ++++++ drivers/net/phy/dp83640_reg.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c index 16c9fda50b19..b371dea23937 100644 --- a/drivers/net/phy/dp83640.c +++ b/drivers/net/phy/dp83640.c @@ -1120,6 +1120,7 @@ static int dp83640_config_init(struct phy_device *phydev) { struct dp83640_private *dp83640 = phydev->priv; struct dp83640_clock *clock = dp83640->clock; + int val; if (clock->chosen && !list_empty(&clock->phylist)) recalibrate(clock); @@ -1135,6 +1136,11 @@ static int dp83640_config_init(struct phy_device *phydev) ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); mutex_unlock(&clock->extreg_lock); + /* Disable unused PHY control frames */ + phy_write(phydev, PAGESEL, 0); + val = phy_read(phydev, PCFCR) & ~PCF_EN; + phy_write(phydev, PCFCR, val); + return 0; } diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h index bf34d422d91e..b5adb8958c08 100644 --- a/drivers/net/phy/dp83640_reg.h +++ b/drivers/net/phy/dp83640_reg.h @@ -10,6 +10,7 @@ #define PHYCR 0x0019 /* PHY Control Register */ #define PHYCR2 0x001c /* PHY Control Register 2 */ #define EDCR 0x001D /* Energy Detect Control Register */ +#define PCFCR 0x001F /* PHY Control Frames Control Register */ #define PAGE4 0x0004 #define PTP_CTL 0x0014 /* PTP Control Register */ @@ -68,6 +69,9 @@ /* Bit definitions for the EDCR register */ #define ED_EN BIT(15) /* Enable Energy Detect Mode */ +/* Bit definitions for the PCFCR register */ +#define PCF_EN BIT(0) /* Enable PHY Control Frames */ + /* Bit definitions for the PTP_CTL register */ #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */ #define TRIG_SEL_MASK (0x7) From patchwork Tue Feb 27 09:39:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastien Curutchet X-Patchwork-Id: 776711 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ED461384A9; Tue, 27 Feb 2024 09:40:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026817; cv=none; b=JqQ03QaEtymczjWvWTHfGawlgwFNUYhqCBaXwpe/PxL46yC6WYbGq0VEcNnZ2FlJuHmKLsqQhJctJfiB1VSMnze4mh8QYGa3v/ARBDx2CQhUGEkO/oNZxB0yBlkQWmXy8R3ktNh5D6H/UCqmhW8syNjatMcZKasEz+69YA1NBa4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709026817; c=relaxed/simple; bh=WKyTm9tvEpOHc9SUmAoFjXDcY9NXpqkPz111tBhUrs0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LiYrgGId+YFjBL8BV1Ik1rOhzaaosfEtetQNUj1Lbogm5T193omDE3+YfhmkT6ILK++cQNkl12lxwCni6IyG0aDzk5/lfbZTwkp+xMFufDodL0i+MRM99lelKKtf+eCndSqrD3vGnCcg6QDrXWXE7tb2zuiD0kEPwpt6Vm63WA8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ele8Kxd/; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ele8Kxd/" Received: by mail.gandi.net (Postfix) with ESMTPA id 500A91BF21B; Tue, 27 Feb 2024 09:40:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709026813; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rgaNBK3volcj4FhXmaNO+Po++qQCUID/slrT9VBh2II=; b=ele8Kxd/pDw2DVnj7w1ZSTVzt5dJp44Z34mJh3wAoCCb1F8Uowblgmmil72EwgmkzjIbbq BnV0zkfG0sko4SN3vb3/BWQ/gGE3L68HdzcY2vqoe79/DT+2DyGyv2Yr6dAGkh5Q8VVSuB PvND6VZRvmeiIZUB8ODZVYVHr1W5pqL9g0E5v3GoDa2QO1eIq+yfgPuPqjaMkqKqZpAssh ZwlzFMmrhJzAeju2hJO5tc4OKbrrq1B1wFgI31ZAwpE54t+edRu4BFKmyTSr1n1G22TrXu mg5xISlvcK4u7ko++V1NXOoQ4jc5fEgEYKuEsupodVlBQ1ZvcE57gIFjl7rCYg== From: Bastien Curutchet To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Pavel Machek , Lee Jones , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Bastien Curutchet Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org, Thomas Petazzoni , herve.codina@bootlin.com, maxime.chevallier@bootlin.com, christophercordahi@nanometrics.ca Subject: [PATCH v2 6/6] net: phy: DP83640: Add fiber mode enabling/disabling from device tree Date: Tue, 27 Feb 2024 10:39:45 +0100 Message-ID: <20240227093945.21525-7-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227093945.21525-1-bastien.curutchet@bootlin.com> References: <20240227093945.21525-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-leds@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: bastien.curutchet@bootlin.com The PHY is able to use copper or fiber. The fiber mode can be enabled or disabled by hardware strap. If hardware strap is incorrect, PHY can't establish link. Add a DT attribute 'ti,fiber-mode' that can be use to override the hardware strap configuration. If the property is not present, hardware strap configuration is left as is. Signed-off-by: Bastien Curutchet --- drivers/net/phy/dp83640.c | 55 +++++++++++++++++++++++++++++++++++ drivers/net/phy/dp83640_reg.h | 5 ++++ 2 files changed, 60 insertions(+) diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c index b371dea23937..886f2bc3710d 100644 --- a/drivers/net/phy/dp83640.c +++ b/drivers/net/phy/dp83640.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -141,6 +142,11 @@ struct dp83640_private { /* queues of incoming and outgoing packets */ struct sk_buff_head rx_queue; struct sk_buff_head tx_queue; + +#define FIBER_MODE_DEFAULT 0 +#define FIBER_MODE_ENABLE 1 +#define FIBER_MODE_DISABLE 2 + int fiber; }; struct dp83640_clock { @@ -1141,6 +1147,17 @@ static int dp83640_config_init(struct phy_device *phydev) val = phy_read(phydev, PCFCR) & ~PCF_EN; phy_write(phydev, PCFCR, val); + if (dp83640->fiber != FIBER_MODE_DEFAULT) { + val = phy_read(phydev, PCSR) & ~FX_EN; + if (dp83640->fiber == FIBER_MODE_ENABLE) + val |= FX_EN; + phy_write(phydev, PCSR, val); + + /* Write SOFT_RESET bit to ensure configuration */ + val = phy_read(phydev, PHYCR2) | SOFT_RESET; + phy_write(phydev, PHYCR2, val); + } + return 0; } @@ -1440,6 +1457,39 @@ static int dp83640_ts_info(struct mii_timestamper *mii_ts, return 0; } +#ifdef CONFIG_OF_MDIO +static int dp83640_of_init(struct phy_device *phydev) +{ + struct dp83640_private *dp83640 = phydev->priv; + struct device *dev = &phydev->mdio.dev; + struct device_node *of_node = dev->of_node; + const char *fiber; + int ret; + + if (of_property_present(of_node, "ti,fiber-mode")) { + ret = of_property_read_string(of_node, "ti,fiber-mode", &fiber); + if (ret) + return ret; + + dp83640->fiber = FIBER_MODE_DEFAULT; + if (!strncmp(fiber, "enable", 6)) + dp83640->fiber = FIBER_MODE_ENABLE; + else if (!strncmp(fiber, "disable", 7)) + dp83640->fiber = FIBER_MODE_DISABLE; + else + return -EINVAL; + } + + return 0; +} +#else +static int dp83640_of_init(struct phy_device *phydev) +{ + dp83640->fiber = FIBER_MODE_DEFAULT; + return 0; +} +#endif /* CONFIG_OF_MDIO */ + static int dp83640_probe(struct phy_device *phydev) { struct dp83640_clock *clock; @@ -1472,6 +1522,10 @@ static int dp83640_probe(struct phy_device *phydev) phydev->mii_ts = &dp83640->mii_ts; phydev->priv = dp83640; + err = dp83640_of_init(phydev); + if (err < 0) + goto of_failed; + spin_lock_init(&dp83640->rx_lock); skb_queue_head_init(&dp83640->rx_queue); skb_queue_head_init(&dp83640->tx_queue); @@ -1494,6 +1548,7 @@ static int dp83640_probe(struct phy_device *phydev) no_register: clock->chosen = NULL; +of_failed: kfree(dp83640); no_memory: dp83640_clock_put(clock); diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h index b5adb8958c08..cbecf04da5a5 100644 --- a/drivers/net/phy/dp83640_reg.h +++ b/drivers/net/phy/dp83640_reg.h @@ -6,6 +6,7 @@ #define HAVE_DP83640_REGISTERS /* #define PAGE0 0x0000 */ +#define PCSR 0x0016 /* PCS Configuration and Status Register */ #define LEDCR 0x0018 /* PHY Control Register */ #define PHYCR 0x0019 /* PHY Control Register */ #define PHYCR2 0x001c /* PHY Control Register 2 */ @@ -54,6 +55,9 @@ #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */ #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */ +/* Bit definitions for the PCSR register */ +#define FX_EN BIT(6) /* Enable FX Fiber Mode */ + /* Bit definitions for the LEDCR register */ #define DP83640_LED_DIS(x) BIT((x) + 9) /* Disable LED */ #define DP83640_LED_DRV(x) BIT((x) + 3) /* Force LED val to output */ @@ -64,6 +68,7 @@ #define LED_CNFG_1 BIT(6) /* LED configuration, bit 1 */ /* Bit definitions for the PHYCR2 register */ +#define SOFT_RESET BIT(9) /* Soft Reset */ #define BC_WRITE (1<<11) /* Broadcast Write Enable */ /* Bit definitions for the EDCR register */