From patchwork Thu Sep 26 11:19:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 174456 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1908040ill; Thu, 26 Sep 2019 04:19:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxp8ruROPBoW0UMmIGC4rt2bwZEkb0J/uQy8yhlun3rB2mLSh83PQL3GtkWOf931tXIT+mU X-Received: by 2002:a17:906:7e06:: with SMTP id e6mr2555393ejr.149.1569496768346; Thu, 26 Sep 2019 04:19:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569496768; cv=none; d=google.com; s=arc-20160816; b=yY3cHUyig9jtjODKBmum/2xlbw7z+4izJYzRv34E37eU3auJlS69DbvByzR9eJZTCH irplLI7ym2Ws7CpWPVm6SGEAxohXRBbUG/GUBkUBXnreMVelzTHqMXnnmsRf7VLJPcC2 VrI15PcwFMUg09IjGy+CHgV1R+rC2QUkEPV31884JbWvvJ9MhUPxwTFn/B9i1pbHBthL pUP6FikMw/ky1VZEojfquUoqFxJ0cSgEyCPN8XxLfoUm0Trkf56g05wW74IVMsNArmid PO0moXDpHzhYmxy/nEYTs+Q6/UzH1yrqgMbIbbl0m0J42Px/M+ygsFXMTfr9N44AtTxt W4lA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gYeM81ZJ0PDJp9Yxe7eqp+2YLGoUzBTCt62WZh8PCUA=; b=y0KyQyht//plE70x5Zz28V2t+wbUs7GD0SLjXZ0sGRLCe8tgcxNdY33OBRZyZjV/DQ WVLDBvWvjRm4unqP/nzWlkThvNbUmle1Pi2eUjDcsylZ1gutRgum4NklIXyXGDYRVaSd di6eBzafqsfgQcSdZ/1Xl4S1hw72vgkzD1p9HF6lWMB8NGWy7J6zTn7PZtjZwlZS6B73 WpcvtOFD4f3TAmf7dJiqguc11FjWUxJWZVOtsjV6zEhqT6Y7ij+BStqlnT8nU/vWtcr+ S9lEZa1s1P29hUOf4nMAifpwxCfGB6MVE7/eW9eCOPQPciZIt7nN9ubxawz2vWQPD5in 5P/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hYR2Zwaz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j11si1236572edj.43.2019.09.26.04.19.28; Thu, 26 Sep 2019 04:19:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hYR2Zwaz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726420AbfIZLTX (ORCPT + 26 others); Thu, 26 Sep 2019 07:19:23 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:48892 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725819AbfIZLTW (ORCPT ); Thu, 26 Sep 2019 07:19:22 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBJF47022824; Thu, 26 Sep 2019 06:19:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569496755; bh=gYeM81ZJ0PDJp9Yxe7eqp+2YLGoUzBTCt62WZh8PCUA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hYR2ZwazZKeQfAknCA8Lfqt6ffg1ZGT3pP2Z9tnZxnrNaEfNm0+cqvulVZv3XnPaM DWuuL4AbK1dNRLHHQgmgOznEwKdnmgM1s5iD8iQn7jP8WKZH4opIY1+e4TgPSd8GuP kbRgYMcydK3hlQKWFkF6ZyLKq2RGiKSQ8e8Ehii8= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBJFX4038351 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:19:15 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:19:15 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:19:07 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBJAds013885; Thu, 26 Sep 2019 06:19:13 -0500 From: Peter Ujfalusi To: , CC: , , , Subject: [PATCH v3 1/3] dt-bindings: dmaengine: dma-common: Change dma-channel-mask to uint32-array Date: Thu, 26 Sep 2019 14:19:52 +0300 Message-ID: <20190926111954.9184-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190926111954.9184-1-peter.ujfalusi@ti.com> References: <20190926111954.9184-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make the dma-channel-mask to be usable for controllers with more than 32 channels. Signed-off-by: Peter Ujfalusi --- Documentation/devicetree/bindings/dma/dma-common.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/dma/dma-common.yaml b/Documentation/devicetree/bindings/dma/dma-common.yaml index ed0a49a6f020..4527f20301ff 100644 --- a/Documentation/devicetree/bindings/dma/dma-common.yaml +++ b/Documentation/devicetree/bindings/dma/dma-common.yaml @@ -25,11 +25,18 @@ properties: Used to provide DMA controller specific information. dma-channel-mask: - $ref: /schemas/types.yaml#definitions/uint32 description: Bitmask of available DMA channels in ascending order that are not reserved by firmware and are available to the kernel. i.e. first channel corresponds to LSB. + The first item in the array is for channels 0-31, the second is for + channels 32-63, etc. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 1 + # Should be enough + maxItems: 255 dma-channels: $ref: /schemas/types.yaml#definitions/uint32 From patchwork Thu Sep 26 11:19:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 174455 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1908032ill; Thu, 26 Sep 2019 04:19:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxVZXd8aivfn4YooU4EimXA79gE+VzgWT3TGxhdQ7Tma6neQAUcNFfBBv7T5UgglybO7tRD X-Received: by 2002:a50:a557:: with SMTP id z23mr2852346edb.99.1569496767857; Thu, 26 Sep 2019 04:19:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569496767; cv=none; d=google.com; s=arc-20160816; b=zTDVgrP6g+5bqn8fxwdzMaN2YMhB5s1JupwZ0B6qCTAqWQppFGBHiM2w9Ne5D5szdJ d8NZjQNENTVlGtI5SZ9fWbH8SPA9og9sJDUUO6ctqgaQLAKPFrT88sSX6A79YGCVIUQU ZWs1NvuXk0KmDv8VbTnKOa02NKkGler7tML7QDq6Yrp07DBK0bTvhweU//3YdAHBcA8j 909LYLcisy9FT6Mj3AtNYQvxMwhc4GFSSAW1gT8CrpbwtU0mqEKmyted1VDiaOKtBGQU GaeMuP5iF2upuBoNIFOVDeU6L9i95hK4PcWhXEEwUYsMzTQ7TpYmTCYHbTpwFfpiEBWN YpVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Os/g4h37INHFj009+Nb83YilihmshiNyFyAPP5WINzY=; b=z+4warWRx2N947FdNy6MWxvQ2mBDLwyWBNR6miWVgKQx4quyU32Pc6hUXDb3jXh6by pJE0Kq1pbxKf9+V6QCovhRY1r6GpnWBarsJsyaCkRVsE8LR0KTb6V6j27+uTW8eTN+XZ 5UPevXwqIB7d+eZO260h1X8TuLINPnzxjYe50HSI/cB9mQZhzZbC53ZO9VpLfUCLgBXa aVwEneJ8V4gIDho1yx4ohu1ANcyjd/n73d7O73HFgZC/YW8RanPWXfWixdmhjo78Qioz G8ynmfzKAO6/Z3Ek9kt15gpMIAxtCTpava+LmC2Rrkv5ARqmfVlPAQbmRj8fc8PsDnm9 N76Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LIpbrj4+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j11si1236572edj.43.2019.09.26.04.19.27; Thu, 26 Sep 2019 04:19:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LIpbrj4+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726446AbfIZLTX (ORCPT + 26 others); Thu, 26 Sep 2019 07:19:23 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:48894 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726393AbfIZLTW (ORCPT ); Thu, 26 Sep 2019 07:19:22 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8QBJHP2022830; Thu, 26 Sep 2019 06:19:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569496757; bh=Os/g4h37INHFj009+Nb83YilihmshiNyFyAPP5WINzY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LIpbrj4+UXDaUeHOqsFfQsn7slxWprVyMuUEs/N0QfHZtdpJKio9GL2SOp1U9BByR lmBXfSe9zmo4Mh7Wq2UF9pAjcUUXvSF9OgihgHczj2VsKWw8vv4xCXU7iSm0Cxa4Cd SDiyjwNG/yjX6jbatu5rW3bC/+iY+xHqf9JYmk0w= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x8QBJHfL078251 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 26 Sep 2019 06:19:17 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 26 Sep 2019 06:19:17 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 26 Sep 2019 06:19:09 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8QBJAdt013885; Thu, 26 Sep 2019 06:19:15 -0500 From: Peter Ujfalusi To: , CC: , , , Subject: [PATCH v3 2/3] dt-bindings: dma: ti-edma: Document dma-channel-mask for EDMA Date: Thu, 26 Sep 2019 14:19:53 +0300 Message-ID: <20190926111954.9184-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190926111954.9184-1-peter.ujfalusi@ti.com> References: <20190926111954.9184-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Similarly to paRAM slots, channels can be used by other cores. The common dma-channel-mask property can be used for specifying the available channels. Signed-off-by: Peter Ujfalusi --- Documentation/devicetree/bindings/dma/ti-edma.txt | 8 ++++++++ 1 file changed, 8 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 4bbc94d829c8..014187088020 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -42,6 +42,11 @@ Optional properties: - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by the driver, they are allocated to be used by for example the DSP. See example. +- dma-channel-mask: Mask of usable channels. + Single uint32 for EDMA with 32 channels, array of two uint32 for + EDMA with 64 channels. See example and + Documentation/devicetree/bindings/dma/dma-common.yaml + ------------------------------------------------------------------------------ eDMA3 Transfer Controller @@ -91,6 +96,9 @@ edma: edma@49000000 { ti,edma-memcpy-channels = <20 21>; /* The following PaRAM slots are reserved: 35-44 and 100-109 */ ti,edma-reserved-slot-ranges = <35 10>, <100 10>; + /* The following channels are reserved: 35-44 */ + dma-channel-mask = <0xffffffff>, /* Channel 0-31 */ + <0xffffe007>; /* Channel 32-63 */ }; edma_tptc0: tptc@49800000 { From patchwork Thu Sep 26 11:19:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 174457 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp1908097ill; Thu, 26 Sep 2019 04:19:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqw3+Ni0G4yv0vdgXbIvLJhi7GtLH6OLDpT7vjGBMGe07wYWeuBLrsQr2CGyo035SrCCjDZ4 X-Received: by 2002:a50:fa83:: with SMTP id w3mr2932873edr.262.1569496770947; Thu, 26 Sep 2019 04:19:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569496770; cv=none; d=google.com; s=arc-20160816; b=g+Z4H7QDiQRg/0J9yhoQeNlo/Rsml4FDCxXNeW5mlVG8g0uW5vmyi5tqBq4rDJjEUS bNP93y/KjMORB2akvtdsqAKWWXdcubL/dpC8PHrvlYL5FiT5brIohYN3L77/7o9QasI6 uBL8MnVHdQDn2G2nceLM8/kkr/QZ/s/DXxLhSS33MIy7I3ccCvQ6qO84j4DkhOJrXQH4 d+XBfh0Fjc6vCiN0tdXXezOoeIwHPVxvdgU6xk3d/BCX4IR6GekvAzEje0M8kdB1NhOS iw5Fz/yWUSy74/LyrsbIpJ4Rj1eaFbcHoZkFfFCC/8/V3/Emx17BI1gItBzsYsGwhoZZ heDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Xv9IdSYQH2Wyjdje4PEB2rgCyL+w8guQKyTJ3UYqNXA=; b=0OykAcRwFyg/sWX6oK7mDDxX3PXhaaTE1g7eza+9J0lCBOKC6OtjOndT+AzcviL26i Y0+jPPW2FMClDMhCrJjWZYSDhnM+o2CG4428MxZKDMAytb8cT/WVkLqXP0lepBjsusjP jWRN1UE8L3ZwDvtZcxqzocirn4VVo1+Q0gzassXnZaQXh7zIIXZsj4uGbbxrQVXPjxd1 96kAOlzzhsJdW+Me8hte9uMrKKzVdwTgB6L/3lJjiKfxmJYJ0DTmr0fU5NlmBf+gXeFL Y1+6AfWdzPtUn32YZh4NKKVLmYa3MDtLCt8OZ18bfwgZMBJdYkAHj51fsDmvZC45HqfR fFKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=SrfXk6WH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Handle the generic dma-channel-mask property to mark channels in a bitmap which can not be used by Linux and convert the legacy rsv_chans if it is provided by platform_data. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/edma.c | 59 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 53 insertions(+), 6 deletions(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index ba7c4f07fcd6..03c9c6296006 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -260,6 +260,13 @@ struct edma_cc { */ unsigned long *slot_inuse; + /* + * For tracking reserved channels used by DSP. + * If the bit is cleared, the channel is allocated to be used by DSP + * and Linux must not touch it. + */ + unsigned long *channels_mask; + struct dma_device dma_slave; struct dma_device *dma_memcpy; struct edma_chan *slave_chans; @@ -716,6 +723,12 @@ static int edma_alloc_channel(struct edma_chan *echan, struct edma_cc *ecc = echan->ecc; int channel = EDMA_CHAN_SLOT(echan->ch_num); + if (!test_bit(echan->ch_num, ecc->channels_mask)) { + dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n", + echan->ch_num); + return -EINVAL; + } + /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel), EDMA_CHANNEL_BIT(channel)); @@ -2250,7 +2263,7 @@ static int edma_probe(struct platform_device *pdev) struct edma_soc_info *info = pdev->dev.platform_data; s8 (*queue_priority_mapping)[2]; int i, off; - const s16 (*rsv_slots)[2]; + const s16 (*reserved)[2]; const s16 (*xbar_chans)[2]; int irq; char *irq_name; @@ -2331,15 +2344,32 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slot_inuse) return -ENOMEM; + ecc->channels_mask = devm_kcalloc(dev, + BITS_TO_LONGS(ecc->num_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->channels_mask) + return -ENOMEM; + + /* Mark all channels available initially */ + bitmap_fill(ecc->channels_mask, ecc->num_channels); + ecc->default_queue = info->default_queue; if (info->rsv) { /* Set the reserved slots in inuse list */ - rsv_slots = info->rsv->rsv_slots; - if (rsv_slots) { - for (i = 0; rsv_slots[i][0] != -1; i++) - bitmap_set(ecc->slot_inuse, rsv_slots[i][0], - rsv_slots[i][1]); + reserved = info->rsv->rsv_slots; + if (reserved) { + for (i = 0; reserved[i][0] != -1; i++) + bitmap_set(ecc->slot_inuse, reserved[i][0], + reserved[i][1]); + } + + /* Clear channels not usable for Linux */ + reserved = info->rsv->rsv_chans; + if (reserved) { + for (i = 0; reserved[i][0] != -1; i++) + bitmap_clear(ecc->channels_mask, reserved[i][0], + reserved[i][1]); } } @@ -2399,6 +2429,7 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->legacy_mode) { int lowest_priority = 0; + unsigned int array_max; struct of_phandle_args tc_args; ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, @@ -2420,6 +2451,18 @@ static int edma_probe(struct platform_device *pdev) info->default_queue = i; } } + + /* See if we have optional dma-channel-mask array */ + array_max = DIV_ROUND_UP(ecc->num_channels, BITS_PER_TYPE(u32)); + ret = of_property_read_variable_u32_array(node, + "dma-channel-mask", + (u32 *)ecc->channels_mask, + 1, array_max); + if (ret > 0 && ret != array_max) + dev_warn(dev, "dma-channel-mask is not complete.\n"); + else if (ret == -EOVERFLOW || ret == -ENODATA) + dev_warn(dev, + "dma-channel-mask is out of range or empty\n"); } /* Event queue priority mapping */ @@ -2437,6 +2480,10 @@ static int edma_probe(struct platform_device *pdev) edma_dma_init(ecc, legacy_mode); for (i = 0; i < ecc->num_channels; i++) { + /* Do not touch reserved channels */ + if (!test_bit(i, ecc->channels_mask)) + continue; + /* Assign all channels to the default queue */ edma_assign_channel_eventq(&ecc->slave_chans[i], info->default_queue);