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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id l3-20020a17090ac58300b0029b2e00359esm681947pjt.36.2024.03.01.12.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 12:41:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 1/6] target/arm: Support 32-byte alignment in pow2_align Date: Fri, 1 Mar 2024 10:41:05 -1000 Message-Id: <20240301204110.656742-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301204110.656742-1-richard.henderson@linaro.org> References: <20240301204110.656742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we have removed TARGET_PAGE_BITS_MIN-6 from TLB_FLAGS_MASK, we can test for 32-byte alignment. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index f947c62c6b..c8a2470675 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -900,13 +900,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) MemOp pow2_align(unsigned i) { static const MemOp mop_align[] = { - 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, - /* - * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such - * that 256-bit alignment (MO_ALIGN_32) cannot be supported: - * see get_alignment_bits(). Enforce only 128-bit alignment for now. - */ - MO_ALIGN_16 + 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, MO_ALIGN_32 }; g_assert(i < ARRAY_SIZE(mop_align)); return mop_align[i]; From patchwork Fri Mar 1 20:41:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 777066 Delivered-To: patch@linaro.org Received: by 2002:adf:e94d:0:b0:33d:f458:43ce with SMTP id m13csp1555169wrn; Fri, 1 Mar 2024 12:42:16 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUq6HCiAsIa4aV4C8szh7w7Y4hdTTt4GZdeY+0w3ZrUjLAnUE6HH/uIwFaEr709XiJdzlOQJbZ3+UuR+/yzeF0t X-Google-Smtp-Source: AGHT+IEaL3WL97PZRKAD1vsLw9FL8jITN1bPoAhLNuReaOLOVAWgwp1Xzsvo6jALpvlzvXbNTdPK X-Received: by 2002:a37:e209:0:b0:787:bb69:bfcf with SMTP id g9-20020a37e209000000b00787bb69bfcfmr4243848qki.12.1709325735894; Fri, 01 Mar 2024 12:42:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1709325735; cv=none; d=google.com; s=arc-20160816; b=Bn2Xfq9PhBa3dTgjkBgaiyiFTsUSGSU2gH+CVTnIOReZy9dG0jGEn6BnXzjeWgxc4m Vq8kssCIJIS5FFMJV4YVtFDjbIa4rJqmVaQoDhCR6F9DVFOCMz4/a6ssyaqq4XRVlh6x IgXrHs+Tx4oDCBNy9uk2yTVrGh1FMTzaLCutw+oEgijfrBhGOr/b85E667qeA4O6iohe ckJUQegxPt/EBsFQuiYe8JouKLWKTWCIWn1+XxawUcgEG6Hsz8ITVDTkUqqPZKqHbD+m +zRUHdiKwItfo9bNWuaoniQfSmI3GJ6I1hfHkc0cqiqoHAfvLlKRrJZRq3vICJ4Z+R0a TMEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uSxGM8jSCUAKauTODiPxOuZGF0sA3+vBxABkPlr2Gc8=; fh=OZQBfL75rC14cCDy3q+1fYHCs9KjWAQ7ZJ3hTfS+5lQ=; b=b9/04pjQWMaTyjytTOQ2dG3kWZlIe6v+0wsPStWQutc2Vr8T2iFYUKouFg+VNBOoc2 E+ErNgms+eu9gafnLbqttTjLMo5BKRIVJThKDUXCOcQ4wl6PSe16zZo3R9+SKYoFTm6U 4jXVVRZR34GnJO4djyvG0UW7tMx/fSCWBRmcX06JdW0EOx5h9pBc5q3lFL84uysORLzE 78BHyxpqYnanMYrojj2CH5qDJeLuxade0kQZJu/WWbgfw/rrydc9jr728jaFWYjEizau eoeGqzhjHlYUXL5JLrJWbdUh0TcngCbI3ZG6dyBkmmnfY7li4HgvTvOGRNhvzP6+uSdG BN9Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D1BRQr5+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id l3-20020a17090ac58300b0029b2e00359esm681947pjt.36.2024.03.01.12.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 12:41:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 2/6] exec/memattrs: Remove target_tlb_bit* Date: Fri, 1 Mar 2024 10:41:06 -1000 Message-Id: <20240301204110.656742-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301204110.656742-1-richard.henderson@linaro.org> References: <20240301204110.656742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These fields are no longer used since 937f224559. Target specific extensions to the page tables should be done with TARGET_PAGE_ENTRY_EXTRA. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d04170aa27..afa885f983 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -54,16 +54,6 @@ typedef struct MemTxAttrs { unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; - /* - * The following are target-specific page-table bits. These are not - * related to actual memory transactions at all. However, this structure - * is part of the tlb_fill interface, cached in the cputlb structure, - * and has unused bits. These fields will be read by target-specific - * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. - */ - unsigned int target_tlb_bit0 : 1; - unsigned int target_tlb_bit1 : 1; - unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, From patchwork Fri Mar 1 20:41:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 777069 Delivered-To: patch@linaro.org Received: by 2002:adf:e94d:0:b0:33d:f458:43ce with SMTP id m13csp1555342wrn; Fri, 1 Mar 2024 12:42:51 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXGc/E9Xg8aQn3THDV7dnlFNwPcxuhn6wHBdtiRQpDHeFWw1uvndD3EufimiPs7/JD9KvJLymHfuIxmJrFh6Hr1 X-Google-Smtp-Source: AGHT+IEs0nnwG3TTD6cadTr9wOewPzdOfe/trr8vp0i8ukfo49sg0ypckwaXl3dbjLm6Uoc2CtPa X-Received: by 2002:a05:6808:1408:b0:3c0:3d0c:edc9 with SMTP id w8-20020a056808140800b003c03d0cedc9mr3142161oiv.5.1709325771417; Fri, 01 Mar 2024 12:42:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1709325771; cv=none; d=google.com; s=arc-20160816; b=qXg2ZD9buIgrZgPFJ3zF/fLXkrUHvCp4YwwUQdjNrhuDBzTgNnUw8hZsYXXRnoV2nz OiIMs1gsuVDmgbQZnmFr0YwI+hIjoNGcPqW5pUK5MrEpcq2Cc79OROAcYVAENqvJ6RKV a7dopXfmiBgrAup5goZ2zhOaxBDfEHHL45A4arqZXLECD6xjG97sFKu5dj2tfu5QhRPK N2tHrlNdopKUignfQKq30fbBDPuVCXUU7NpbKcFNKN99b9kncdXNYJPE+OYJKVMnHIis JtdJnK8eGi23Off0plOm0EW0UCPwxzRKZS39979TrvOek3IYP4Ou7W4DxICZU+eyj3yu 0+WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GuRyEJUy3EeC0acSqgIfQ+cNnDkZek7t4EbMZ1kuVCY=; fh=OZQBfL75rC14cCDy3q+1fYHCs9KjWAQ7ZJ3hTfS+5lQ=; b=ETcfjeqN4gmHtmwNn7jxGW3MOXEc2YlsfADGQwKBMKzzMfnhN/A1DEyNJj31qaVIQI vrsaFclQ713q6CBEKKlejpe+gtpWsrywyPVk52fsA5a7ynNbWB/kGSRnvJlknbqiP+Na 9HiU43Te/bWzfe0N2Gm996btvQGnggCo+PIAi0cfXp7LfSlPfL4MQXkI4/JUoTNUW7vr JzBE65EqI3NBxPGDa48XudSOl7AI8VGm263eel8oxHZFgj0UuCTqa8bO7XsZSb0k7niG gDbRkQkA4hX7XSabW0+Zjn+dOI4N9X3uGYxKGfPergDznxQ4Ii1A8LbNJKSVfMzJfK5j xylw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RwKdvFaq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id l3-20020a17090ac58300b0029b2e00359esm681947pjt.36.2024.03.01.12.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 12:41:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 3/6] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull Date: Fri, 1 Mar 2024 10:41:07 -1000 Message-Id: <20240301204110.656742-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301204110.656742-1-richard.henderson@linaro.org> References: <20240301204110.656742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 2 -- include/hw/core/cpu.h | 3 +++ accel/tcg/cputlb.c | 5 +---- target/sparc/mmu_helper.c | 2 +- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index afa885f983..14cdd8d582 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -52,8 +52,6 @@ typedef struct MemTxAttrs { unsigned int memory:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; - /* Invert endianness for this page */ - unsigned int byte_swap:1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index af1a29526d..4c2fddc85b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -230,6 +230,9 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + /* Additional tlb flags requested by tlb_fill. */ + uint8_t tlb_fill_flags; + /* * Additional tlb flags for use by the slow path. If non-zero, * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 047cd2cc0a..72d6a09616 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1145,14 +1145,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=%x idx=%d\n", addr, full->phys_addr, prot, mmu_idx); - read_flags = 0; + read_flags = full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |= TLB_INVALID_MASK; } - if (full->attrs.byte_swap) { - read_flags |= TLB_BSWAP; - } is_ram = memory_region_is_ram(section->mr); is_romd = memory_region_is_romd(section->mr); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 5170a668bb..e7b1997d54 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -580,7 +580,7 @@ static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full, int do_fault = 0; if (TTE_IS_IE(env->dtlb[i].tte)) { - full->attrs.byte_swap = true; + full->tlb_fill_flags |= TLB_BSWAP; } /* access ok? */ From patchwork Fri Mar 1 20:41:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 777071 Delivered-To: patch@linaro.org Received: by 2002:adf:e94d:0:b0:33d:f458:43ce with SMTP id m13csp1555416wrn; Fri, 1 Mar 2024 12:43:08 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXNk2zT8R6x9v47VeNUHP15wQ+98fq8jgbg7x7d/1mzniaqRiO/qd/2kYMCOnoJxU5jc1s8HiBpCm7Og+Qc+HYq X-Google-Smtp-Source: AGHT+IENIYmZgVT9bRS764//wxeO/jJJxKpF5A1QHnoVUw0tjD7Fcs4nCow1raz5e4BnONx5lHCk X-Received: by 2002:a05:6870:8094:b0:21a:6818:8da7 with SMTP id q20-20020a056870809400b0021a68188da7mr3130432oab.17.1709325788550; Fri, 01 Mar 2024 12:43:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1709325788; cv=none; d=google.com; s=arc-20160816; b=eP8CCIAoZHhDv9IPvBs7QWW3xeIYLQhmpgY7KHXw5zsm9ioCvlQWvvm+5qUH1WEEUi DPR0DICDLXNpalCNBatcC5pum3I2G4bvfhpe0Hy/dvXA8NIMjFy5dwX+rCczGyP+95AT 1yXrUzXK02lUTX1g2lywnwPRxcLar5IGoqX7cPOJmelXMZg6f191W8Oy8bQtiMMm8y5F AC7xo8CQRxNqvCbdnp4sfnHvcWQh8IOgDXbTJ/pS6U9HQMNqm4I/49r/m5ZDyGb+ytMa CW1FzIWkSzXfyi5yIGBLZ1+WkPAPxJ5LVTdStjw8kYIQNTTjZfJ7cEwLcQ+540GHGiIs 9h2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ODF936SZPk4uxaAkeX8YtobtmAxstAcsRTqY9d2kdho=; fh=OZQBfL75rC14cCDy3q+1fYHCs9KjWAQ7ZJ3hTfS+5lQ=; b=FMRfH8Geb7BMqtUd6gc8Y7I2AP0Y829cvrs6YQgjL06D3D0OjnE0nP8t1Aex+QPtLB MzIWxfolOlR0uFPpsvJdURKTmZZdJMeFYZd5gZkLvJ8VYgKLywnGEH2kiD3qSsL0ZWXV T1RgUt85SlqgTBwWTI4XCMKunEnVvBwATAux9B+sWdH8O4MkJ+YZbF18YLHYavmY81+u AvbQOhTg/WcAToEGJmjivWnE5jUnXb1Im/9MMlynKpaOiAUuxjw6pmQXoxCSBV/LueTS 3Dr/xZtOQItK66J6ZFfqzMxK3SjpMp8HYkzJXMW5QNsLlgXL2CZw5UU/rlL6caqOzFGf sNlw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R223uc9M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id l3-20020a17090ac58300b0029b2e00359esm681947pjt.36.2024.03.01.12.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 12:41:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 4/6] accel/tcg: Add TLB_CHECK_ALIGNED Date: Fri, 1 Mar 2024 10:41:08 -1000 Message-Id: <20240301204110.656742-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301204110.656742-1-richard.henderson@linaro.org> References: <20240301204110.656742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This creates a per-page method for checking of alignment. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 +++- accel/tcg/cputlb.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index bc05dce7ab..1a6510fd3b 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -357,8 +357,10 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) #define TLB_BSWAP (1 << 0) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << 1) +/* Set if TLB entry requires aligned accesses. */ +#define TLB_CHECK_ALIGNED (1 << 2) -#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 72d6a09616..f1e4c23535 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1453,9 +1453,8 @@ static int probe_access_internal(CPUState *cpu, vaddr addr, flags |= full->slow_flags[access_type]; /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ - if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY)) - || - (access_type != MMU_INST_FETCH && force_mmio)) { + if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGNED)) + || (access_type != MMU_INST_FETCH && force_mmio)) { *phost = NULL; return TLB_MMIO; } @@ -1836,6 +1835,31 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, tcg_debug_assert((flags & TLB_BSWAP) == 0); } + /* + * This alignment check differs from the one above, in that this is + * based on the atomicity of the operation. The intended use case is + * the ARM memory type field of each PTE, where access to pages with + * Device memory type require alignment. + */ + if (unlikely(flags & TLB_CHECK_ALIGNED)) { + MemOp size = l->memop & MO_SIZE; + + switch (l->memop & MO_ATOM_MASK) { + case MO_ATOM_NONE: + size = MO_8; + break; + case MO_ATOM_IFALIGN_PAIR: + case MO_ATOM_WITHIN16_PAIR: + size = size ? size - 1 : 0; + break; + default: + break; + } + if (addr & ((1 << size) - 1)) { + cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); + } + } + return crosspage; } From patchwork Fri Mar 1 20:41:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 777072 Delivered-To: patch@linaro.org Received: by 2002:adf:e94d:0:b0:33d:f458:43ce with SMTP id m13csp1555482wrn; Fri, 1 Mar 2024 12:43:20 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCVVsLzLdOcbXvNs1oZaxvaz1hG2aW3G/WLqtLRIV+Xwhn+t9PnYKpMm2bWrpLqm3nzZXV/5knRt1nCNSnzqyBFF X-Google-Smtp-Source: AGHT+IGbFekDBndUWetbaLolEQo+XxFrzDCd2rOk2HoNrBCZ2xdZueHkg402+HteYCrHxfXP4bSX X-Received: by 2002:ad4:4815:0:b0:690:182c:d398 with SMTP id qd21-20020ad44815000000b00690182cd398mr3419846qvb.0.1709325800249; Fri, 01 Mar 2024 12:43:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1709325800; cv=none; d=google.com; s=arc-20160816; b=txdqE+c71K0gBJ4wQBZy2gKegASmeiGHQ1Gv3FYlfVENdd5RblmA6AHR2m/ksLm3aS 4UPsFqfaBmB6bMlW4yBKQwDg/Gs+QAt/wOiQ2RqWUYkO6raomp+mxdTJGOG7zRIAoa2a JrH+XD9/6IrJvb5S9UVIXZlYPq4dWcD/dB3AvCS1j7ONhpmpBV1Q4iiuxdWGQmk6+01s 8zksvIEHBpl7jRtb2ImoDMwJm1qjaEgEOfs+MYHYoP2XRA+fcdaxDFsm4fTwVUkCJ2rr tf/igisf5Oi4sodZRDZeVr4jM11+hinN9NONggxlZd6TV6OkXZgvpET/Cqvy99tg7ijd ggBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9Kev1JbGsH8SPuVfwyjwv2zI6xwvmoOl1CfSqGhDN5g=; fh=X6WeDsGLRGf50j0Uf29WVs/9IAwsZZZhxH8c0rS+hfU=; b=dzeuZJ5y1zNLtEBDhs/ageM58MZ18E5uEH6aUNzrszA3IDlvoKdSM4P/GEoP8jbuBL oRt8lMg11FevSlBLcbZXoJzXG7BHnAwoSG/GImzZsDHnN3nGSOPSIxkqwnoJyk5BDqbc W2ubv4gZ83hhOrD9tQUrW0w7CyiXXNtekZhNpfeVsYw728VILDP0Xu6ovzU8Vki5wTG7 8oMDuU8aEWqAzt/1fdKpwL2AcLCSyXMUalWvoofBBkDgWsHJbj76iiX/MKxhUW3GYFO5 qm24AVrlZTKfdnbp0V01X+YF1O6s6PrAL70eBZpo8OS1KpaeIqDnh8iQzsXyCjGSTZs+ sitQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AD0X293s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id l3-20020a17090ac58300b0029b2e00359esm681947pjt.36.2024.03.01.12.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 12:41:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Idan Horowitz Subject: [PATCH v3 5/6] target/arm: Do memory type alignment check when translation disabled Date: Fri, 1 Mar 2024 10:41:09 -1000 Message-Id: <20240301204110.656742-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301204110.656742-1-richard.henderson@linaro.org> References: <20240301204110.656742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If translation is disabled, the default memory type is Device, which requires alignment checking. This is more optimally done early via the MemOp given to the TCG memory operation. Reviewed-by: Philippe Mathieu-Daudé Reported-by: Idan Horowitz Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204 Signed-off-by: Richard Henderson --- target/arm/tcg/hflags.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 8e5d35d922..5da1b0fc1d 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -26,6 +26,35 @@ static inline bool fgt_svc(CPUARMState *env, int el) FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); } +/* Return true if memory alignment should be enforced. */ +static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + /* Check the alignment enable bit. */ + if (sctlr & SCTLR_A) { + return true; + } + + /* + * If translation is disabled, then the default memory type is + * Device(-nGnRnE) instead of Normal, which requires that alignment + * be enforced. Since this affects all ram, it is most efficient + * to handle this during translation. + */ + if (sctlr & SCTLR_M) { + /* Translation enabled: memory type in PTE via MAIR_ELx. */ + return false; + } + if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { + /* Stage 2 translation enabled: memory type in PTE. */ + return false; + } + return true; +#endif +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -121,8 +150,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, { CPUARMTBFlags flags = {}; int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); - if (arm_sctlr(env, el) & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } @@ -223,7 +253,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sctlr = regime_sctlr(env, stage1); - if (sctlr & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } From patchwork Fri Mar 1 20:41:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 777067 Delivered-To: patch@linaro.org Received: by 2002:adf:e94d:0:b0:33d:f458:43ce with SMTP id m13csp1555187wrn; Fri, 1 Mar 2024 12:42:18 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUZQgZuRAFdA085aoV3GjKaHjmqq7FLWHziFQZVLYwbgNMAhbYn4TJQNL7It4tJSOD2NbDecbCUilJd9vgVCQ+o X-Google-Smtp-Source: AGHT+IG9djV1PTtKa9E7ziZjs4CzAyPitmYKNV/SP3a2o5e0TmI+XQgqYaehoA52+zWFG/1Qvo0r X-Received: by 2002:ac8:4e47:0:b0:42e:d423:c073 with SMTP id e7-20020ac84e47000000b0042ed423c073mr1327800qtw.29.1709325738404; Fri, 01 Mar 2024 12:42:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1709325738; cv=none; d=google.com; s=arc-20160816; b=gVTjJyFuIMZfaKXADOgZdCSnQXkXtkD5l81EOsi01lTwIh2YLLqSnWHvoHCJ6IU3+r Jq/sSq6gez2AZyyI8v0tohul0zUx8roNhQuTRoPd6bJ9Lf3rMBiaqOlXChUlWXS0EBLW yVWnYMxHZa3DxXTt1jdZ+oWBKCO1p0FISWSC9OnF9QDAmHc9/cGYGpuqetB8ca5DYAZy ekNCwscqhDE15vmEF/4Kdqm1oBRUrTzskkaKEOhdJlxubLLVy2bVC1hLfz0u6H8xHd1i aZGckJKWJqiFlN4pgHyf0oWn3OK+ddfv1sL4UvneYeZmS1QXK/vCrU6ynqg46HiuMl78 Rd+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TxofW6bNC8fGOO2v/wfoJQ/7dw6hp4z2OqJzWySAJjk=; fh=9Ev+QBUhk6P6vR3LT1wYeDLexozsz44nqjfoyPajZCc=; b=jFSQVGqJoN/i6gBgaMGEw9HfPTo+ludeYUMts6GUM/PL9IAliWQ2MXilwQytIGACXZ E+OKN3qq0hn/BOmZCYvSW1spZiXdrgrFMXXzS/fCysWniQXQfGQPIXIgsxs13JnKE78c uJwmijzeokG8SxxkpXsnswf9zSlc5Og0/O/xZKuykT4KjVmpyEIfINCBpAtspZfPTzr0 9K9JKjtlVXXbgSdxPre8bl+bTaq8kkkeLUCOjrrHMgPqIU3c7vP0OIJ2MBmjPSh+1bHE xoyPivWHmK2PD0WWst+sdW6THz0uNOh889bqECiqwo3I+FgHfZRkTQiLC+1pA/QK374s 1RUA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CdcT8qGo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id l3-20020a17090ac58300b0029b2e00359esm681947pjt.36.2024.03.01.12.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 12:41:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 6/6] target/arm: Do memory type alignment check when translation enabled Date: Fri, 1 Mar 2024 10:41:10 -1000 Message-Id: <20240301204110.656742-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301204110.656742-1-richard.henderson@linaro.org> References: <20240301204110.656742-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If translation is enabled, and the PTE memory type is Device, enable checking alignment via TLB_CHECK_ALIGNMENT. While the check is done later than it should be per the ARM, it's better than not performing the check at all. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ba1a27ca2b..fc2f226411 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -471,6 +471,16 @@ static bool granule_protection_check(CPUARMState *env, uint64_t paddress, return false; } +static bool S1_attrs_are_device(uint8_t attrs) +{ + /* + * This slightly under-decodes the MAIR_ELx field: + * 0b0000dd01 is Device with FEAT_XS, otherwise UNPREDICTABLE; + * 0b0000dd1x is UNPREDICTABLE. + */ + return (attrs & 0xf0) == 0; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -1684,6 +1694,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, bool aarch64 = arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; ARMSecuritySpace out_space; + bool device; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -2106,6 +2117,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, if (regime_is_stage2(mmu_idx)) { result->cacheattrs.is_s2_format = true; result->cacheattrs.attrs = extract32(attrs, 2, 4); + /* + * Security state does not really affect HCR_EL2.FWB; + * we only need to filter FWB for aa32 or other FEAT. + */ + device = S2_attrs_are_device(arm_hcr_el2_eff(env), + result->cacheattrs.attrs); } else { /* Index into MAIR registers for cache attributes */ uint8_t attrindx = extract32(attrs, 2, 3); @@ -2118,6 +2135,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ } + device = S1_attrs_are_device(result->cacheattrs.attrs); + } + + /* + * Enable alignment checks on Device memory. + * + * Per R_XCHFJ, this check is mis-ordered, in that this alignment check + * should have priority 30, while the permission check should be next at + * priority 31 and stage2 translation faults come after that. + * Due to the way the TCG softmmu TLB operates, we will have implicitly + * done the permission check and the stage2 lookup in finding the TLB + * entry, so the alignment check cannot be done sooner. + */ + if (device) { + result->f.tlb_fill_flags |= TLB_CHECK_ALIGNED; } /*