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([223.178.211.249]) by smtp.gmail.com with ESMTPSA id o13-20020a170902d4cd00b001dd8ce888aasm2877895plg.74.2024.03.11.04.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Mar 2024 04:10:54 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v2 1/5] qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default Date: Mon, 11 Mar 2024 16:40:22 +0530 Message-Id: <20240311111027.44577-2-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240311111027.44577-1-sumit.garg@linaro.org> References: <20240311111027.44577-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is loaded as a first stage bootloader. It leads to secondary CPUs bringup failure and later causing the Linux kernel to freeze. So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's actually required. Fixes: 059d526af312 ("mach-snapdragon: generalise board support") Signed-off-by: Sumit Garg Reviewed-by: Caleb Connolly --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 65fa7ba4ce7..27f3d9a43e1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1090,7 +1090,7 @@ config ARCH_SNAPDRAGON select BOARD_LATE_INIT select OF_BOARD select SAVE_PREV_BL_FDT_ADDR - select LINUX_KERNEL_IMAGE_HEADER + select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK imply CMD_DM config ARCH_SOCFPGA From patchwork Mon Mar 11 11:10:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 779411 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp1466887wrt; Mon, 11 Mar 2024 04:11:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXhsaoN5qyAp8jNLo/8l9Hbe0nZf4/0aYZlNzqKdCCD/64u0m4/cyq9aYJ5xp5WH2CkD9oj1rE1NSdB2SvlSmkT X-Google-Smtp-Source: AGHT+IFCIkRe7oU2IYW1eYAvPW/NCJ8oq738F7YDegtI8sSo04ZQkqHfn9xeiMXu/utNLTnxxE8y X-Received: by 2002:a5d:4a05:0:b0:33e:774f:e3ca with SMTP id m5-20020a5d4a05000000b0033e774fe3camr4054558wrq.64.1710155481005; Mon, 11 Mar 2024 04:11:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710155480; cv=none; d=google.com; s=arc-20160816; b=LgLX4ooB5tkkjIOaikbNIEje2aSw857yRyQtBYGHddcw6Scp4fW+o3nSB14tpmnlcI +t3izUfZatWJiXLMMYIfZcYJ3p6Eof9CKXcvK53T7IaX7TD8R10YyAmV9E2qYgErPNDP BvW0/xMexQM8gXPq81OEjAV/6YYab0wTdJh35n9SMO079prwanqCyttXW3KcFJomygew yolIZOhoKuwNL/HvKhJsRCKINmOJNCcDri/XuCTfTDLtb29R9Ii+PwOJW6pqbv0sw+fD U95+rzxXH/kJhtJbTopplIlVnemMv8JL40vHHBqgRFVahArL5PdQug/NmNoIx0nU5K8V WEnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fwXGse+l23PHgPgrHvODcCdkPJjhR7UyLi5HUZ/u6KQ=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=A6pnSa7CXIqHxjnScP1Mdi+i3upNEPHILMXf1KsysHKdEiQxY6rjI3u1JvsMzLlFG4 rlpduOIaTZiHMIS+OHIhWk12+Y5tKGkz1bShd8OyF5zoWgApnaIMI32qr4aLGtkmL2pr C2g62V6WVCPj5Na/zMSVclIQm6EkGfZK3H5PH+BPoC+JK+88iP6HVoeJh9bBe53xrfj2 Z0qQstXgQi02ba2/u9dyZ/wpzvjfdE3UBKId8EC2D94XQLvd1B+6c/vQQZMSjmUuj7aT Rqm8S01PWvZP8LQlo7EaSxdQXF+UnIThSR/N30jOfjrrgy40s5vOViDB3y0Gn80tQdkJ z0eA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Tus1yyjJ; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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([223.178.211.249]) by smtp.gmail.com with ESMTPSA id o13-20020a170902d4cd00b001dd8ce888aasm2877895plg.74.2024.03.11.04.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Mar 2024 04:10:59 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v2 2/5] apq8016: Add support for UART1 clocks and pinmux Date: Mon, 11 Mar 2024 16:40:23 +0530 Message-Id: <20240311111027.44577-3-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240311111027.44577-1-sumit.garg@linaro.org> References: <20240311111027.44577-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Signed-off-by: Sumit Garg --- drivers/clk/qcom/clock-apq8016.c | 50 +++++++++++++++++++++----- drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 + drivers/serial/serial_msm.c | 6 ++-- 3 files changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index e6647f7c41d..a620a10a520 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -43,6 +43,14 @@ #define BLSP1_UART2_APPS_N (0x3040) #define BLSP1_UART2_APPS_D (0x3044) +#define BLSP1_UART1_BCR (0x2038) +#define BLSP1_UART1_APPS_CBCR (0x203C) +#define BLSP1_UART1_APPS_CMD_RCGR (0x2044) +#define BLSP1_UART1_APPS_CFG_RCGR (0x2048) +#define BLSP1_UART1_APPS_M (0x204C) +#define BLSP1_UART1_APPS_N (0x2050) +#define BLSP1_UART1_APPS_D (0x2054) + /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) @@ -77,7 +85,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = { }; /* SDHCI */ -static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) +static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) { int div = 15; /* 100MHz default */ @@ -94,6 +102,33 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) return rate; } +static const struct bcr_regs uart1_regs = { + .cfg_rcgr = BLSP1_UART1_APPS_CFG_RCGR, + .cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR, + .M = BLSP1_UART1_APPS_M, + .N = BLSP1_UART1_APPS_N, + .D = BLSP1_UART1_APPS_D, +}; + +/* UART: 115200 */ +static int apq8016_clk_init_uart1(phys_addr_t base) +{ + /* Enable AHB clock */ + clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); + + /* 7372800 uart block clock @ GPLL0 */ + clk_rcg_set_rate_mnd(base, &uart1_regs, 1, 144, 15625, + CFG_CLK_SRC_GPLL0, 16); + + /* Vote for gpll0 clock */ + clk_enable_gpll0(base, &gpll0_vote_clk); + + /* Enable core clk */ + clk_enable_cbc(base + BLSP1_UART1_APPS_CBCR); + + return 0; +} + static const struct bcr_regs uart2_regs = { .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR, .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR, @@ -103,7 +138,7 @@ static const struct bcr_regs uart2_regs = { }; /* UART: 115200 */ -int apq8016_clk_init_uart(phys_addr_t base) +int apq8016_clk_init_uart2(phys_addr_t base) { /* Enable AHB clock */ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); @@ -127,14 +162,13 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_SDCC1_APPS_CLK: /* SDC1 */ - return clk_init_sdc(priv, 0, rate); - break; + return apq8016_clk_init_sdc(priv, 0, rate); case GCC_SDCC2_APPS_CLK: /* SDC2 */ - return clk_init_sdc(priv, 1, rate); - break; + return apq8016_clk_init_sdc(priv, 1, rate); case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return apq8016_clk_init_uart(priv->base); - break; + return apq8016_clk_init_uart2(priv->base); + case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */ + return apq8016_clk_init_uart1(priv->base); default: return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index db0e2124684..cb0e2227079 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = { }; static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart1", 2}, {"blsp_uart2", 2}, }; diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index ac4280c6c4c..eaf024a55b0 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -248,12 +248,14 @@ static struct msm_serial_data init_serial_data = { #include /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ -//int apq8016_clk_init_uart(phys_addr_t gcc_base); +//int apq8016_clk_init_uart1(phys_addr_t gcc_base); +//int apq8016_clk_init_uart2(phys_addr_t gcc_base); static inline void _debug_uart_init(void) { /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ - //apq8016_clk_init_uart(0x1800000); + //apq8016_clk_init_uart1(0x1800000); + //apq8016_clk_init_uart2(0x1800000); uart_dm_init(&init_serial_data); } From patchwork Mon Mar 11 11:10:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 779412 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp1466961wrt; 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([223.178.211.249]) by smtp.gmail.com with ESMTPSA id o13-20020a170902d4cd00b001dd8ce888aasm2877895plg.74.2024.03.11.04.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Mar 2024 04:11:04 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v2 3/5] serial_msm: Enable RS232 flow control Date: Mon, 11 Mar 2024 16:40:24 +0530 Message-Id: <20240311111027.44577-4-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240311111027.44577-1-sumit.garg@linaro.org> References: <20240311111027.44577-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present. Signed-off-by: Sumit Garg Reviewed-by: Caleb Connolly --- drivers/serial/serial_msm.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index eaf024a55b0..7b2a3fdb2c1 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -53,10 +53,11 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC -#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 -#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 -#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define MSM_UART_MR1_RX_RDY_CTL BIT(7) DECLARE_GLOBAL_DATA_PTR; @@ -182,7 +183,9 @@ static void uart_dm_init(struct msm_serial_data *priv) mdelay(5); writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); - writel(0x0, priv->base + UARTDM_MR1); + + /* Enable RS232 flow control to support RS232 db9 connector */ + writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1); writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); From patchwork Mon Mar 11 11:10:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 779413 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp1467060wrt; Mon, 11 Mar 2024 04:11:43 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUWUgFh4BdKKdIJ3Cv/hcDkd5vr4Exl5RE8kosUHlUnd1za3JQ6Vt+YVaavQirRMHao2t2MS/ws+Zo6FO4rQy5d X-Google-Smtp-Source: AGHT+IEsQInTaRN6gXwNHqjI8jYjPfK7OS5x9J3ZKNGRjS6IGQYO+SWh84tT5SyyzFzCrWPK/CS6 X-Received: by 2002:a19:700e:0:b0:512:eee2:d8d0 with SMTP id h14-20020a19700e000000b00512eee2d8d0mr3873730lfc.59.1710155503549; Mon, 11 Mar 2024 04:11:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710155503; cv=none; d=google.com; s=arc-20160816; b=B01e8f1AWv1fFkzG26OWNM8DPMbxM1AT8Z/OTrfxyZ7Z+/WJyyyxpY1tfcpi88F4AL bAw0uda0RFQ9FWCcmGiuf9OXQTu70+4ae/PS97j67yvRGGgW3uweX1Kjv7fdTcrfJ0XM V8defoycBTYnvMULPA/7zG+HKXPIiozIvbnixSMUx5DDsgI0xTVKnh7GyayxvREmcZUa J/Ix5MeIDPYoNM7WJ8nz5kH7uputHiTOHuIPVzs8fQGb9RlRELo6z/DbUuH6eSvbOdGn TkyFu/Vm0nA7Nix1Wwevz9eD40mZTyRZMjjASnfF0yp91H2rmWdUHPKGdX4cblwDTm9+ taxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=seKN50Etda75U/FJdHIIcqKTArRh0uu3C+V9JBF2uLU=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=qfuXyCvmUh5y16PAKseKuZi9N74eEDhs3pWj7RRiGrC+s1lgQmNrGhgrP/FFAXRuf+ uqjRjiVZU1+sqr7mkHHuMIXFdJ385DtfESrd8BF7uJfYnbij/pzk0lnm+Yklgj5ni7tt eaL3eZ2xCk9KeoD5goYOCH3T9AGJMzUMoa9ttAYdO7c9i5Vgv0gy1sk1uPRN1/SghaWI u2DGfx1mtUutVUCgA/DUHX6STmvj9pslAMYt8fNhk0INSFYFi5Rry4G/UDNpR79O+Wfx I1yOQym0P4401pL67sRCVRoa+cbQkVqZOOB0FNfdiBMl5dhl39Hwydd8AoV8ohwifrXu fZ1g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vAzKQQt3; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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([223.178.211.249]) by smtp.gmail.com with ESMTPSA id o13-20020a170902d4cd00b001dd8ce888aasm2877895plg.74.2024.03.11.04.11.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Mar 2024 04:11:09 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v2 4/5] pinctrl: qcom: Add support for driving GPIO pins output Date: Mon, 11 Mar 2024 16:40:25 +0530 Message-Id: <20240311111027.44577-5-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240311111027.44577-1-sumit.garg@linaro.org> References: <20240311111027.44577-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for driving the GPIO pins as output low or high. Signed-off-by: Sumit Garg --- drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 + drivers/pinctrl/qcom/pinctrl-qcom.c | 26 +++++++++++++++++++++----- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index cb0e2227079..04b501c563d 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = { }; static const struct pinctrl_function msm_pinctrl_functions[] = { + {"gpio", 0}, {"blsp_uart1", 2}, {"blsp_uart2", 2}, }; diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index ee0624df296..932be7c4840 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -29,15 +29,25 @@ struct msm_pinctrl_priv { #define GPIO_CONFIG_REG(priv, x) \ (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x)) -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9) +#define GPIO_IN_OUT_REG(priv, x) \ + (GPIO_CONFIG_REG(priv, x) + 0x4) + +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_OUTPUT_MASK BIT(1) +#define TLMM_GPIO_OE_MASK BIT(9) + +/* GPIO_IN_OUT register shifts. */ +#define GPIO_IN 0 +#define GPIO_OUT 1 static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, }; static int msm_get_functions_count(struct udevice *dev) @@ -89,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0; clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, + TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, priv->data->get_function_mux(func_selector) << 2); return 0; } @@ -117,6 +127,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_GPIO_PULL_MASK, argument); break; + case PIN_CONFIG_OUTPUT: + writel(argument << GPIO_OUT, + priv->base + GPIO_IN_OUT_REG(priv, pin_selector)); + setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), + TLMM_GPIO_OE_MASK); + break; default: return 0; } From patchwork Mon Mar 11 11:10:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 779414 Delivered-To: patch@linaro.org Received: by 2002:a5d:604e:0:b0:33e:7753:30bd with SMTP id j14csp1467131wrt; Mon, 11 Mar 2024 04:11:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVcNdiZhDcVi3ttNWS/zHRjp2mMK0p+gzFLUiLAKMQjMBlZR8gxrDipsDhcay6j145ty6IZAj3E5gnS6kSEbrdA X-Google-Smtp-Source: AGHT+IFTvLdbo6RPnC6hds0JO5D6yKqPsUs2UKT8cw7OVG9YQbTGjGDQoDgjmXJqUu2OaIqujuv4 X-Received: by 2002:a05:600c:5190:b0:413:27d0:44ff with SMTP id fa16-20020a05600c519000b0041327d044ffmr2307471wmb.8.1710155514225; Mon, 11 Mar 2024 04:11:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1710155514; cv=none; d=google.com; s=arc-20160816; b=FiAWbiHBdA1G13Yer+PNjiDBD2KnFkvuwZC17Z7u/fRywzMV8ocq0YK8wxnd3B0Ba8 qXWIUGW8Xxq/0H8BwiEQzs92g9OX/rlaHIppRTZVgW4MuUumGi3gZ//FZZmPCBwhV5A/ 2zsHpat+/ON2+yV0H8eAxDPrSOya3K29TtZgY2tva/fYpqWfBokNezS915jH93wvZ6+s 6VLjwq4nRQaRi1TR2BhXHmvDuZ24ftU7RZvu11JpgI2tL0s+bNVsXLseo3aq9Ci7pp6c lQxomrhuWFWqxN3yp4YlR4uDtJjHavU6xJBL6Del29gFJkbe7QnQAungbg/py4xB+Qyb IlwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OEWLc6mLFoiSUhzbGt+0UkUaS2XPrJ2LAOzkTRtTRow=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=fIA5wNE9qPt2Mz7pKSjtO5TWCXwN7e9eheaKgr8LnbSHl0h4aNh0TfbMpqM0bNYbrV vel/6DATHorpJyhjTnHDzPO4UiGQtyAtoMXFPIRDsZJcOMJiK77kliSWkWvy4Ugn0M/j 7mY0Lq8yFqF6OtFxWx6BxL1vKXGcNwe3V4VzEQ59mhE6PNZktCNtfTHDpAa4HLJWAr3U S5//K4W3uucfbEr5orw3kP8yCrHVYwBnza2lPTcNCmpg5OvTnnbTfQpwyPLhXA33o9Jn el8vgBvl6aK/7V6VeNDJ5/ArMVaw+2BN7LIib31gXCvU1mxzOpGpfeNvzQp7gII18oSn VtiA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JXMqDPnv; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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([223.178.211.249]) by smtp.gmail.com with ESMTPSA id o13-20020a170902d4cd00b001dd8ce888aasm2877895plg.74.2024.03.11.04.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Mar 2024 04:11:14 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v2 5/5] board: add support for Schneider HMIBSC board Date: Mon, 11 Mar 2024 16:40:26 +0530 Message-Id: <20240311111027.44577-6-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240311111027.44577-1-sumit.garg@linaro.org> References: <20240311111027.44577-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Support for Schneider Electric HMIBSC. Features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI Features enabled in U-Boot: - RAUC updates - Environment protection - USB based ethernet adaptors Signed-off-by: Sumit Garg --- arch/arm/dts/apq8016-hmibsc.dts | 496 +++++++++++++++++++++++++++++ board/schneider/hmibsc/MAINTAINERS | 6 + configs/hmibsc_defconfig | 87 +++++ doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst | 45 +++ doc/board/schneider/index.rst | 9 + include/configs/hmibsc.h | 57 ++++ 7 files changed, 701 insertions(+) create mode 100644 arch/arm/dts/apq8016-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h diff --git a/arch/arm/dts/apq8016-hmibsc.dts b/arch/arm/dts/apq8016-hmibsc.dts new file mode 100644 index 00000000000..490ab5fd2fa --- /dev/null +++ b/arch/arm/dts/apq8016-hmibsc.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. + */ + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + model = "Schneider Electric HMIBSC Board"; + compatible = "qcom,apq8016-hmibsc", "qcom,apq8016"; + + aliases { + serial0 = &blsp_uart1; + serial1 = &blsp_uart2; + usid0 = &pm8916_0; + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + i2c4 = &blsp_i2c3; + spi0 = &blsp_spi5; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory@80000000 { + reg = <0 0x80000000 0 0x40000000>; + }; + + reserved-memory { + ramoops@bff00000 { + compatible = "ramoops"; + reg = <0x0 0xbff00000 0x0 0x100000>; + + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + }; + }; + + usb2513 { + compatible = "smsc,usb3503"; + reset-gpios = <&pm8916_gpios 1 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&msm_key_volp_n_default>; + + button { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pm8916_mpps_leds>; + + compatible = "gpio-leds"; + + led@5 { + label = "apq8016-hmibsc:green:wlan"; + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led@6 { + label = "apq8016-hmibsc:yellow:bt"; + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; +}; + +&blsp_i2c4 { + status = "okay"; + label = "I2C2"; + + adv_bridge: bridge@39 { + status = "okay"; + + compatible = "adi,adv7533"; + reg = <0x39>; + + interrupt-parent = <&tlmm>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; + + adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + + pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&pm8916_l6>; + a2vdd-supply = <&pm8916_l6>; + dvdd-supply = <&pm8916_l6>; + pvdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp_i2c6 { + status = "okay"; + label = "I2C1"; + + rtc1: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + eeprom1: 24c256@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&blsp_i2c3 { + status = "okay"; + label = "I2C4"; + + eeprom: 24c32@50 { + compatible = "onsemi,24c32"; + reg = <0x50>; + }; +}; + +&blsp_spi5 { + status = "okay"; + label = "SPI0"; + cs-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + + tpm@0 { + compatible = "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <500000>; + }; +}; + +&blsp_uart1 { + status = "okay"; + label = "UART0"; +}; + +&blsp_uart2 { + status = "okay"; + label = "UART1"; +}; + +&lpass { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; +}; + +&pm8916_0 { + pon@800 { + pwrkey { + status = "okay"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + }; + }; +}; + +&pm8916_codec { + status = "okay"; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; +}; + +&sound { + status = "okay"; + + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; + pinctrl-names = "default", "sleep"; + model = "DB410c"; + audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + + quaternary-dai-link { + link-name = "ADV7533"; + cpu { + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; + + primary-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; + }; + }; + + tertiary-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; + }; + }; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; + + pinctrl-names = "default", "device"; + pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; + pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + status = "okay"; + firmware-name = "qcom/apq8016/wcnss.mbn"; +}; + +&wcnss_ctrl { + firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; +}; + +/* Enable CoreSight */ +&cti0 { status = "okay"; }; +&cti1 { status = "okay"; }; +&cti12 { status = "okay"; }; +&cti13 { status = "okay"; }; +&cti14 { status = "okay"; }; +&cti15 { status = "okay"; }; +&debug0 { status = "okay"; }; +&debug1 { status = "okay"; }; +&debug2 { status = "okay"; }; +&debug3 { status = "okay"; }; +&etf { status = "okay"; }; +&etm0 { status = "okay"; }; +&etm1 { status = "okay"; }; +&etm2 { status = "okay"; }; +&etm3 { status = "okay"; }; +&etr { status = "okay"; }; +&funnel0 { status = "okay"; }; +&funnel1 { status = "okay"; }; +&replicator { status = "okay"; }; +&stm { status = "okay"; }; +&tpiu { status = "okay"; }; + +/* + * 2mA drive strength is not enough when connecting multiple + * I2C devices with different pull up resistors. + */ + +&blsp_i2c4_default { + drive-strength = <16>; +}; + +&blsp_i2c6_default { + drive-strength = <16>; +}; + +&tlmm { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_rs232_high &gpio_rs232_low>; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; + + adv7533_int_active: adv533-int-active-state { + pins = "gpio31"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + adv7533_int_suspend: adv7533-int-suspend-state { + pins = "gpio31"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + adv7533_switch_active: adv7533-switch-active-state { + pins = "gpio32"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + adv7533_switch_suspend: adv7533-switch-suspend-state { + pins = "gpio32"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + msm_key_volp_n_default: msm-key-volp-n-default-state { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; + + gpio_rs232_high: gpio_rs232_high { + bootph-all; + pins = "gpio99"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + + gpio_rs232_low: gpio_rs232_low { + bootph-all; + pins = "gpio100"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&pm8916_gpios { + gpio-line-names = + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM"; + + usb_hub_reset_pm: usb-hub-reset-pm-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + + input-disable; + output-high; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + + output-low; + }; + + usb_sw_sel_pm: usb-sw-sel-pm-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + + power-source = ; + input-disable; + output-high; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + + power-source = ; + input-disable; + output-low; + }; +}; + +&pm8916_mpps { + gpio-line-names = + "WLAN_LED_CTRL", + "BT_LED_CTRL"; + + pm8916_mpps_leds: pm8916-mpps-state { + pins = "mpp2", "mpp3"; + function = "digital"; + + output-low; + }; +}; + +&blsp_uart1_default { + bootph-all; +}; diff --git a/board/schneider/hmibsc/MAINTAINERS b/board/schneider/hmibsc/MAINTAINERS new file mode 100644 index 00000000000..0f31bbda966 --- /dev/null +++ b/board/schneider/hmibsc/MAINTAINERS @@ -0,0 +1,6 @@ +HMIBSC BOARD +M: Sumit Garg +S: Maintained +F: board/schneider/hmibsc/ +F: include/configs/hmibsc.h +F: configs/hmibsc_defconfig diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig new file mode 100644 index 00000000000..02b9615114b --- /dev/null +++ b/configs/hmibsc_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="hmibsc" +CONFIG_COUNTER_FREQUENCY=19000000 +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_TEXT_BASE=0x8f600000 +CONFIG_SYS_MALLOC_LEN=0x802000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DEFAULT_DEVICE_TREE="apq8016-hmibsc" +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IDENT_STRING="\nSchneider Electric-HMIBSC" +CONFIG_SYS_LOAD_ADDR=0x80080000 +CONFIG_REMAKE_ELF=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=2048 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="hmibsc => " +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_ENV_EXISTS=y +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON_QCOM_PMIC=y +CONFIG_CLK=y +CONFIG_CLK_QCOM_APQ8016=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_MSM_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_QCOM_APQ8016=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_QCOM=y +CONFIG_MSM_SERIAL=y +CONFIG_SPMI_MSM=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_PHYLIB=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d +CONFIG_CI_UDC=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 62357c99388..bc6c27a8457 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc renesas/index rockchip/index samsung/index + schneider/index sielaff/index siemens/index sifive/index diff --git a/doc/board/schneider/hmibsc.rst b/doc/board/schneider/hmibsc.rst new file mode 100644 index 00000000000..f09fb5af1b3 --- /dev/null +++ b/doc/board/schneider/hmibsc.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Sumit Garg + +HMIBSC +====== + +The HMIBSC is an IIoT Edge Box Core board based on the Qualcomm APQ8016E SoC. +More information can be found on the `SE product page`_. + +U-Boot can be used as a replacement for Qualcomm's original Android bootloader +(a fork of Little Kernel/LK). Like LK, it is installed directly into the ``aboot`` +partition. Note that the U-Boot port used to be loaded as an Android boot image +through LK. This is no longer the case, now U-Boot can replace LK entirely. + +.. _SE product page: https://www.se.com/us/en/product/HMIBSCEA53D1L0T/iiot-edge-box-core-harmony-ipc-emmc-dc-linux-tpm/ + +Build steps +----------- + +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``hmibsc``:: + + $ export CROSS_COMPILE= + $ make hmibsc_defconfig + $ make + +This will build ``u-boot.elf`` in the configured output directory. + +Installation +------------ + +Although the HMIBSC does not have secure boot set up by default, the firmware +still expects firmware ELF images to be "signed". The signature does not provide +any security in this case, but it provides the firmware with some required +metadata. + +To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_:: + + $ ./qtestsign.py aboot u-boot.elf + +Then install the resulting ``u-boot-test-signed.mbn`` to the ``aboot`` partition +on your device, e.g. with ``fastboot flash aboot u-boot-test-signed.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign diff --git a/doc/board/schneider/index.rst b/doc/board/schneider/index.rst new file mode 100644 index 00000000000..55792ed3100 --- /dev/null +++ b/doc/board/schneider/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Schneider Electric +================== + +.. toctree:: + :maxdepth: 2 + + hmibsc diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h new file mode 100644 index 00000000000..66dfa549ce1 --- /dev/null +++ b/include/configs/hmibsc.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for HMIBSC + * + * (C) Copyright 2024 Sumit Garg + */ + +#ifndef __CONFIGS_HMIBSC_H +#define __CONFIGS_HMIBSC_H + +/* PHY needs a longer aneg time */ +#define PHY_ANEG_TIMEOUT 8000 + +#define HMIBSC_BOOTCOMMAND \ + "setenv devtype mmc; setenv devnum 0; " \ + "test -n \"${BOOT_ORDER}\" || setenv BOOT_ORDER \"A B\"; " \ + "test -n \"${BOOT_A_LEFT}\" || setenv BOOT_A_LEFT 3; " \ + "test -n \"${BOOT_B_LEFT}\" || setenv BOOT_B_LEFT 3; " \ + "setenv raucslot; " \ + "for BOOT_SLOT in \"${BOOT_ORDER}\"; do " \ + " if test \"x${raucslot}\" != \"x\"; then " \ + " echo \"skip remaining slots...\"; " \ + " elif test \"x${BOOT_SLOT}\" = \"xA\"; then " \ + " if test ${BOOT_A_LEFT} -gt 0; then " \ + " setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1; " \ + " echo \"Found valid RAUC slot A\"; " \ + " setenv raucslot \"rauc.slot=A\"; " \ + " setenv raucpart A; setenv distro_bootpart 6;" \ + " fi; " \ + " elif test \"x${BOOT_SLOT}\" = \"xB\"; then " \ + " if test ${BOOT_B_LEFT} -gt 0; then " \ + " setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1; " \ + " echo \"Found valid RAUC slot B\"; " \ + " setenv raucslot \"rauc.slot=B\"; " \ + " setenv raucpart B; setenv distro_bootpart 7;" \ + " fi; " \ + " fi; " \ + "done; " \ + "if test -n \"${raucslot}\"; then " \ + " setenv bootargs console=ttyMSM1 root=PARTLABEL=rootfs_${raucpart} rw rootwait ${raucslot}; " \ + " saveenv; " \ + "else " \ + " echo \"No valid RAUC slot found. Resetting tries to 3\"; " \ + " setenv BOOT_A_LEFT 3; " \ + " setenv BOOT_B_LEFT 3; " \ + " saveenv; " \ + " reset; " \ + "fi; " \ + "load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} /boot/fitImage && bootm" + +#define CFG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x90000000\0" \ + "bootcmd=" HMIBSC_BOOTCOMMAND "\0" + +#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" + +#endif