From patchwork Mon Sep 30 14:40:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 174762 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7239613ill; Mon, 30 Sep 2019 07:57:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqwygPK4fjkvG8ZatkSj/YC15M5WtQ51jR84vBTifVN1PaI/xjua/xEgIXPCVAVEEe2CZP+M X-Received: by 2002:a50:b6a8:: with SMTP id d37mr20173518ede.63.1569855442473; Mon, 30 Sep 2019 07:57:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569855442; cv=none; d=google.com; s=arc-20160816; b=N4s01Yq4g56FPx9CppaviOFHINGOZJ0uBZF9XEqRPBZp7Lv1KCCaqBlDVHQJAk3kB7 4qZsa5hhGy5AGZAW0Ss09DBdsn0Uvcj0A69HkRgzQNWfqpChDh693omafqq9oDRWIC3y FsEYuS+fLtB/D8dlFt0wEM1283XzgAAXXuLLhhNLHt70unyk0vvyQDy5UmM2I4WbO2Kf f3N64l9g3rapKcyr46CeJ6Huty6UBwZ2hOX1PDZPXZg08kFb0DczONbKWTQ4XGqlSRWd zgCJB49vAz6J7ZGFId8021NTBWcLQ2xrAxS3sMnlBFcZrxXLQvo4VsZx6KDGFE1ZA9if 32EQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=LPWMSCF2aq+6NsEB8lFtH/77Rmrs+TCau9cdC6TMWpw=; b=MQ2E6QNACHQgrV6TX/SnYW2koIEROMz6+rZxhCFbTZXYEJudVix5BRlMPCODV9Hnqm s8lv+FJ6byK3snCK99UJXnmXb9lktENyzPXSp0P1TS3UrOOjAdMI9r7AFTB1gvdVnxf4 OH3uKfq0g6wMuCwGuOs5rZxghtm7LFGm56enicV3+RHzUCfpibOkRbUUgMVccpS1vGfW yzokJHC3MAILPDAjF9rjjE/QydH8UB+2JSSaD4rdXfRUXkzZw35N+vViUDfpvKou30Qu C1B18uw5IjRTaSxF6mGOBnZGQY0ujbbTKeq3gu73oU9oZFvDn4qFtocf68g9j4FMYFdV yXDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id ot41si7281022ejb.215.2019.09.30.07.57.22; Mon, 30 Sep 2019 07:57:22 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E49A71BEC0; Mon, 30 Sep 2019 16:56:38 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id E975F1BE8F for ; Mon, 30 Sep 2019 16:56:23 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id C303320049E; Mon, 30 Sep 2019 16:56:23 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6565C2000A7; Mon, 30 Sep 2019 16:56:21 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 5FB9040318; Mon, 30 Sep 2019 22:56:18 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: aconole@redhat.com, anoobj@marvell.com, Hemant Agrawal Date: Mon, 30 Sep 2019 20:10:46 +0530 Message-Id: <20190930144104.12742-7-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930144104.12742-1-akhil.goyal@nxp.com> References: <20190930115237.5073-1-akhil.goyal@nxp.com> <20190930144104.12742-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v3 06/24] crypto/dpaa2_sec: support CAAM HW era 10 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Adding minimal support for CAAM HW era 10 (used in LX2) Primary changes are: 1. increased shard desc length form 6 bit to 7 bits 2. support for several PDCP operations as PROTOCOL offload. Signed-off-by: Hemant Agrawal Acked-by: Akhil Goyal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 5 ++++ drivers/crypto/dpaa2_sec/hw/desc.h | 5 ++++ drivers/crypto/dpaa2_sec/hw/desc/pdcp.h | 21 ++++++++++----- .../dpaa2_sec/hw/rta/fifo_load_store_cmd.h | 9 ++++--- drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h | 21 ++++++++++++--- drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h | 3 +-- drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h | 5 ++-- drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h | 10 ++++--- drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h | 12 +++++---- drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h | 8 +++--- drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h | 10 +++---- .../crypto/dpaa2_sec/hw/rta/operation_cmd.h | 6 ++--- .../crypto/dpaa2_sec/hw/rta/protocol_cmd.h | 9 +++++-- .../dpaa2_sec/hw/rta/sec_run_time_asm.h | 27 +++++++++++++------ .../dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h | 7 +++-- drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h | 6 ++--- 16 files changed, 110 insertions(+), 54 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 7946abf40..9108b3c43 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -3450,6 +3450,11 @@ cryptodev_dpaa2_sec_probe(struct rte_dpaa2_driver *dpaa2_drv __rte_unused, /* init user callbacks */ TAILQ_INIT(&(cryptodev->link_intr_cbs)); + if (dpaa2_svr_family == SVR_LX2160A) + rta_set_sec_era(RTA_SEC_ERA_10); + + DPAA2_SEC_INFO("2-SEC ERA is %d", rta_get_sec_era()); + /* Invoke PMD device initialization function */ retval = dpaa2_sec_dev_init(cryptodev); if (retval == 0) diff --git a/drivers/crypto/dpaa2_sec/hw/desc.h b/drivers/crypto/dpaa2_sec/hw/desc.h index e12c3db2f..667da971b 100644 --- a/drivers/crypto/dpaa2_sec/hw/desc.h +++ b/drivers/crypto/dpaa2_sec/hw/desc.h @@ -18,6 +18,8 @@ #include "hw/compat.h" #endif +extern enum rta_sec_era rta_sec_era; + /* Max size of any SEC descriptor in 32-bit words, inclusive of header */ #define MAX_CAAM_DESCSIZE 64 @@ -113,9 +115,12 @@ /* Start Index or SharedDesc Length */ #define HDR_START_IDX_SHIFT 16 #define HDR_START_IDX_MASK (0x3f << HDR_START_IDX_SHIFT) +#define HDR_START_IDX_MASK_ERA10 (0x7f << HDR_START_IDX_SHIFT) /* If shared descriptor header, 6-bit length */ #define HDR_DESCLEN_SHR_MASK 0x3f +/* If shared descriptor header, 7-bit length era10 onwards*/ +#define HDR_DESCLEN_SHR_MASK_ERA10 0x7f /* If non-shared header, 7-bit length */ #define HDR_DESCLEN_MASK 0x7f diff --git a/drivers/crypto/dpaa2_sec/hw/desc/pdcp.h b/drivers/crypto/dpaa2_sec/hw/desc/pdcp.h index 9a73105ac..4bf1d69f9 100644 --- a/drivers/crypto/dpaa2_sec/hw/desc/pdcp.h +++ b/drivers/crypto/dpaa2_sec/hw/desc/pdcp.h @@ -776,7 +776,8 @@ pdcp_insert_cplane_enc_only_op(struct program *p, KEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key, cipherdata->keylen, INLINE_KEY(cipherdata)); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { if (sn_size == PDCP_SN_SIZE_5) PROTOCOL(p, dir, OP_PCLID_LTE_PDCP_CTRL_MIXED, (uint16_t)cipherdata->algtype << 8); @@ -962,7 +963,8 @@ pdcp_insert_cplane_snow_aes_op(struct program *p, REFERENCE(jump_back_to_sd_cmd); REFERENCE(move_mac_i_to_desc_buf); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { KEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key, cipherdata->keylen, INLINE_KEY(cipherdata)); KEY(p, KEY2, authdata->key_enc_flags, authdata->key, @@ -1286,7 +1288,8 @@ pdcp_insert_cplane_aes_snow_op(struct program *p, KEY(p, KEY2, authdata->key_enc_flags, authdata->key, authdata->keylen, INLINE_KEY(authdata)); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; if (sn_size == PDCP_SN_SIZE_5) @@ -1430,7 +1433,8 @@ pdcp_insert_cplane_snow_zuc_op(struct program *p, SET_LABEL(p, keyjump); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; if (sn_size == PDCP_SN_SIZE_5) @@ -1548,7 +1552,8 @@ pdcp_insert_cplane_aes_zuc_op(struct program *p, KEY(p, KEY2, authdata->key_enc_flags, authdata->key, authdata->keylen, INLINE_KEY(authdata)); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; if (sn_size == PDCP_SN_SIZE_5) @@ -1671,7 +1676,8 @@ pdcp_insert_cplane_zuc_snow_op(struct program *p, KEY(p, KEY2, authdata->key_enc_flags, authdata->key, authdata->keylen, INLINE_KEY(authdata)); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; if (sn_size == PDCP_SN_SIZE_5) @@ -1806,7 +1812,8 @@ pdcp_insert_cplane_zuc_aes_op(struct program *p, return -ENOTSUP; } - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; KEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/fifo_load_store_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/fifo_load_store_cmd.h index 8c807aaa2..287e09cd7 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/fifo_load_store_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/fifo_load_store_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_FIFO_LOAD_STORE_CMD_H__ @@ -42,7 +41,8 @@ static const uint32_t fifo_load_table[][2] = { * supported. */ static const unsigned int fifo_load_table_sz[] = {22, 22, 23, 23, - 23, 23, 23, 23}; + 23, 23, 23, 23, + 23, 23}; static inline int rta_fifo_load(struct program *program, uint32_t src, @@ -201,7 +201,8 @@ static const uint32_t fifo_store_table[][2] = { * supported. */ static const unsigned int fifo_store_table_sz[] = {21, 21, 21, 21, - 22, 22, 22, 23}; + 22, 22, 22, 23, + 23, 23}; static inline int rta_fifo_store(struct program *program, uint32_t src, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h index 0c7ea9387..45aefa04c 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_HEADER_CMD_H__ @@ -19,6 +18,8 @@ static const uint32_t job_header_flags[] = { DNR | TD | MTD | SHR | REO | RSMS | EXT, DNR | TD | MTD | SHR | REO | RSMS | EXT, DNR | TD | MTD | SHR | REO | RSMS | EXT, + DNR | TD | MTD | SHR | REO | EXT, + DNR | TD | MTD | SHR | REO | EXT, DNR | TD | MTD | SHR | REO | EXT }; @@ -31,6 +32,8 @@ static const uint32_t shr_header_flags[] = { DNR | SC | PD | CIF | RIF, DNR | SC | PD | CIF | RIF, DNR | SC | PD | CIF | RIF, + DNR | SC | PD | CIF | RIF, + DNR | SC | PD | CIF | RIF, DNR | SC | PD | CIF | RIF }; @@ -72,7 +75,12 @@ rta_shr_header(struct program *program, } opcode |= HDR_ONE; - opcode |= (start_idx << HDR_START_IDX_SHIFT) & HDR_START_IDX_MASK; + if (rta_sec_era >= RTA_SEC_ERA_10) + opcode |= (start_idx << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK_ERA10; + else + opcode |= (start_idx << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK; if (flags & DNR) opcode |= HDR_DNR; @@ -160,7 +168,12 @@ rta_job_header(struct program *program, } opcode |= HDR_ONE; - opcode |= ((start_idx << HDR_START_IDX_SHIFT) & HDR_START_IDX_MASK); + if (rta_sec_era >= RTA_SEC_ERA_10) + opcode |= (start_idx << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK_ERA10; + else + opcode |= (start_idx << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK; if (flags & EXT) { opcode |= HDR_EXT; diff --git a/drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h index 546d22e98..18f781e37 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_JUMP_CMD_H__ diff --git a/drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h index 1ec21234a..ec3fbcaf6 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_KEY_CMD_H__ @@ -19,6 +18,8 @@ static const uint32_t key_enc_flags[] = { ENC | NWB | EKT | TK, ENC | NWB | EKT | TK, ENC | NWB | EKT | TK | PTS, + ENC | NWB | EKT | TK | PTS, + ENC | NWB | EKT | TK | PTS, ENC | NWB | EKT | TK | PTS }; diff --git a/drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h index f3b0dcfcb..38e253c22 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_LOAD_CMD_H__ @@ -19,6 +18,8 @@ static const uint32_t load_len_mask_allowed[] = { 0x000000fe, 0x000000fe, 0x000000fe, + 0x000000fe, + 0x000000fe, 0x000000fe }; @@ -30,6 +31,8 @@ static const uint32_t load_off_mask_allowed[] = { 0x000000ff, 0x000000ff, 0x000000ff, + 0x000000ff, + 0x000000ff, 0x000000ff }; @@ -137,7 +140,8 @@ static const struct load_map load_dst[] = { * Allowed LOAD destinations for each SEC Era. * Values represent the number of entries from load_dst[] that are supported. */ -static const unsigned int load_dst_sz[] = { 31, 34, 34, 40, 40, 40, 40, 40 }; +static const unsigned int load_dst_sz[] = { 31, 34, 34, 40, 40, + 40, 40, 40, 40, 40}; static inline int load_check_len_offset(int pos, uint32_t length, uint32_t offset) diff --git a/drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h index 5b28cbabb..cca70f7e0 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_MATH_CMD_H__ @@ -29,7 +28,8 @@ static const uint32_t math_op1[][2] = { * Allowed MATH op1 sources for each SEC Era. * Values represent the number of entries from math_op1[] that are supported. */ -static const unsigned int math_op1_sz[] = {10, 10, 12, 12, 12, 12, 12, 12}; +static const unsigned int math_op1_sz[] = {10, 10, 12, 12, 12, 12, + 12, 12, 12, 12}; static const uint32_t math_op2[][2] = { /*1*/ { MATH0, MATH_SRC1_REG0 }, @@ -51,7 +51,8 @@ static const uint32_t math_op2[][2] = { * Allowed MATH op2 sources for each SEC Era. * Values represent the number of entries from math_op2[] that are supported. */ -static const unsigned int math_op2_sz[] = {8, 9, 13, 13, 13, 13, 13, 13}; +static const unsigned int math_op2_sz[] = {8, 9, 13, 13, 13, 13, 13, 13, + 13, 13}; static const uint32_t math_result[][2] = { /*1*/ { MATH0, MATH_DEST_REG0 }, @@ -71,7 +72,8 @@ static const uint32_t math_result[][2] = { * Values represent the number of entries from math_result[] that are * supported. */ -static const unsigned int math_result_sz[] = {9, 9, 10, 10, 10, 10, 10, 10}; +static const unsigned int math_result_sz[] = {9, 9, 10, 10, 10, 10, 10, 10, + 10, 10}; static inline int rta_math(struct program *program, uint64_t operand1, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h index a7ff7c675..d2151c6dd 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_MOVE_CMD_H__ @@ -47,7 +46,8 @@ static const uint32_t move_src_table[][2] = { * Values represent the number of entries from move_src_table[] that are * supported. */ -static const unsigned int move_src_table_sz[] = {9, 11, 14, 14, 14, 14, 14, 14}; +static const unsigned int move_src_table_sz[] = {9, 11, 14, 14, 14, 14, 14, 14, + 14, 14}; static const uint32_t move_dst_table[][2] = { /*1*/ { CONTEXT1, MOVE_DEST_CLASS1CTX }, @@ -72,7 +72,7 @@ static const uint32_t move_dst_table[][2] = { * supported. */ static const -unsigned int move_dst_table_sz[] = {13, 14, 14, 15, 15, 15, 15, 15}; +unsigned int move_dst_table_sz[] = {13, 14, 14, 15, 15, 15, 15, 15, 15, 15}; static inline int set_move_offset(struct program *program __maybe_unused, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h index 94f775e2e..85092d961 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_NFIFO_CMD_H__ @@ -24,7 +23,7 @@ static const uint32_t nfifo_src[][2] = { * Allowed NFIFO LOAD sources for each SEC Era. * Values represent the number of entries from nfifo_src[] that are supported. */ -static const unsigned int nfifo_src_sz[] = {4, 5, 5, 5, 5, 5, 5, 7}; +static const unsigned int nfifo_src_sz[] = {4, 5, 5, 5, 5, 5, 5, 7, 7, 7}; static const uint32_t nfifo_data[][2] = { { MSG, NFIFOENTRY_DTYPE_MSG }, @@ -77,7 +76,8 @@ static const uint32_t nfifo_flags[][2] = { * Allowed NFIFO LOAD flags for each SEC Era. * Values represent the number of entries from nfifo_flags[] that are supported. */ -static const unsigned int nfifo_flags_sz[] = {12, 14, 14, 14, 14, 14, 14, 14}; +static const unsigned int nfifo_flags_sz[] = {12, 14, 14, 14, 14, 14, + 14, 14, 14, 14}; static const uint32_t nfifo_pad_flags[][2] = { { BM, NFIFOENTRY_BM }, @@ -90,7 +90,7 @@ static const uint32_t nfifo_pad_flags[][2] = { * Values represent the number of entries from nfifo_pad_flags[] that are * supported. */ -static const unsigned int nfifo_pad_flags_sz[] = {2, 2, 2, 2, 3, 3, 3, 3}; +static const unsigned int nfifo_pad_flags_sz[] = {2, 2, 2, 2, 3, 3, 3, 3, 3, 3}; static inline int rta_nfifo_load(struct program *program, uint32_t src, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/operation_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/operation_cmd.h index b85760e5b..9a1788c0f 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/operation_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/operation_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_OPERATION_CMD_H__ @@ -229,7 +228,8 @@ static const struct alg_aai_map alg_table[] = { * Allowed OPERATION algorithms for each SEC Era. * Values represent the number of entries from alg_table[] that are supported. */ -static const unsigned int alg_table_sz[] = {14, 15, 15, 15, 17, 17, 11, 17}; +static const unsigned int alg_table_sz[] = {14, 15, 15, 15, 17, 17, + 11, 17, 17, 17}; static inline int rta_operation(struct program *program, uint32_t cipher_algo, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/protocol_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/protocol_cmd.h index 82581edf5..e9f20703f 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/protocol_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/protocol_cmd.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016, 2019 NXP + * Copyright 2016,2019 NXP * */ @@ -326,6 +326,10 @@ static const uint32_t proto_blob_flags[] = { OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM, OP_PCL_BLOB_FORMAT_MASK | OP_PCL_BLOB_BLACK | OP_PCL_BLOB_TKEK | OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM, + OP_PCL_BLOB_FORMAT_MASK | OP_PCL_BLOB_BLACK | OP_PCL_BLOB_TKEK | + OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM, + OP_PCL_BLOB_FORMAT_MASK | OP_PCL_BLOB_BLACK | OP_PCL_BLOB_TKEK | + OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM, OP_PCL_BLOB_FORMAT_MASK | OP_PCL_BLOB_BLACK | OP_PCL_BLOB_TKEK | OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM }; @@ -604,7 +608,8 @@ static const struct proto_map proto_table[] = { * Allowed OPERATION protocols for each SEC Era. * Values represent the number of entries from proto_table[] that are supported. */ -static const unsigned int proto_table_sz[] = {21, 29, 29, 29, 29, 35, 37, 40}; +static const unsigned int proto_table_sz[] = {21, 29, 29, 29, 29, 35, 37, + 40, 40, 40}; static inline int rta_proto_operation(struct program *program, uint32_t optype, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/sec_run_time_asm.h b/drivers/crypto/dpaa2_sec/hw/rta/sec_run_time_asm.h index 5357187f8..d8cdebd20 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/sec_run_time_asm.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/sec_run_time_asm.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_SEC_RUN_TIME_ASM_H__ @@ -36,7 +35,9 @@ enum rta_sec_era { RTA_SEC_ERA_6, RTA_SEC_ERA_7, RTA_SEC_ERA_8, - MAX_SEC_ERA = RTA_SEC_ERA_8 + RTA_SEC_ERA_9, + RTA_SEC_ERA_10, + MAX_SEC_ERA = RTA_SEC_ERA_10 }; /** @@ -605,10 +606,14 @@ __rta_inline_data(struct program *program, uint64_t data, static inline unsigned int rta_desc_len(uint32_t *buffer) { - if ((*buffer & CMD_MASK) == CMD_DESC_HDR) + if ((*buffer & CMD_MASK) == CMD_DESC_HDR) { return *buffer & HDR_DESCLEN_MASK; - else - return *buffer & HDR_DESCLEN_SHR_MASK; + } else { + if (rta_sec_era >= RTA_SEC_ERA_10) + return *buffer & HDR_DESCLEN_SHR_MASK_ERA10; + else + return *buffer & HDR_DESCLEN_SHR_MASK; + } } static inline unsigned int @@ -701,9 +706,15 @@ rta_patch_header(struct program *program, int line, unsigned int new_ref) return -EINVAL; opcode = bswap ? swab32(program->buffer[line]) : program->buffer[line]; + if (rta_sec_era >= RTA_SEC_ERA_10) { + opcode &= (uint32_t)~HDR_START_IDX_MASK_ERA10; + opcode |= (new_ref << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK_ERA10; + } else { + opcode &= (uint32_t)~HDR_START_IDX_MASK; + opcode |= (new_ref << HDR_START_IDX_SHIFT) & HDR_START_IDX_MASK; + } - opcode &= (uint32_t)~HDR_START_IDX_MASK; - opcode |= (new_ref << HDR_START_IDX_SHIFT) & HDR_START_IDX_MASK; program->buffer[line] = bswap ? swab32(opcode) : opcode; return 0; diff --git a/drivers/crypto/dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h index ceb6a8719..5e6af0c83 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_SEQ_IN_OUT_PTR_CMD_H__ @@ -19,6 +18,8 @@ static const uint32_t seq_in_ptr_flags[] = { RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, + RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, + RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP }; @@ -31,6 +32,8 @@ static const uint32_t seq_out_ptr_flags[] = { SGF | PRE | EXT | RTO | RST | EWS, SGF | PRE | EXT | RTO | RST | EWS, SGF | PRE | EXT | RTO | RST | EWS, + SGF | PRE | EXT | RTO | RST | EWS, + SGF | PRE | EXT | RTO | RST | EWS, SGF | PRE | EXT | RTO | RST | EWS }; diff --git a/drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h index 8b58e544d..5de47d053 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_STORE_CMD_H__ @@ -56,7 +55,8 @@ static const uint32_t store_src_table[][2] = { * supported. */ static const unsigned int store_src_table_sz[] = {29, 31, 33, 33, - 33, 33, 35, 35}; + 33, 33, 35, 35, + 35, 35}; static inline int rta_store(struct program *program, uint64_t src, From patchwork Mon Sep 30 14:40:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 174763 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7241529ill; Mon, 30 Sep 2019 07:59:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqy8adKkrhtdaVzj+A/KUwTQU752TxfNSQYpp1440nzfmPCycSnMb0PcGS1LS4JWp+zsMXuv X-Received: by 2002:a17:906:d92c:: with SMTP id rn12mr19723378ejb.16.1569855553068; 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[92.243.14.124]) by mx.google.com with ESMTP id c52si7881463eda.132.2019.09.30.07.59.12; Mon, 30 Sep 2019 07:59:13 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8BEBF1BF20; Mon, 30 Sep 2019 16:57:35 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 24B881BE99 for ; Mon, 30 Sep 2019 16:56:28 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 05010200489; Mon, 30 Sep 2019 16:56:28 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 4094F2007B1; Mon, 30 Sep 2019 16:56:25 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id B091540296; Mon, 30 Sep 2019 22:56:21 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: aconole@redhat.com, anoobj@marvell.com, Hemant Agrawal , Akhil Goyal Date: Mon, 30 Sep 2019 20:10:49 +0530 Message-Id: <20190930144104.12742-10-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930144104.12742-1-akhil.goyal@nxp.com> References: <20190930115237.5073-1-akhil.goyal@nxp.com> <20190930144104.12742-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v3 09/24] crypto/dpaa2_sec: support scatter gather for proto offloads X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal This patch add support for chained input or output mbufs for PDCP and ipsec protocol offload cases. Signed-off-by: Hemant Agrawal Signed-off-by: Akhil Goyal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 134 +++++++++++++++++++- drivers/crypto/dpaa2_sec/dpaa2_sec_logs.h | 4 +- 2 files changed, 133 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 9108b3c43..b8712af24 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -65,6 +65,121 @@ static uint8_t cryptodev_driver_id; int dpaa2_logtype_sec; +static inline int +build_proto_compound_sg_fd(dpaa2_sec_session *sess, + struct rte_crypto_op *op, + struct qbman_fd *fd, uint16_t bpid) +{ + struct rte_crypto_sym_op *sym_op = op->sym; + struct ctxt_priv *priv = sess->ctxt; + struct qbman_fle *fle, *sge, *ip_fle, *op_fle; + struct sec_flow_context *flc; + struct rte_mbuf *mbuf; + uint32_t in_len = 0, out_len = 0; + + if (sym_op->m_dst) + mbuf = sym_op->m_dst; + else + mbuf = sym_op->m_src; + + /* first FLE entry used to store mbuf and session ctxt */ + fle = (struct qbman_fle *)rte_malloc(NULL, FLE_SG_MEM_SIZE, + RTE_CACHE_LINE_SIZE); + if (unlikely(!fle)) { + DPAA2_SEC_DP_ERR("Proto:SG: Memory alloc failed for SGE"); + return -1; + } + memset(fle, 0, FLE_SG_MEM_SIZE); + DPAA2_SET_FLE_ADDR(fle, (size_t)op); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); + + /* Save the shared descriptor */ + flc = &priv->flc_desc[0].flc; + + op_fle = fle + 1; + ip_fle = fle + 2; + sge = fle + 3; + + if (likely(bpid < MAX_BPID)) { + DPAA2_SET_FD_BPID(fd, bpid); + DPAA2_SET_FLE_BPID(op_fle, bpid); + DPAA2_SET_FLE_BPID(ip_fle, bpid); + } else { + DPAA2_SET_FD_IVP(fd); + DPAA2_SET_FLE_IVP(op_fle); + DPAA2_SET_FLE_IVP(ip_fle); + } + + /* Configure FD as a FRAME LIST */ + DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(op_fle)); + DPAA2_SET_FD_COMPOUND_FMT(fd); + DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc)); + + /* Configure Output FLE with Scatter/Gather Entry */ + DPAA2_SET_FLE_SG_EXT(op_fle); + DPAA2_SET_FLE_ADDR(op_fle, DPAA2_VADDR_TO_IOVA(sge)); + + /* Configure Output SGE for Encap/Decap */ + DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); + DPAA2_SET_FLE_OFFSET(sge, mbuf->data_off); + /* o/p segs */ + while (mbuf->next) { + sge->length = mbuf->data_len; + out_len += sge->length; + sge++; + mbuf = mbuf->next; + DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); + DPAA2_SET_FLE_OFFSET(sge, mbuf->data_off); + } + /* using buf_len for last buf - so that extra data can be added */ + sge->length = mbuf->buf_len - mbuf->data_off; + out_len += sge->length; + + DPAA2_SET_FLE_FIN(sge); + op_fle->length = out_len; + + sge++; + mbuf = sym_op->m_src; + + /* Configure Input FLE with Scatter/Gather Entry */ + DPAA2_SET_FLE_ADDR(ip_fle, DPAA2_VADDR_TO_IOVA(sge)); + DPAA2_SET_FLE_SG_EXT(ip_fle); + DPAA2_SET_FLE_FIN(ip_fle); + + /* Configure input SGE for Encap/Decap */ + DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); + DPAA2_SET_FLE_OFFSET(sge, mbuf->data_off); + sge->length = mbuf->data_len; + in_len += sge->length; + + mbuf = mbuf->next; + /* i/p segs */ + while (mbuf) { + sge++; + DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); + DPAA2_SET_FLE_OFFSET(sge, mbuf->data_off); + sge->length = mbuf->data_len; + in_len += sge->length; + mbuf = mbuf->next; + } + ip_fle->length = in_len; + DPAA2_SET_FLE_FIN(sge); + + /* In case of PDCP, per packet HFN is stored in + * mbuf priv after sym_op. + */ + if (sess->ctxt_type == DPAA2_SEC_PDCP && sess->pdcp.hfn_ovd) { + uint32_t hfn_ovd = *((uint8_t *)op + sess->pdcp.hfn_ovd_offset); + /*enable HFN override override */ + DPAA2_SET_FLE_INTERNAL_JD(ip_fle, hfn_ovd); + DPAA2_SET_FLE_INTERNAL_JD(op_fle, hfn_ovd); + DPAA2_SET_FD_INTERNAL_JD(fd, hfn_ovd); + } + DPAA2_SET_FD_LEN(fd, ip_fle->length); + + return 0; +} + static inline int build_proto_compound_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, @@ -87,7 +202,7 @@ build_proto_compound_fd(dpaa2_sec_session *sess, /* we are using the first FLE entry to store Mbuf */ retval = rte_mempool_get(priv->fle_pool, (void **)(&fle)); if (retval) { - DPAA2_SEC_ERR("Memory alloc failed"); + DPAA2_SEC_DP_ERR("Memory alloc failed"); return -1; } memset(fle, 0, FLE_POOL_BUF_SIZE); @@ -1170,8 +1285,10 @@ build_sec_fd(struct rte_crypto_op *op, else return -1; - /* Segmented buffer */ - if (unlikely(!rte_pktmbuf_is_contiguous(op->sym->m_src))) { + /* Any of the buffer is segmented*/ + if (!rte_pktmbuf_is_contiguous(op->sym->m_src) || + ((op->sym->m_dst != NULL) && + !rte_pktmbuf_is_contiguous(op->sym->m_dst))) { switch (sess->ctxt_type) { case DPAA2_SEC_CIPHER: ret = build_cipher_sg_fd(sess, op, fd, bpid); @@ -1185,6 +1302,10 @@ build_sec_fd(struct rte_crypto_op *op, case DPAA2_SEC_CIPHER_HASH: ret = build_authenc_sg_fd(sess, op, fd, bpid); break; + case DPAA2_SEC_IPSEC: + case DPAA2_SEC_PDCP: + ret = build_proto_compound_sg_fd(sess, op, fd, bpid); + break; case DPAA2_SEC_HASH_CIPHER: default: DPAA2_SEC_ERR("error: Unsupported session"); @@ -1372,9 +1493,14 @@ sec_fd_to_mbuf(const struct qbman_fd *fd) if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) { dpaa2_sec_session *sess = (dpaa2_sec_session *) get_sec_session_private_data(op->sym->sec_session); - if (sess->ctxt_type == DPAA2_SEC_IPSEC) { + if (sess->ctxt_type == DPAA2_SEC_IPSEC || + sess->ctxt_type == DPAA2_SEC_PDCP) { uint16_t len = DPAA2_GET_FD_LEN(fd); dst->pkt_len = len; + while (dst->next != NULL) { + len -= dst->data_len; + dst = dst->next; + } dst->data_len = len; } } diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_logs.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_logs.h index 8a9904426..c2e11f951 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_logs.h +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_logs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. - * Copyright 2016 NXP + * Copyright 2016,2019 NXP * */ @@ -37,6 +37,8 @@ extern int dpaa2_logtype_sec; DPAA2_SEC_DP_LOG(INFO, fmt, ## args) #define DPAA2_SEC_DP_WARN(fmt, args...) \ DPAA2_SEC_DP_LOG(WARNING, fmt, ## args) +#define DPAA2_SEC_DP_ERR(fmt, args...) \ + DPAA2_SEC_DP_LOG(ERR, fmt, ## args) #endif /* _DPAA2_SEC_LOGS_H_ */ From patchwork Mon Sep 30 14:40:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 174764 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7242038ill; Mon, 30 Sep 2019 07:59:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqxmcHUHhkuYz5JprO7DbD50D82zPNhZx+Nn7KauHq+5ChrajnjgkErvHZrcNVdAWlJrFibl X-Received: by 2002:a17:906:1e57:: with SMTP id i23mr19798332ejj.204.1569855583076; Mon, 30 Sep 2019 07:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569855583; cv=none; d=google.com; s=arc-20160816; b=Q3J6AuNTcNoEv4Ht7mCsCBUI06ROngLQvH1EHv/n9IWZqYYctfvN1p1Tm9XrVkuUP8 I8kR3ghDdgwYCzePKvUc5yPpcbhlF8FYlz+R+rWV3vwl1cZvqm2GUkEbNIJT3YTBX9G6 0gHsF2LBM6Qj3wP7FINqilAje9qzftHx7GjT7KlRmQK4g96OF8ckiwMYdyXAX6C51s8p dT5tKFYDpOjnlmve3eA7jm5y1vYJvGJQBl7VxEgHlSF7L37tq+S1+7G327CP4CSZYTnp g5gW+A0Xl+qu0nnQxYgqWncPq3TAvHdMoVXVQz/5YWYpSIJmurl/rthuQdEgjpPAKEl6 Hw6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=Mjjrb1cF5Gc9ks3j1wOwumZiM2DIPEtHqeEaJUZ3H0w=; b=uVZRK6S/r197gZda/Ev1eJWaRtHcB27RADPJet/5H0l0J3GQYPAIP8hVcvbGq0AmJ+ G1QR/OSf/45APGYM2DUmKbpB1ZrDHTWk4PWLqH8uuWWSjXCRdrshFaXLK6XiLIijwm10 Hu0lMQxdWPHX6HuncoTpfUVmaP4A3qUZklmYyPJT+IQ8PUuH1tKxijG9D8miVyng8dX7 /7nkIgoi70JuALJKfdwbt7GuOsulSq6AQY6GTKGhohaZ9NEv6HoANAZpnqec0Bwaoe6n g/EFLa0YrJSKh83zTYRtZ9kST8UtpApl9AQ/q4sRJ1/BSAglE2Wq/QSjvpQp9L0kxs+R nrQA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id qh16si7221856ejb.349.2019.09.30.07.59.42; Mon, 30 Sep 2019 07:59:43 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 12DA71BF33; Mon, 30 Sep 2019 16:57:45 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 4F4B21BEC3 for ; Mon, 30 Sep 2019 16:56:39 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 31427200897; Mon, 30 Sep 2019 16:56:39 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3B40920008A; Mon, 30 Sep 2019 16:56:36 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 4E93B402B7; Mon, 30 Sep 2019 22:56:32 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: aconole@redhat.com, anoobj@marvell.com, Hemant Agrawal , Vakul Garg Date: Mon, 30 Sep 2019 20:10:57 +0530 Message-Id: <20190930144104.12742-18-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930144104.12742-1-akhil.goyal@nxp.com> References: <20190930115237.5073-1-akhil.goyal@nxp.com> <20190930144104.12742-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v3 17/24] crypto/dpaa2_sec: support snow3g cipher/integrity X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Adding basic framework to use snow3g f8 and f9 based ciphering or integrity with direct crypto apis. This patch does not support any combo usages yet. Signed-off-by: Hemant Agrawal Signed-off-by: Vakul Garg Acked-by: Akhil Goyal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 310 ++++++++++++++------ drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 46 ++- drivers/crypto/dpaa2_sec/hw/desc/algo.h | 30 ++ 3 files changed, 301 insertions(+), 85 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index b020041c8..451fa91fb 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -880,11 +880,26 @@ static inline int build_auth_sg_fd( struct qbman_fle *fle, *sge, *ip_fle, *op_fle; struct sec_flow_context *flc; struct ctxt_priv *priv = sess->ctxt; + int data_len, data_offset; uint8_t *old_digest; struct rte_mbuf *mbuf; PMD_INIT_FUNC_TRACE(); + data_len = sym_op->auth.data.length; + data_offset = sym_op->auth.data.offset; + + if (sess->auth_alg == RTE_CRYPTO_AUTH_SNOW3G_UIA2 || + sess->auth_alg == RTE_CRYPTO_AUTH_ZUC_EIA3) { + if ((data_len & 7) || (data_offset & 7)) { + DPAA2_SEC_ERR("AUTH: len/offset must be full bytes"); + return -1; + } + + data_len = data_len >> 3; + data_offset = data_offset >> 3; + } + mbuf = sym_op->m_src; fle = (struct qbman_fle *)rte_malloc(NULL, FLE_SG_MEM_SIZE, RTE_CACHE_LINE_SIZE); @@ -914,25 +929,51 @@ static inline int build_auth_sg_fd( /* i/p fle */ DPAA2_SET_FLE_SG_EXT(ip_fle); DPAA2_SET_FLE_ADDR(ip_fle, DPAA2_VADDR_TO_IOVA(sge)); - /* i/p 1st seg */ - DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); - DPAA2_SET_FLE_OFFSET(sge, sym_op->auth.data.offset + mbuf->data_off); - sge->length = mbuf->data_len - sym_op->auth.data.offset; + ip_fle->length = data_len; - /* i/p segs */ - mbuf = mbuf->next; - while (mbuf) { + if (sess->iv.length) { + uint8_t *iv_ptr; + + iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *, + sess->iv.offset); + + if (sess->auth_alg == RTE_CRYPTO_AUTH_SNOW3G_UIA2) { + iv_ptr = conv_to_snow_f9_iv(iv_ptr); + sge->length = 12; + } else if (sess->auth_alg == RTE_CRYPTO_AUTH_ZUC_EIA3) { + iv_ptr = conv_to_zuc_eia_iv(iv_ptr); + sge->length = 8; + } else { + sge->length = sess->iv.length; + } + DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(iv_ptr)); + ip_fle->length += sge->length; sge++; - DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); - DPAA2_SET_FLE_OFFSET(sge, mbuf->data_off); - sge->length = mbuf->data_len; - mbuf = mbuf->next; } - if (sess->dir == DIR_ENC) { - /* Digest calculation case */ - sge->length -= sess->digest_length; - ip_fle->length = sym_op->auth.data.length; + /* i/p 1st seg */ + DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); + DPAA2_SET_FLE_OFFSET(sge, data_offset + mbuf->data_off); + + if (data_len <= (mbuf->data_len - data_offset)) { + sge->length = data_len; + data_len = 0; } else { + sge->length = mbuf->data_len - data_offset; + + /* remaining i/p segs */ + while ((data_len = data_len - sge->length) && + (mbuf = mbuf->next)) { + sge++; + DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); + DPAA2_SET_FLE_OFFSET(sge, mbuf->data_off); + if (data_len > mbuf->data_len) + sge->length = mbuf->data_len; + else + sge->length = data_len; + } + } + + if (sess->dir == DIR_DEC) { /* Digest verification case */ sge++; old_digest = (uint8_t *)(sge + 1); @@ -940,8 +981,7 @@ static inline int build_auth_sg_fd( sess->digest_length); DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(old_digest)); sge->length = sess->digest_length; - ip_fle->length = sym_op->auth.data.length + - sess->digest_length; + ip_fle->length += sess->digest_length; } DPAA2_SET_FLE_FIN(sge); DPAA2_SET_FLE_FIN(ip_fle); @@ -958,11 +998,26 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, struct qbman_fle *fle, *sge; struct sec_flow_context *flc; struct ctxt_priv *priv = sess->ctxt; + int data_len, data_offset; uint8_t *old_digest; int retval; PMD_INIT_FUNC_TRACE(); + data_len = sym_op->auth.data.length; + data_offset = sym_op->auth.data.offset; + + if (sess->auth_alg == RTE_CRYPTO_AUTH_SNOW3G_UIA2 || + sess->auth_alg == RTE_CRYPTO_AUTH_ZUC_EIA3) { + if ((data_len & 7) || (data_offset & 7)) { + DPAA2_SEC_ERR("AUTH: len/offset must be full bytes"); + return -1; + } + + data_len = data_len >> 3; + data_offset = data_offset >> 3; + } + retval = rte_mempool_get(priv->fle_pool, (void **)(&fle)); if (retval) { DPAA2_SEC_ERR("AUTH Memory alloc failed for SGE"); @@ -978,64 +1033,72 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, DPAA2_SET_FLE_ADDR(fle, (size_t)op); DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; + sge = fle + 2; if (likely(bpid < MAX_BPID)) { DPAA2_SET_FD_BPID(fd, bpid); DPAA2_SET_FLE_BPID(fle, bpid); DPAA2_SET_FLE_BPID(fle + 1, bpid); + DPAA2_SET_FLE_BPID(sge, bpid); + DPAA2_SET_FLE_BPID(sge + 1, bpid); } else { DPAA2_SET_FD_IVP(fd); DPAA2_SET_FLE_IVP(fle); DPAA2_SET_FLE_IVP((fle + 1)); + DPAA2_SET_FLE_IVP(sge); + DPAA2_SET_FLE_IVP((sge + 1)); } + flc = &priv->flc_desc[DESC_INITFINAL].flc; DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc)); + DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle)); + DPAA2_SET_FD_COMPOUND_FMT(fd); DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sym_op->auth.digest.data)); fle->length = sess->digest_length; - - DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle)); - DPAA2_SET_FD_COMPOUND_FMT(fd); fle++; - if (sess->dir == DIR_ENC) { - DPAA2_SET_FLE_ADDR(fle, - DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src)); - DPAA2_SET_FLE_OFFSET(fle, sym_op->auth.data.offset + - sym_op->m_src->data_off); - DPAA2_SET_FD_LEN(fd, sym_op->auth.data.length); - fle->length = sym_op->auth.data.length; - } else { - sge = fle + 2; - DPAA2_SET_FLE_SG_EXT(fle); - DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge)); + /* Setting input FLE */ + DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge)); + DPAA2_SET_FLE_SG_EXT(fle); + fle->length = data_len; + + if (sess->iv.length) { + uint8_t *iv_ptr; + + iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *, + sess->iv.offset); - if (likely(bpid < MAX_BPID)) { - DPAA2_SET_FLE_BPID(sge, bpid); - DPAA2_SET_FLE_BPID(sge + 1, bpid); + if (sess->auth_alg == RTE_CRYPTO_AUTH_SNOW3G_UIA2) { + iv_ptr = conv_to_snow_f9_iv(iv_ptr); + sge->length = 12; } else { - DPAA2_SET_FLE_IVP(sge); - DPAA2_SET_FLE_IVP((sge + 1)); + sge->length = sess->iv.length; } - DPAA2_SET_FLE_ADDR(sge, - DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src)); - DPAA2_SET_FLE_OFFSET(sge, sym_op->auth.data.offset + - sym_op->m_src->data_off); - DPAA2_SET_FD_LEN(fd, sym_op->auth.data.length + - sess->digest_length); - sge->length = sym_op->auth.data.length; + DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(iv_ptr)); + fle->length = fle->length + sge->length; + sge++; + } + + /* Setting data to authenticate */ + DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src)); + DPAA2_SET_FLE_OFFSET(sge, data_offset + sym_op->m_src->data_off); + sge->length = data_len; + + if (sess->dir == DIR_DEC) { sge++; old_digest = (uint8_t *)(sge + 1); rte_memcpy(old_digest, sym_op->auth.digest.data, sess->digest_length); DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(old_digest)); sge->length = sess->digest_length; - fle->length = sym_op->auth.data.length + - sess->digest_length; - DPAA2_SET_FLE_FIN(sge); + fle->length = fle->length + sess->digest_length; } + + DPAA2_SET_FLE_FIN(sge); DPAA2_SET_FLE_FIN(fle); + DPAA2_SET_FD_LEN(fd, fle->length); return 0; } @@ -1046,6 +1109,7 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, { struct rte_crypto_sym_op *sym_op = op->sym; struct qbman_fle *ip_fle, *op_fle, *sge, *fle; + int data_len, data_offset; struct sec_flow_context *flc; struct ctxt_priv *priv = sess->ctxt; struct rte_mbuf *mbuf; @@ -1054,6 +1118,20 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, PMD_INIT_FUNC_TRACE(); + data_len = sym_op->cipher.data.length; + data_offset = sym_op->cipher.data.offset; + + if (sess->cipher_alg == RTE_CRYPTO_CIPHER_SNOW3G_UEA2 || + sess->cipher_alg == RTE_CRYPTO_CIPHER_ZUC_EEA3) { + if ((data_len & 7) || (data_offset & 7)) { + DPAA2_SEC_ERR("CIPHER: len/offset must be full bytes"); + return -1; + } + + data_len = data_len >> 3; + data_offset = data_offset >> 3; + } + if (sym_op->m_dst) mbuf = sym_op->m_dst; else @@ -1079,20 +1157,20 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, DPAA2_SEC_DP_DEBUG( "CIPHER SG: cipher_off: 0x%x/length %d, ivlen=%d" " data_off: 0x%x\n", - sym_op->cipher.data.offset, - sym_op->cipher.data.length, + data_offset, + data_len, sess->iv.length, sym_op->m_src->data_off); /* o/p fle */ DPAA2_SET_FLE_ADDR(op_fle, DPAA2_VADDR_TO_IOVA(sge)); - op_fle->length = sym_op->cipher.data.length; + op_fle->length = data_len; DPAA2_SET_FLE_SG_EXT(op_fle); /* o/p 1st seg */ DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); - DPAA2_SET_FLE_OFFSET(sge, sym_op->cipher.data.offset + mbuf->data_off); - sge->length = mbuf->data_len - sym_op->cipher.data.offset; + DPAA2_SET_FLE_OFFSET(sge, data_offset + mbuf->data_off); + sge->length = mbuf->data_len - data_offset; mbuf = mbuf->next; /* o/p segs */ @@ -1114,7 +1192,7 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, mbuf = sym_op->m_src; sge++; DPAA2_SET_FLE_ADDR(ip_fle, DPAA2_VADDR_TO_IOVA(sge)); - ip_fle->length = sess->iv.length + sym_op->cipher.data.length; + ip_fle->length = sess->iv.length + data_len; DPAA2_SET_FLE_SG_EXT(ip_fle); /* i/p IV */ @@ -1126,9 +1204,8 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, /* i/p 1st seg */ DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); - DPAA2_SET_FLE_OFFSET(sge, sym_op->cipher.data.offset + - mbuf->data_off); - sge->length = mbuf->data_len - sym_op->cipher.data.offset; + DPAA2_SET_FLE_OFFSET(sge, data_offset + mbuf->data_off); + sge->length = mbuf->data_len - data_offset; mbuf = mbuf->next; /* i/p segs */ @@ -1165,7 +1242,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, { struct rte_crypto_sym_op *sym_op = op->sym; struct qbman_fle *fle, *sge; - int retval; + int retval, data_len, data_offset; struct sec_flow_context *flc; struct ctxt_priv *priv = sess->ctxt; uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *, @@ -1174,6 +1251,20 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, PMD_INIT_FUNC_TRACE(); + data_len = sym_op->cipher.data.length; + data_offset = sym_op->cipher.data.offset; + + if (sess->cipher_alg == RTE_CRYPTO_CIPHER_SNOW3G_UEA2 || + sess->cipher_alg == RTE_CRYPTO_CIPHER_ZUC_EEA3) { + if ((data_len & 7) || (data_offset & 7)) { + DPAA2_SEC_ERR("CIPHER: len/offset must be full bytes"); + return -1; + } + + data_len = data_len >> 3; + data_offset = data_offset >> 3; + } + if (sym_op->m_dst) dst = sym_op->m_dst; else @@ -1212,24 +1303,22 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, flc = &priv->flc_desc[0].flc; DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle)); - DPAA2_SET_FD_LEN(fd, sym_op->cipher.data.length + - sess->iv.length); + DPAA2_SET_FD_LEN(fd, data_len + sess->iv.length); DPAA2_SET_FD_COMPOUND_FMT(fd); DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc)); DPAA2_SEC_DP_DEBUG( "CIPHER: cipher_off: 0x%x/length %d, ivlen=%d," " data_off: 0x%x\n", - sym_op->cipher.data.offset, - sym_op->cipher.data.length, + data_offset, + data_len, sess->iv.length, sym_op->m_src->data_off); DPAA2_SET_FLE_ADDR(fle, DPAA2_MBUF_VADDR_TO_IOVA(dst)); - DPAA2_SET_FLE_OFFSET(fle, sym_op->cipher.data.offset + - dst->data_off); + DPAA2_SET_FLE_OFFSET(fle, data_offset + dst->data_off); - fle->length = sym_op->cipher.data.length + sess->iv.length; + fle->length = data_len + sess->iv.length; DPAA2_SEC_DP_DEBUG( "CIPHER: 1 - flc = %p, fle = %p FLEaddr = %x-%x, length %d\n", @@ -1239,7 +1328,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, fle++; DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge)); - fle->length = sym_op->cipher.data.length + sess->iv.length; + fle->length = data_len + sess->iv.length; DPAA2_SET_FLE_SG_EXT(fle); @@ -1248,10 +1337,9 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, sge++; DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src)); - DPAA2_SET_FLE_OFFSET(sge, sym_op->cipher.data.offset + - sym_op->m_src->data_off); + DPAA2_SET_FLE_OFFSET(sge, data_offset + sym_op->m_src->data_off); - sge->length = sym_op->cipher.data.length; + sge->length = data_len; DPAA2_SET_FLE_FIN(sge); DPAA2_SET_FLE_FIN(fle); @@ -1762,32 +1850,60 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, /* Set IV parameters */ session->iv.offset = xform->cipher.iv.offset; session->iv.length = xform->cipher.iv.length; + session->dir = (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ? + DIR_ENC : DIR_DEC; switch (xform->cipher.algo) { case RTE_CRYPTO_CIPHER_AES_CBC: cipherdata.algtype = OP_ALG_ALGSEL_AES; cipherdata.algmode = OP_ALG_AAI_CBC; session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CBC; + bufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0, + SHR_NEVER, &cipherdata, NULL, + session->iv.length, + session->dir); break; case RTE_CRYPTO_CIPHER_3DES_CBC: cipherdata.algtype = OP_ALG_ALGSEL_3DES; cipherdata.algmode = OP_ALG_AAI_CBC; session->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CBC; + bufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0, + SHR_NEVER, &cipherdata, NULL, + session->iv.length, + session->dir); break; case RTE_CRYPTO_CIPHER_AES_CTR: cipherdata.algtype = OP_ALG_ALGSEL_AES; cipherdata.algmode = OP_ALG_AAI_CTR; session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CTR; + bufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0, + SHR_NEVER, &cipherdata, NULL, + session->iv.length, + session->dir); break; case RTE_CRYPTO_CIPHER_3DES_CTR: + cipherdata.algtype = OP_ALG_ALGSEL_3DES; + cipherdata.algmode = OP_ALG_AAI_CTR; + session->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CTR; + bufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0, + SHR_NEVER, &cipherdata, NULL, + session->iv.length, + session->dir); + break; + case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: + cipherdata.algtype = OP_ALG_ALGSEL_SNOW_F8; + session->cipher_alg = RTE_CRYPTO_CIPHER_SNOW3G_UEA2; + bufsize = cnstr_shdsc_snow_f8(priv->flc_desc[0].desc, 1, 0, + &cipherdata, + session->dir); + break; + case RTE_CRYPTO_CIPHER_KASUMI_F8: + case RTE_CRYPTO_CIPHER_ZUC_EEA3: + case RTE_CRYPTO_CIPHER_AES_F8: case RTE_CRYPTO_CIPHER_AES_ECB: case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_AES_XTS: - case RTE_CRYPTO_CIPHER_AES_F8: case RTE_CRYPTO_CIPHER_ARC4: - case RTE_CRYPTO_CIPHER_KASUMI_F8: - case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: - case RTE_CRYPTO_CIPHER_ZUC_EEA3: case RTE_CRYPTO_CIPHER_NULL: DPAA2_SEC_ERR("Crypto: Unsupported Cipher alg %u", xform->cipher.algo); @@ -1797,12 +1913,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, xform->cipher.algo); goto error_out; } - session->dir = (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ? - DIR_ENC : DIR_DEC; - bufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0, SHR_NEVER, - &cipherdata, NULL, session->iv.length, - session->dir); if (bufsize < 0) { DPAA2_SEC_ERR("Crypto: Descriptor build failed"); goto error_out; @@ -1865,40 +1976,77 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, authdata.key_type = RTA_DATA_IMM; session->digest_length = xform->auth.digest_length; + session->dir = (xform->auth.op == RTE_CRYPTO_AUTH_OP_GENERATE) ? + DIR_ENC : DIR_DEC; switch (xform->auth.algo) { case RTE_CRYPTO_AUTH_SHA1_HMAC: authdata.algtype = OP_ALG_ALGSEL_SHA1; authdata.algmode = OP_ALG_AAI_HMAC; session->auth_alg = RTE_CRYPTO_AUTH_SHA1_HMAC; + bufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc, + 1, 0, SHR_NEVER, &authdata, + !session->dir, + session->digest_length); break; case RTE_CRYPTO_AUTH_MD5_HMAC: authdata.algtype = OP_ALG_ALGSEL_MD5; authdata.algmode = OP_ALG_AAI_HMAC; session->auth_alg = RTE_CRYPTO_AUTH_MD5_HMAC; + bufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc, + 1, 0, SHR_NEVER, &authdata, + !session->dir, + session->digest_length); break; case RTE_CRYPTO_AUTH_SHA256_HMAC: authdata.algtype = OP_ALG_ALGSEL_SHA256; authdata.algmode = OP_ALG_AAI_HMAC; session->auth_alg = RTE_CRYPTO_AUTH_SHA256_HMAC; + bufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc, + 1, 0, SHR_NEVER, &authdata, + !session->dir, + session->digest_length); break; case RTE_CRYPTO_AUTH_SHA384_HMAC: authdata.algtype = OP_ALG_ALGSEL_SHA384; authdata.algmode = OP_ALG_AAI_HMAC; session->auth_alg = RTE_CRYPTO_AUTH_SHA384_HMAC; + bufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc, + 1, 0, SHR_NEVER, &authdata, + !session->dir, + session->digest_length); break; case RTE_CRYPTO_AUTH_SHA512_HMAC: authdata.algtype = OP_ALG_ALGSEL_SHA512; authdata.algmode = OP_ALG_AAI_HMAC; session->auth_alg = RTE_CRYPTO_AUTH_SHA512_HMAC; + bufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc, + 1, 0, SHR_NEVER, &authdata, + !session->dir, + session->digest_length); break; case RTE_CRYPTO_AUTH_SHA224_HMAC: authdata.algtype = OP_ALG_ALGSEL_SHA224; authdata.algmode = OP_ALG_AAI_HMAC; session->auth_alg = RTE_CRYPTO_AUTH_SHA224_HMAC; + bufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc, + 1, 0, SHR_NEVER, &authdata, + !session->dir, + session->digest_length); break; - case RTE_CRYPTO_AUTH_AES_XCBC_MAC: case RTE_CRYPTO_AUTH_SNOW3G_UIA2: + authdata.algtype = OP_ALG_ALGSEL_SNOW_F9; + authdata.algmode = OP_ALG_AAI_F9; + session->auth_alg = RTE_CRYPTO_AUTH_SNOW3G_UIA2; + session->iv.offset = xform->auth.iv.offset; + session->iv.length = xform->auth.iv.length; + bufsize = cnstr_shdsc_snow_f9(priv->flc_desc[DESC_INITFINAL].desc, + 1, 0, &authdata, + !session->dir, + session->digest_length); + break; + case RTE_CRYPTO_AUTH_KASUMI_F9: + case RTE_CRYPTO_AUTH_ZUC_EIA3: case RTE_CRYPTO_AUTH_NULL: case RTE_CRYPTO_AUTH_SHA1: case RTE_CRYPTO_AUTH_SHA256: @@ -1907,10 +2055,9 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, case RTE_CRYPTO_AUTH_SHA384: case RTE_CRYPTO_AUTH_MD5: case RTE_CRYPTO_AUTH_AES_GMAC: - case RTE_CRYPTO_AUTH_KASUMI_F9: + case RTE_CRYPTO_AUTH_AES_XCBC_MAC: case RTE_CRYPTO_AUTH_AES_CMAC: case RTE_CRYPTO_AUTH_AES_CBC_MAC: - case RTE_CRYPTO_AUTH_ZUC_EIA3: DPAA2_SEC_ERR("Crypto: Unsupported auth alg %un", xform->auth.algo); goto error_out; @@ -1919,12 +2066,7 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, xform->auth.algo); goto error_out; } - session->dir = (xform->auth.op == RTE_CRYPTO_AUTH_OP_GENERATE) ? - DIR_ENC : DIR_DEC; - bufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc, - 1, 0, SHR_NEVER, &authdata, !session->dir, - session->digest_length); if (bufsize < 0) { DPAA2_SEC_ERR("Crypto: Invalid buffer length"); goto error_out; diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h index afd98b2d5..3d793363b 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h @@ -411,7 +411,51 @@ static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = { }, } }, } }, - + { /* SNOW 3G (UIA2) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* SNOW 3G (UEA2) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; diff --git a/drivers/crypto/dpaa2_sec/hw/desc/algo.h b/drivers/crypto/dpaa2_sec/hw/desc/algo.h index 5e8e5e79c..042cffa59 100644 --- a/drivers/crypto/dpaa2_sec/hw/desc/algo.h +++ b/drivers/crypto/dpaa2_sec/hw/desc/algo.h @@ -57,6 +57,36 @@ cnstr_shdsc_snow_f8(uint32_t *descbuf, bool ps, bool swap, return PROGRAM_FINALIZE(p); } +/** + * conv_to_snow_f9_iv - SNOW/f9 (UIA2) IV 16bit to 12 bit convert + * function for 3G. + * @iv: 16 bit original IV data + * + * Return: 12 bit IV data as understood by SEC HW + */ + +static inline uint8_t *conv_to_snow_f9_iv(uint8_t *iv) +{ + uint8_t temp = (iv[8] == iv[0]) ? 0 : 4; + + iv[12] = iv[4]; + iv[13] = iv[5]; + iv[14] = iv[6]; + iv[15] = iv[7]; + + iv[8] = temp; + iv[9] = 0x00; + iv[10] = 0x00; + iv[11] = 0x00; + + iv[4] = iv[0]; + iv[5] = iv[1]; + iv[6] = iv[2]; + iv[7] = iv[3]; + + return (iv + 4); +} + /** * cnstr_shdsc_snow_f9 - SNOW/f9 (UIA2) as a shared descriptor * @descbuf: pointer to descriptor-under-construction buffer From patchwork Mon Sep 30 14:41:00 2019 Content-Type: text/plain; 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Mon, 30 Sep 2019 16:56:39 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id DEEED4030D; Mon, 30 Sep 2019 22:56:35 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: aconole@redhat.com, anoobj@marvell.com, Hemant Agrawal , Vakul Garg Date: Mon, 30 Sep 2019 20:11:00 +0530 Message-Id: <20190930144104.12742-21-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930144104.12742-1-akhil.goyal@nxp.com> References: <20190930115237.5073-1-akhil.goyal@nxp.com> <20190930144104.12742-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v3 20/24] crypto/dpaa2_sec: support zuc ciphering/integrity X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Signed-off-by: Hemant Agrawal Signed-off-by: Vakul Garg Acked-by: Akhil Goyal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 25 +++++++++++- drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 45 +++++++++++++++++++++ 2 files changed, 68 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 451fa91fb..165324567 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -1072,6 +1072,9 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, if (sess->auth_alg == RTE_CRYPTO_AUTH_SNOW3G_UIA2) { iv_ptr = conv_to_snow_f9_iv(iv_ptr); sge->length = 12; + } else if (sess->auth_alg == RTE_CRYPTO_AUTH_ZUC_EIA3) { + iv_ptr = conv_to_zuc_eia_iv(iv_ptr); + sge->length = 8; } else { sge->length = sess->iv.length; } @@ -1897,8 +1900,14 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, &cipherdata, session->dir); break; - case RTE_CRYPTO_CIPHER_KASUMI_F8: case RTE_CRYPTO_CIPHER_ZUC_EEA3: + cipherdata.algtype = OP_ALG_ALGSEL_ZUCE; + session->cipher_alg = RTE_CRYPTO_CIPHER_ZUC_EEA3; + bufsize = cnstr_shdsc_zuce(priv->flc_desc[0].desc, 1, 0, + &cipherdata, + session->dir); + break; + case RTE_CRYPTO_CIPHER_KASUMI_F8: case RTE_CRYPTO_CIPHER_AES_F8: case RTE_CRYPTO_CIPHER_AES_ECB: case RTE_CRYPTO_CIPHER_3DES_ECB: @@ -2045,8 +2054,18 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, !session->dir, session->digest_length); break; - case RTE_CRYPTO_AUTH_KASUMI_F9: case RTE_CRYPTO_AUTH_ZUC_EIA3: + authdata.algtype = OP_ALG_ALGSEL_ZUCA; + authdata.algmode = OP_ALG_AAI_F9; + session->auth_alg = RTE_CRYPTO_AUTH_ZUC_EIA3; + session->iv.offset = xform->auth.iv.offset; + session->iv.length = xform->auth.iv.length; + bufsize = cnstr_shdsc_zuca(priv->flc_desc[DESC_INITFINAL].desc, + 1, 0, &authdata, + !session->dir, + session->digest_length); + break; + case RTE_CRYPTO_AUTH_KASUMI_F9: case RTE_CRYPTO_AUTH_NULL: case RTE_CRYPTO_AUTH_SHA1: case RTE_CRYPTO_AUTH_SHA256: @@ -2357,6 +2376,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CTR; break; case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: + case RTE_CRYPTO_CIPHER_ZUC_EEA3: case RTE_CRYPTO_CIPHER_NULL: case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_AES_ECB: @@ -2651,6 +2671,7 @@ dpaa2_sec_ipsec_proto_init(struct rte_crypto_cipher_xform *cipher_xform, cipherdata->algtype = OP_PCL_IPSEC_NULL; break; case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: + case RTE_CRYPTO_CIPHER_ZUC_EEA3: case RTE_CRYPTO_CIPHER_3DES_ECB: case RTE_CRYPTO_CIPHER_AES_ECB: case RTE_CRYPTO_CIPHER_KASUMI_F8: diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h index 3d793363b..ca4fcfe9b 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h @@ -456,6 +456,51 @@ static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = { }, } }, } }, + { /* ZUC (EEA3) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_ZUC_EEA3, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, + { /* ZUC (EIA3) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_ZUC_EIA3, + .block_size = 16, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + .iv_size = { + .min = 16, + .max = 16, + .increment = 0 + } + }, } + }, } + }, RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; From patchwork Mon Sep 30 14:41:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 174766 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7242929ill; Mon, 30 Sep 2019 08:00:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqx9CyE3NUd009Lg0GPE85J0q+mZHXnqUqNtSwTVzzPzmui3S5UQyWDrSYSuXtWvWCEOEWfT X-Received: by 2002:aa7:dad9:: with SMTP id x25mr20504734eds.7.1569855626114; Mon, 30 Sep 2019 08:00:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569855626; cv=none; d=google.com; s=arc-20160816; b=VI1ae2rBSq5FJ/QuOyNe4rSxGbJ2yr22H4xHO+UJVXPo9NXyVfQOjzOW8IxOSEkW6z jsM8PUasQl8WAF8PvuFWb0dW0+a2VTL4Gn/oT3I6hq6ltlcTMD1HwvigiXLbE3BR/jrU aHIKNCVfP//aCQqF8Rs+biRlECkX2O8Wx3A+Lntr4ilx5sPkiLWIWlpfa8dPWOBXJZQC Kcyf4ADEb3r64uJ8XuwgIDNpGTjZhC5SextUTfJ/izpDljVnL4TdGy+0GqT5SDl5mu1j Ab0lZNM2HVcK+2XO8Vi11Cpv7ePDrF6U3LEUf+08dwDlY0U7X5v0MNvTS9JTAPf/Fj73 KykQ== ARC-Message-Signature: i=1; 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[92.243.14.124]) by mx.google.com with ESMTP id a41si7196390eda.366.2019.09.30.08.00.25; Mon, 30 Sep 2019 08:00:26 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2C5991BF52; Mon, 30 Sep 2019 16:57:54 +0200 (CEST) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id A2D751BED3 for ; Mon, 30 Sep 2019 16:56:43 +0200 (CEST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 679861A0110; Mon, 30 Sep 2019 16:56:43 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 9B3B11A0043; Mon, 30 Sep 2019 16:56:40 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 1C88040318; Mon, 30 Sep 2019 22:56:36 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: aconole@redhat.com, anoobj@marvell.com, Hemant Agrawal , Akhil Goyal Date: Mon, 30 Sep 2019 20:11:01 +0530 Message-Id: <20190930144104.12742-22-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930144104.12742-1-akhil.goyal@nxp.com> References: <20190930115237.5073-1-akhil.goyal@nxp.com> <20190930144104.12742-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v3 21/24] crypto/dpaa2_sec: allocate context as per num segs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal DPAA2_SEC hardware can support any number of SG entries. This patch allocate as many SG entries as are required. Signed-off-by: Hemant Agrawal Signed-off-by: Akhil Goyal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 28 +++++++++++++-------- 1 file changed, 17 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 165324567..b811f2f1b 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -55,7 +55,7 @@ typedef uint64_t dma_addr_t; #define FLE_POOL_NUM_BUFS 32000 #define FLE_POOL_BUF_SIZE 256 #define FLE_POOL_CACHE_SIZE 512 -#define FLE_SG_MEM_SIZE 2048 +#define FLE_SG_MEM_SIZE(num) (FLE_POOL_BUF_SIZE + ((num) * 32)) #define SEC_FLC_DHR_OUTBOUND -114 #define SEC_FLC_DHR_INBOUND 0 @@ -83,13 +83,14 @@ build_proto_compound_sg_fd(dpaa2_sec_session *sess, mbuf = sym_op->m_src; /* first FLE entry used to store mbuf and session ctxt */ - fle = (struct qbman_fle *)rte_malloc(NULL, FLE_SG_MEM_SIZE, + fle = (struct qbman_fle *)rte_malloc(NULL, + FLE_SG_MEM_SIZE(mbuf->nb_segs + sym_op->m_src->nb_segs), RTE_CACHE_LINE_SIZE); if (unlikely(!fle)) { DPAA2_SEC_DP_ERR("Proto:SG: Memory alloc failed for SGE"); return -1; } - memset(fle, 0, FLE_SG_MEM_SIZE); + memset(fle, 0, FLE_SG_MEM_SIZE(mbuf->nb_segs + sym_op->m_src->nb_segs)); DPAA2_SET_FLE_ADDR(fle, (size_t)op); DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); @@ -312,13 +313,14 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess, mbuf = sym_op->m_src; /* first FLE entry used to store mbuf and session ctxt */ - fle = (struct qbman_fle *)rte_malloc(NULL, FLE_SG_MEM_SIZE, + fle = (struct qbman_fle *)rte_malloc(NULL, + FLE_SG_MEM_SIZE(mbuf->nb_segs + sym_op->m_src->nb_segs), RTE_CACHE_LINE_SIZE); if (unlikely(!fle)) { DPAA2_SEC_ERR("GCM SG: Memory alloc failed for SGE"); return -1; } - memset(fle, 0, FLE_SG_MEM_SIZE); + memset(fle, 0, FLE_SG_MEM_SIZE(mbuf->nb_segs + sym_op->m_src->nb_segs)); DPAA2_SET_FLE_ADDR(fle, (size_t)op); DPAA2_FLE_SAVE_CTXT(fle, (size_t)priv); @@ -608,13 +610,14 @@ build_authenc_sg_fd(dpaa2_sec_session *sess, mbuf = sym_op->m_src; /* first FLE entry used to store mbuf and session ctxt */ - fle = (struct qbman_fle *)rte_malloc(NULL, FLE_SG_MEM_SIZE, + fle = (struct qbman_fle *)rte_malloc(NULL, + FLE_SG_MEM_SIZE(mbuf->nb_segs + sym_op->m_src->nb_segs), RTE_CACHE_LINE_SIZE); if (unlikely(!fle)) { DPAA2_SEC_ERR("AUTHENC SG: Memory alloc failed for SGE"); return -1; } - memset(fle, 0, FLE_SG_MEM_SIZE); + memset(fle, 0, FLE_SG_MEM_SIZE(mbuf->nb_segs + sym_op->m_src->nb_segs)); DPAA2_SET_FLE_ADDR(fle, (size_t)op); DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); @@ -901,13 +904,14 @@ static inline int build_auth_sg_fd( } mbuf = sym_op->m_src; - fle = (struct qbman_fle *)rte_malloc(NULL, FLE_SG_MEM_SIZE, + fle = (struct qbman_fle *)rte_malloc(NULL, + FLE_SG_MEM_SIZE(mbuf->nb_segs), RTE_CACHE_LINE_SIZE); if (unlikely(!fle)) { DPAA2_SEC_ERR("AUTH SG: Memory alloc failed for SGE"); return -1; } - memset(fle, 0, FLE_SG_MEM_SIZE); + memset(fle, 0, FLE_SG_MEM_SIZE(mbuf->nb_segs)); /* first FLE entry used to store mbuf and session ctxt */ DPAA2_SET_FLE_ADDR(fle, (size_t)op); DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); @@ -1140,13 +1144,15 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, else mbuf = sym_op->m_src; - fle = (struct qbman_fle *)rte_malloc(NULL, FLE_SG_MEM_SIZE, + /* first FLE entry used to store mbuf and session ctxt */ + fle = (struct qbman_fle *)rte_malloc(NULL, + FLE_SG_MEM_SIZE(mbuf->nb_segs + sym_op->m_src->nb_segs), RTE_CACHE_LINE_SIZE); if (!fle) { DPAA2_SEC_ERR("CIPHER SG: Memory alloc failed for SGE"); return -1; } - memset(fle, 0, FLE_SG_MEM_SIZE); + memset(fle, 0, FLE_SG_MEM_SIZE(mbuf->nb_segs + sym_op->m_src->nb_segs)); /* first FLE entry used to store mbuf and session ctxt */ DPAA2_SET_FLE_ADDR(fle, (size_t)op); DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); From patchwork Mon Sep 30 14:41:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 174767 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7243206ill; Mon, 30 Sep 2019 08:00:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqymgj+PTbnaeelJox5m4Fg/Hghz9ozX29FkHcNWCrpqftIy1kud6vxCHZQlgJJ5A2zpUlAu X-Received: by 2002:a17:906:2542:: with SMTP id j2mr20091007ejb.278.1569855639173; Mon, 30 Sep 2019 08:00:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569855639; cv=none; d=google.com; s=arc-20160816; b=jmIAu/ZlyMNrpc7E09jJLM7+r+Y/ax8JRHZiM+R/+07ApMVRSi1n/uBDQWPxpchmlu hpDvloW0WQxelM2QBUYlz+TSQZETIFv4rOhYw6iwYT9W+ke13C/G9GRlwbU+34wEy3sm r2c7Slf2ME4PiE8dIEYGS1r5mkt31buIl0T5ENLSLOMLgcLmeEw3ZGUVjCSIqFoa15i7 SSIE6gAzNSzWrPdwPT6FgJHcGAFR61FEuM5p5coiNYNkXwao0p7s5SlRFQiKkyc0GnRA KRaLC+6vLGyrFXgIDPl0r9ygtz3+J9gXOFXDUkSztC3mi3vfgfp2+h1ObOhraYjt9Ll3 Wm8g== ARC-Message-Signature: i=1; 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[92.243.14.124]) by mx.google.com with ESMTP id k2si7135788ede.311.2019.09.30.08.00.38; Mon, 30 Sep 2019 08:00:39 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 581BF1BF5B; Mon, 30 Sep 2019 16:57:56 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id C36E61BED5 for ; Mon, 30 Sep 2019 16:56:43 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A18B420008A; Mon, 30 Sep 2019 16:56:43 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 47A1920049E; Mon, 30 Sep 2019 16:56:41 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 45F3B40313; Mon, 30 Sep 2019 22:56:38 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: aconole@redhat.com, anoobj@marvell.com, Hemant Agrawal Date: Mon, 30 Sep 2019 20:11:02 +0530 Message-Id: <20190930144104.12742-23-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930144104.12742-1-akhil.goyal@nxp.com> References: <20190930115237.5073-1-akhil.goyal@nxp.com> <20190930144104.12742-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v3 22/24] crypto/dpaa_sec: dynamic contxt buffer for SG cases X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal This patch allocate/clean the SEC context dynamically based on the number of SG entries in the buffer. Signed-off-by: Hemant Agrawal Acked-by: Akhil Goyal --- drivers/crypto/dpaa_sec/dpaa_sec.c | 43 ++++++++++++++---------------- drivers/crypto/dpaa_sec/dpaa_sec.h | 8 +++--- 2 files changed, 23 insertions(+), 28 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c index 291cba28d..fa9d03adc 100644 --- a/drivers/crypto/dpaa_sec/dpaa_sec.c +++ b/drivers/crypto/dpaa_sec/dpaa_sec.c @@ -65,10 +65,10 @@ dpaa_sec_op_ending(struct dpaa_sec_op_ctx *ctx) } static inline struct dpaa_sec_op_ctx * -dpaa_sec_alloc_ctx(dpaa_sec_session *ses) +dpaa_sec_alloc_ctx(dpaa_sec_session *ses, int sg_count) { struct dpaa_sec_op_ctx *ctx; - int retval; + int i, retval; retval = rte_mempool_get(ses->ctx_pool, (void **)(&ctx)); if (!ctx || retval) { @@ -81,14 +81,11 @@ dpaa_sec_alloc_ctx(dpaa_sec_session *ses) * to clear all the SG entries. dpaa_sec_alloc_ctx() is called for * each packet, memset is costlier than dcbz_64(). */ - dcbz_64(&ctx->job.sg[SG_CACHELINE_0]); - dcbz_64(&ctx->job.sg[SG_CACHELINE_1]); - dcbz_64(&ctx->job.sg[SG_CACHELINE_2]); - dcbz_64(&ctx->job.sg[SG_CACHELINE_3]); + for (i = 0; i < sg_count && i < MAX_JOB_SG_ENTRIES; i += 4) + dcbz_64(&ctx->job.sg[i]); ctx->ctx_pool = ses->ctx_pool; - ctx->vtop_offset = (size_t) ctx - - rte_mempool_virt2iova(ctx); + ctx->vtop_offset = (size_t) ctx - rte_mempool_virt2iova(ctx); return ctx; } @@ -855,12 +852,12 @@ build_auth_only_sg(struct rte_crypto_op *op, dpaa_sec_session *ses) else extra_segs = 2; - if ((mbuf->nb_segs + extra_segs) > MAX_SG_ENTRIES) { + if (mbuf->nb_segs > MAX_SG_ENTRIES) { DPAA_SEC_DP_ERR("Auth: Max sec segs supported is %d", MAX_SG_ENTRIES); return NULL; } - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, mbuf->nb_segs + extra_segs); if (!ctx) return NULL; @@ -938,7 +935,7 @@ build_auth_only(struct rte_crypto_op *op, dpaa_sec_session *ses) rte_iova_t start_addr; uint8_t *old_digest; - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, 4); if (!ctx) return NULL; @@ -1008,13 +1005,13 @@ build_cipher_only_sg(struct rte_crypto_op *op, dpaa_sec_session *ses) req_segs = mbuf->nb_segs * 2 + 3; } - if (req_segs > MAX_SG_ENTRIES) { + if (mbuf->nb_segs > MAX_SG_ENTRIES) { DPAA_SEC_DP_ERR("Cipher: Max sec segs supported is %d", MAX_SG_ENTRIES); return NULL; } - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, req_segs); if (!ctx) return NULL; @@ -1094,7 +1091,7 @@ build_cipher_only(struct rte_crypto_op *op, dpaa_sec_session *ses) uint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *, ses->iv.offset); - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, 4); if (!ctx) return NULL; @@ -1161,13 +1158,13 @@ build_cipher_auth_gcm_sg(struct rte_crypto_op *op, dpaa_sec_session *ses) if (ses->auth_only_len) req_segs++; - if (req_segs > MAX_SG_ENTRIES) { + if (mbuf->nb_segs > MAX_SG_ENTRIES) { DPAA_SEC_DP_ERR("AEAD: Max sec segs supported is %d", MAX_SG_ENTRIES); return NULL; } - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, req_segs); if (!ctx) return NULL; @@ -1296,7 +1293,7 @@ build_cipher_auth_gcm(struct rte_crypto_op *op, dpaa_sec_session *ses) else dst_start_addr = src_start_addr; - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, 7); if (!ctx) return NULL; @@ -1409,13 +1406,13 @@ build_cipher_auth_sg(struct rte_crypto_op *op, dpaa_sec_session *ses) req_segs = mbuf->nb_segs * 2 + 4; } - if (req_segs > MAX_SG_ENTRIES) { + if (mbuf->nb_segs > MAX_SG_ENTRIES) { DPAA_SEC_DP_ERR("Cipher-Auth: Max sec segs supported is %d", MAX_SG_ENTRIES); return NULL; } - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, req_segs); if (!ctx) return NULL; @@ -1533,7 +1530,7 @@ build_cipher_auth(struct rte_crypto_op *op, dpaa_sec_session *ses) else dst_start_addr = src_start_addr; - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, 7); if (!ctx) return NULL; @@ -1619,7 +1616,7 @@ build_proto(struct rte_crypto_op *op, dpaa_sec_session *ses) struct qm_sg_entry *sg; phys_addr_t src_start_addr, dst_start_addr; - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, 2); if (!ctx) return NULL; cf = &ctx->job; @@ -1666,13 +1663,13 @@ build_proto_sg(struct rte_crypto_op *op, dpaa_sec_session *ses) mbuf = sym->m_src; req_segs = mbuf->nb_segs + sym->m_src->nb_segs + 2; - if (req_segs > MAX_SG_ENTRIES) { + if (mbuf->nb_segs > MAX_SG_ENTRIES) { DPAA_SEC_DP_ERR("Proto: Max sec segs supported is %d", MAX_SG_ENTRIES); return NULL; } - ctx = dpaa_sec_alloc_ctx(ses); + ctx = dpaa_sec_alloc_ctx(ses, req_segs); if (!ctx) return NULL; cf = &ctx->job; diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.h b/drivers/crypto/dpaa_sec/dpaa_sec.h index 68461cecc..2a6a3fad7 100644 --- a/drivers/crypto/dpaa_sec/dpaa_sec.h +++ b/drivers/crypto/dpaa_sec/dpaa_sec.h @@ -183,13 +183,11 @@ struct dpaa_sec_dev_private { }; #define MAX_SG_ENTRIES 16 -#define SG_CACHELINE_0 0 -#define SG_CACHELINE_1 4 -#define SG_CACHELINE_2 8 -#define SG_CACHELINE_3 12 +#define MAX_JOB_SG_ENTRIES 36 + struct dpaa_sec_job { /* sg[0] output, sg[1] input, others are possible sub frames */ - struct qm_sg_entry sg[MAX_SG_ENTRIES]; + struct qm_sg_entry sg[MAX_JOB_SG_ENTRIES]; }; #define DPAA_MAX_NB_MAX_DIGEST 32 From patchwork Mon Sep 30 14:41:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 174768 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7243911ill; Mon, 30 Sep 2019 08:01:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqxI91sql1Zoli2jXpN2i397lT4k/ZbcZaWYSXyR4YftAts77OagH4EeCE0Lavdvabi0Tk5x X-Received: by 2002:a50:95a3:: with SMTP id w32mr20161148eda.211.1569855669859; Mon, 30 Sep 2019 08:01:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569855669; cv=none; d=google.com; s=arc-20160816; b=du1Yf2i8doG8RfRpLHbL1rb+VAG41nhQrYKEZiEQGSjoRBOetAdoajjPU7DiNpXCZv mX77omJl6MZMr8VavvYKwlU7uwm/JNZisJAX27eokbBbT5SPOCbnSQkYMkk+IpWZWE/n qfJjWovYm6vI0NrYUC54afRkNqNiNvGRgPJ2MvPbQQqTFm3MAwsOpO8xjCgsPb97DgQX 5mdsk2C7bRhj2KoZHoYkWBrOd+EcMi/ZYi/3od99R1+ZuVW+L2FC3WeaDMEV1AEb6jZc w1cM0IDBUaVA3o38mJ0TKCG9VCmF2XFr2sUKHhRmhXtj+Qv7Hfs9iBNTkfz+7DmaEUO5 SSHA== ARC-Message-Signature: i=1; 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[92.243.14.124]) by mx.google.com with ESMTP id v4si7055506edm.183.2019.09.30.08.01.09; Mon, 30 Sep 2019 08:01:09 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 565821BFB3; Mon, 30 Sep 2019 16:58:03 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id D84C21BED7 for ; Mon, 30 Sep 2019 16:56:45 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id BA8682000A7; Mon, 30 Sep 2019 16:56:45 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6107C200489; Mon, 30 Sep 2019 16:56:43 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 60E88402C1; Mon, 30 Sep 2019 22:56:40 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: aconole@redhat.com, anoobj@marvell.com, Hemant Agrawal Date: Mon, 30 Sep 2019 20:11:04 +0530 Message-Id: <20190930144104.12742-25-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930144104.12742-1-akhil.goyal@nxp.com> References: <20190930115237.5073-1-akhil.goyal@nxp.com> <20190930144104.12742-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v3 24/24] crypto/dpaa2_sec: improve debug logging X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal unnecessary debug logs in data path are removed and hardware debug logs are compiled off. Signed-off-by: Hemant Agrawal Acked-by: Akhil Goyal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 41 ++++++++------------- 1 file changed, 16 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index b811f2f1b..2ab34a00f 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -305,8 +305,6 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess, uint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv.offset); - PMD_INIT_FUNC_TRACE(); - if (sym_op->m_dst) mbuf = sym_op->m_dst; else @@ -453,8 +451,6 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess, uint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv.offset); - PMD_INIT_FUNC_TRACE(); - if (sym_op->m_dst) dst = sym_op->m_dst; else @@ -602,8 +598,6 @@ build_authenc_sg_fd(dpaa2_sec_session *sess, uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv.offset); - PMD_INIT_FUNC_TRACE(); - if (sym_op->m_dst) mbuf = sym_op->m_dst; else @@ -748,8 +742,6 @@ build_authenc_fd(dpaa2_sec_session *sess, sess->iv.offset); struct rte_mbuf *dst; - PMD_INIT_FUNC_TRACE(); - if (sym_op->m_dst) dst = sym_op->m_dst; else @@ -887,8 +879,6 @@ static inline int build_auth_sg_fd( uint8_t *old_digest; struct rte_mbuf *mbuf; - PMD_INIT_FUNC_TRACE(); - data_len = sym_op->auth.data.length; data_offset = sym_op->auth.data.offset; @@ -1006,8 +996,6 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, uint8_t *old_digest; int retval; - PMD_INIT_FUNC_TRACE(); - data_len = sym_op->auth.data.length; data_offset = sym_op->auth.data.offset; @@ -1123,8 +1111,6 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv.offset); - PMD_INIT_FUNC_TRACE(); - data_len = sym_op->cipher.data.length; data_offset = sym_op->cipher.data.offset; @@ -1258,8 +1244,6 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, sess->iv.offset); struct rte_mbuf *dst; - PMD_INIT_FUNC_TRACE(); - data_len = sym_op->cipher.data.length; data_offset = sym_op->cipher.data.offset; @@ -1371,8 +1355,6 @@ build_sec_fd(struct rte_crypto_op *op, int ret = -1; dpaa2_sec_session *sess; - PMD_INIT_FUNC_TRACE(); - if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) sess = (dpaa2_sec_session *)get_sym_session_private_data( op->sym->session, cryptodev_driver_id); @@ -1821,7 +1803,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, { struct dpaa2_sec_dev_private *dev_priv = dev->data->dev_private; struct alginfo cipherdata; - int bufsize, i; + int bufsize; struct ctxt_priv *priv; struct sec_flow_context *flc; @@ -1937,9 +1919,11 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; session->ctxt = priv; +#ifdef CAAM_DESC_DEBUG + int i; for (i = 0; i < bufsize; i++) DPAA2_SEC_DEBUG("DESC[%d]:0x%x", i, priv->flc_desc[0].desc[i]); - +#endif return 0; error_out: @@ -1955,7 +1939,7 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, { struct dpaa2_sec_dev_private *dev_priv = dev->data->dev_private; struct alginfo authdata; - int bufsize, i; + int bufsize; struct ctxt_priv *priv; struct sec_flow_context *flc; @@ -2099,10 +2083,12 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; session->ctxt = priv; +#ifdef CAAM_DESC_DEBUG + int i; for (i = 0; i < bufsize; i++) DPAA2_SEC_DEBUG("DESC[%d]:0x%x", i, priv->flc_desc[DESC_INITFINAL].desc[i]); - +#endif return 0; @@ -2120,7 +2106,7 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev, struct dpaa2_sec_aead_ctxt *ctxt = &session->ext_params.aead_ctxt; struct dpaa2_sec_dev_private *dev_priv = dev->data->dev_private; struct alginfo aeaddata; - int bufsize, i; + int bufsize; struct ctxt_priv *priv; struct sec_flow_context *flc; struct rte_crypto_aead_xform *aead_xform = &xform->aead; @@ -2218,10 +2204,12 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; session->ctxt = priv; +#ifdef CAAM_DESC_DEBUG + int i; for (i = 0; i < bufsize; i++) DPAA2_SEC_DEBUG("DESC[%d]:0x%x\n", i, priv->flc_desc[0].desc[i]); - +#endif return 0; error_out: @@ -2239,7 +2227,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, struct dpaa2_sec_aead_ctxt *ctxt = &session->ext_params.aead_ctxt; struct dpaa2_sec_dev_private *dev_priv = dev->data->dev_private; struct alginfo authdata, cipherdata; - int bufsize, i; + int bufsize; struct ctxt_priv *priv; struct sec_flow_context *flc; struct rte_crypto_cipher_xform *cipher_xform; @@ -2444,9 +2432,12 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; session->ctxt = priv; +#ifdef CAAM_DESC_DEBUG + int i; for (i = 0; i < bufsize; i++) DPAA2_SEC_DEBUG("DESC[%d]:0x%x", i, priv->flc_desc[0].desc[i]); +#endif return 0;