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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000066EA.mail.protection.outlook.com (10.167.249.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7386.12 via Frontend Transport; Wed, 13 Mar 2024 10:05:04 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 13 Mar 2024 05:04:58 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 1/7] cpufreq: amd-pstate: initialize new core precision boost state Date: Wed, 13 Mar 2024 18:04:38 +0800 Message-ID: <1bd9da56478c07fc2117b7c11f88eb517bd60f0f.1710322310.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066EA:EE_|SA1PR12MB6773:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c3cc435-2ea3-448d-7a25-08dc43450dff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:05:04.3919 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c3cc435-2ea3-448d-7a25-08dc43450dff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6773 From: Perry Yuan Add gloal global_params to represent current CPU Performance Boost(cpb) state for cpu frequency scaling, both active and passive modes all can support CPU cores frequency boosting control which is based on the BIOS setting, while BIOS turn on the "Core Performance Boost", it will allow OS control each core highest perf limitation from OS side. If core performance boost is disabled while a core is in a boosted P-state, the core transitions to the highest performance non-boosted P-state, that is the same as the nominal frequency limit. Reported-by: Artem S. Tashkinov" Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 50 ++++++++++++------------------------ include/linux/amd-pstate.h | 14 ++++++++++ 2 files changed, 31 insertions(+), 33 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 2015c9fcc3c9..ef6381b48e76 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -67,6 +67,8 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; +struct amd_pstate_global_params amd_pstate_global_params; +EXPORT_SYMBOL_GPL(amd_pstate_global_params); /* * AMD Energy Preference Performance (EPP) @@ -676,43 +678,21 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) return lowest_nonlinear_freq * 1000; } -static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) +static int amd_pstate_boost_init(struct amd_cpudata *cpudata) { - struct amd_cpudata *cpudata = policy->driver_data; + u64 boost_val; int ret; - if (!cpudata->boost_supported) { - pr_err("Boost mode is not supported by this processor or SBIOS\n"); - return -EINVAL; - } - - if (state) - policy->cpuinfo.max_freq = cpudata->max_freq; - else - policy->cpuinfo.max_freq = cpudata->nominal_freq; - - policy->max = policy->cpuinfo.max_freq; - - ret = freq_qos_update_request(&cpudata->req[1], - policy->cpuinfo.max_freq); - if (ret < 0) + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); return ret; + } - return 0; -} - -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) -{ - u32 highest_perf, nominal_perf; - - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); - - if (highest_perf <= nominal_perf) - return; + amd_pstate_global_params.cpb_supported = !((boost_val >> 25) & 0x1); + amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported; - cpudata->boost_supported = true; - current_pstate_driver->boost_enabled = true; + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -855,6 +835,9 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + /* initialize cpu cores boot state */ + amd_pstate_boost_init(cpudata); + min_freq = amd_get_min_freq(cpudata); max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); @@ -906,7 +889,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1317,6 +1299,9 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + /* initialize cpu cores boot state */ + amd_pstate_boost_init(cpudata); + min_freq = amd_get_min_freq(cpudata); max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); @@ -1367,7 +1352,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index d21838835abd..c6e2a97913de 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -124,4 +124,18 @@ static const char * const amd_pstate_mode_string[] = { [AMD_PSTATE_GUIDED] = "guided", NULL, }; + +/** + * struct amd_pstate_global_params - Global parameters, mostly tunable via sysfs. + * @cpb_boost: Whether or not to use boost CPU P-states. + * @cpb_supported: Whether or not CPU boost P-states are available + * based on the MSR_K7_HWCR bit[25] state + */ +struct amd_pstate_global_params { + bool cpb_boost; + bool cpb_supported; +}; + +extern struct amd_pstate_global_params amd_pstate_global_params; + #endif /* _LINUX_AMD_PSTATE_H */ From patchwork Wed Mar 13 10:04:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Perry Yuan X-Patchwork-Id: 780249 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2082.outbound.protection.outlook.com [40.107.92.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E80093A1A3; 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Wed, 13 Mar 2024 05:05:05 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 3/7] cpufreq: amd-pstate: fix max_perf calculation for amd_get_max_freq() Date: Wed, 13 Mar 2024 18:04:40 +0800 Message-ID: <1da9848e022c49fef0a8cc390feba95c74be531d.1710322310.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066EA:EE_|IA0PR12MB8279:EE_ X-MS-Office365-Filtering-Correlation-Id: fad30bcc-2ef5-4277-cd9a-08dc4345111b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3egCThHhwi0wnPLRxFI3QhtMpmlqqx8bO/foHqe/pWp6+T4MzvT87b+lP1qsXCYPcfPgwNn9uEC/cLwpzkD7zB8EDA6CJjpD3ueLnpA2cxzcYpNLxql62+y/RPja3wSF66Z3gWwIOTfu4keEQJf0yAuZ20JteEqNg4iGCh3B75HphbI39qMNEh3pLCe3gremx/FuAOzCD+6vPBb46AHUXxcLUz8e06Ve63SllRHzr8xvL8uicNJNWxpzC98M/qaLXy2ACcKiHt7ZpudFCy9ShaDXdXaTXqH0EEf+r4OdswNqjsfZwPL83TzXlGuSJzbVc8Fdlvuz0+Ybz+fbZpvMWLnn8qXw/Lbo5P8noUUWI3YR3hq1Taz5w8Rvg0j/S0gJv31h9U5zDb7t8wYmYf3ArloIOOZWTVHD782t42QUxQk/yAJxuAq92T9jryLdXuehugWeVO/AGT7q/cG3Fa24Psw4lCxL7GysqKbMuMh4IwbKJE8v5YzfNUqUKNxjtYaLS43FBVtSmj2WtrcUSvw1HzbKxNY+yvFXM+Bg4vvy4lECH/wUkz4e//qZfXXNUsKCB+O/fiKsUQO7LPSt+yiiRTJlJZv5ITxr+wfDf5PsJ6L3Nd3wQRCttebateLmLiRvlNxEi6pDzSRlbXsBg1XawvKcWstdSNXy9gXui54VTJVqsHUV439sYEyu7AzqYhBdLkv0gI7vynhBwO9nYfAU2cD7ICIccwL+cCQUm+fJRiXZvbs0DKlScdH03ZdyDuUL X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(376005)(36860700004)(82310400014)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:05:09.7044 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fad30bcc-2ef5-4277-cd9a-08dc4345111b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8279 From: Perry Yuan When CPU core Precision Boost state changed, the max frequency will also need to be updated according to the current boost state, if boost is disabled now, the max perf will be limited to nominal perf values. otherwise the max frequency will be showed wrongly. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d54399ebb758..0965fbf660dd 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -632,6 +632,10 @@ static int amd_get_max_freq(struct amd_cpudata *cpudata) nominal_perf = READ_ONCE(cpudata->nominal_perf); max_perf = READ_ONCE(cpudata->highest_perf); + /* when boost is off, the highest perf will be limited to nominal_perf */ + if (!amd_pstate_global_params.cpb_boost) + max_perf = nominal_perf; + boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT, nominal_perf); From patchwork Wed Mar 13 10:04:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Perry Yuan X-Patchwork-Id: 780248 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2054.outbound.protection.outlook.com [40.107.223.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CE093CF68; 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Wed, 13 Mar 2024 05:05:11 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v4 5/7] Documentation: cpufreq: amd-pstate: introduce the new cpu boost control method Date: Wed, 13 Mar 2024 18:04:42 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066EC:EE_|DS7PR12MB6119:EE_ X-MS-Office365-Filtering-Correlation-Id: efefb17c-8f2e-4ad7-83c5-08dc434514fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fd/AAiYFbAC0bazfRsO+xXbbwf6RiSZSxLy6VNyS/RpWbDQSxY89WBwMWG4DZ5OmFVgn6rAeNiByNouU4g6ARBsmC1vatPDClYRLISXEwO1HyBsBWzuAQf9WQHmR2GG+sES9mRDztYqP/fepjFmc1SatHBP2xpxSEhzKOp7SUxXTtjYQgfLNF76d60O/eYqkPwR8Vo7yDq54Z/Qvi8bnIZr+X2bDeky3hTtgUhugsmwsxevWqe+wGerJdmIAFXaU9jRvAR4my2e7WWsdm54dAfAo8FLfnxb8r+2AbA5ALHs4bz66RlMye/XNQQqBZUKiInZRJqG34L1kxtOxWSNR8qMJl72zoRTbBwodzbTSblrOMFyPSCHVy3uvaNGFJxcmrZxf0ypODDCN6UeourTXc88eEIenNLEjNpLH461BIeVutiF/ep1/S74eLdfQ6bbGV6vSu+liMaakDdxnGu39SMMor6jHI50EkH1nkjIg6iFcqF5STZtYVGh2mHfsOQuElOXVEXpN0+ac0/EbQ/5hPLaUuivNxDxIeidNvl1MTtseYYUP+MZM9T0b/p5lk4hRx1IOeGtLV+rz5Z6yTB3SX0T3WKWX4zrS9KV9O3WzXuhp51IRYV8WVtvSj5HMlElw1Q7kpGAKi9qZhY5UzQR/oHAe24CkRnaHxG3nviLPnYU+fHwTNsNC5AXIaGR8tQWNrIIWMD+2XD0YzVKkDxneehxSxru3CvjzalS/Rp3aXh/rwQyxS2n5rJ/cz/D58XU5 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(82310400014)(36860700004)(376005)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:05:16.2102 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efefb17c-8f2e-4ad7-83c5-08dc434514fc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6119 From: Perry Yuan Introduce AMD CPU frequency boosting control sysfs entry which used for switching boost on and boost off. If core performance boost is disabled while a core is in a boosted P-state, the core automatically transitions to the highest performance non-boosted P-state The highest perf and frequency will be limited by the setting value. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1e0d101b020a..82fbd01da658 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -440,6 +440,17 @@ control its functionality at the system level. They are located in the This attribute is read-only to check the state of preferred core set by the kernel parameter. +``cpb_boost`` + Specifies whether core performance boost is requested to be enabled or disabled + If core performance boost is disabled while a core is in a boosted P-state, the + core automatically transitions to the highest performance non-boosted P-state. + AMD Core Performance Boost(CPB) is controlled by this new attribute file which + allow user to change all cores frequency boosting state. It supports both + ``active``, ``passive`` and ``guided`` mode control with below value write to it. + + "0" Disable Core Performance Boosting + "1" Enable Core Performance Boosting + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Wed Mar 13 10:04:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Perry Yuan X-Patchwork-Id: 780247 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94E3F3DBB2; Wed, 13 Mar 2024 10:05:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.40 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710324327; cv=fail; b=dmuiwcSxSHpl+WSRWwD9NLtyzcjSQDprgehcm16UnpeDse8UY+u6/Iq+F3jBdDOQfqIxZ6lZRQoLG5ceMLEmj4+xCgjlsjgPdySu3CdieeMsPCkNthVHxT3AdE9OnrIT0i1Iu4EUZdXil4zGMUToXs2M4kFJd2ZZCR+U9W40fCw= ARC-Message-Signature: i=2; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:05:21.0776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b18f8761-2501-4bcd-36ca-08dc434517e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9348 As the new CPB boost control is enabled, pstate unit test needs to remove legacy `boost_supported` check and start to use new CPB boost control interface `global.cpb_boost`. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate-ut.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c index f04ae67dda37..b3601b0e6dd3 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -226,7 +226,7 @@ static void amd_pstate_ut_check_freq(u32 index) goto skip_test; } - if (cpudata->boost_supported) { + if (amd_pstate_global_params.cpb_boost) { if ((policy->max == cpudata->max_freq) || (policy->max == cpudata->nominal_freq)) amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_PASS;