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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D4.mail.protection.outlook.com (10.167.241.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Mon, 18 Mar 2024 10:11:37 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 18 Mar 2024 05:11:33 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v6 2/6] cpufreq: amd-pstate: initialize new core precision boost state Date: Mon, 18 Mar 2024 18:11:09 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|DM4PR12MB6424:EE_ X-MS-Office365-Filtering-Correlation-Id: c76b125a-38da-4c3e-4125-08dc4733cc11 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2024 10:11:37.1261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c76b125a-38da-4c3e-4125-08dc4733cc11 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6424 From: Perry Yuan Add gloal global_params to represent current CPU Performance Boost(cpb) state for cpu frequency scaling, both active and passive modes all can support CPU cores frequency boosting control which is based on the BIOS setting, while BIOS turn on the "Core Performance Boost", it will allow OS control each core highest perf limitation from OS side. If core performance boost is disabled while a core is in a boosted P-state, the core transitions to the highest performance non-boosted P-state, that is the same as the nominal frequency limit. Reported-by: Artem S. Tashkinov" Cc: Oleksandr Natalenko Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 39 +++++++++++++++++++++++++++--------- include/linux/amd-pstate.h | 13 ++++++++++++ 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 59a2db225d98..81787f83c906 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -68,6 +68,8 @@ static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +struct amd_pstate_global_params amd_pstate_global_params; +EXPORT_SYMBOL_GPL(amd_pstate_global_params); /* * AMD Energy Preference Performance (EPP) @@ -665,18 +667,27 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) return 0; } -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) +static int amd_pstate_boost_init(struct amd_cpudata *cpudata) { - u32 highest_perf, nominal_perf; + u64 boost_val; + int ret; - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); + return ret; + } - if (highest_perf <= nominal_perf) - return; + amd_pstate_global_params.cpb_supported = !(boost_val & MSR_K7_HWCR_CPB_DIS); + + if (amd_pstate_global_params.cpb_supported) { + cpudata->boost_supported = true; + current_pstate_driver->boost_enabled = true; + } - cpudata->boost_supported = true; - current_pstate_driver->boost_enabled = true; + amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported; + + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -900,6 +911,11 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) amd_pstate_init_prefcore(cpudata); + /* initialize cpu cores boot state */ + ret = amd_pstate_boost_init(cpudata); + if (ret) + goto free_cpudata1; + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -956,7 +972,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1363,6 +1378,11 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) amd_pstate_init_prefcore(cpudata); + /* initialize cpu cores boot state */ + ret = amd_pstate_boost_init(cpudata); + if (ret) + goto free_cpudata1; + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1417,7 +1437,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 6b832153a126..c5e41de65f70 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -134,4 +134,17 @@ struct quirk_entry { u32 lowest_freq; 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Mon, 18 Mar 2024 05:11:40 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v6 4/6] cpufreq: amd-pstate: fix the MSR highest perf will be reset issue while cpb boost off Date: Mon, 18 Mar 2024 18:11:11 +0800 Message-ID: <8e04afd3f5f8f9f9aa1a4b7954ad4b8946d11d31.1710754236.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|SJ2PR12MB8135:EE_ X-MS-Office365-Filtering-Correlation-Id: e79d78d6-d818-4d1c-008b-08dc4733d009 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mWZKWT1Ekzh5O508Jma8MRPno2l79nNZ0mqy9AGskdRRIG+q9JaYeYgNsmc/iY8DpAAa42smCm9fQyInKdOj0K/AFC6ykZL09fGnBKsB49Rm7atx74DOuW8M+Oh9wJBLzQjh9CCsgWbCXtencUFJcFI562vBz8Ahl6Ims3bVddlqgsinvZ+Dba8I4wHRiQJKsM1vYk+BahB4FlZLPcPXY7Z8iflfilGmDPhITcBkbCUkrqtSXLgpMN6EB1XwPi2Q0om2huIoRS9iA1GrFnc8B77Lmo3KlvQ9UAS8ro33GY+BYU/On+5FEFjl6NGj3U5c9iocMypMC3TM7Ms5L7yPo4mEZXHSPP+a+H+saVt+WhVc7WLCdKDs7lOUIrzhzlbpP1c+ndMrnbZeqKGUtXBEUdelxC4subWrX7DFuslyEvhU6r1zrcuzrfS8TdtZ7tTIhKhTAfdAVWDdTH+UNIuiEaBwgqiW2sU7JGZr+DRJ9wxlp1Bk4CI6Fn0qPQKhvKg0/A+5ZnGEh7YyrZWoo3IgP98JbXp3zxK7qxACwZMps9gVlvabqRGPLVswMn/Sk87HNjP4E00djRdgpJsuV76C4SPb7VTqxIw/RWy+9JKnTxpqOj0mj0iu4XlqekTyDgQ+TGZmu46o1Yt7W32/vH8FC8yCDfnl4y6HPeuTdulf4SJxueunNwx8WNppUPk7X3baDRLhavTNu8gFCxr2qY7PrJvqLccKFOUiFnaQRM/fQPHUCoNRKlWZedDTc2Vjsoag X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(82310400014)(36860700004)(1800799015)(376005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2024 10:11:43.7829 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e79d78d6-d818-4d1c-008b-08dc4733d009 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8135 From: Perry Yuan Select the min perf to fix the highest perf value while update pstate CPPC request MSR register, here we need to limit the max perf value when CPU boost is disabled in case of that highest perf value in the MSR will be reset to original highest perf value which cause the BOOST control failed. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 4cd2818045c7..513f91611cd5 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -476,6 +476,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags) { u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, @@ -495,6 +496,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~AMD_CPPC_DES_PERF(~0L); value |= AMD_CPPC_DES_PERF(des_perf); + /* limit the max perf when core performance boost feature is disabled */ + if (!amd_pstate_global_params.cpb_boost) + max_perf = min_t(unsigned long, nominal_perf, max_perf); + value &= ~AMD_CPPC_MAX_PERF(~0L); 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D3.mail.protection.outlook.com (10.167.241.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Mon, 18 Mar 2024 10:11:50 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 18 Mar 2024 05:11:47 -0500 From: Perry Yuan To: , , , , , CC: , , , , , , Subject: [PATCH v6 6/6] cpufreq: amd-pstate-ut: support new cpb boost control interface Date: Mon, 18 Mar 2024 18:11:13 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|SN7PR12MB8819:EE_ X-MS-Office365-Filtering-Correlation-Id: e0991a4a-d80e-48fd-e593-08dc4733d3dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Mar 2024 10:11:50.2047 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0991a4a-d80e-48fd-e593-08dc4733d3dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8819 As the new CPB boost control is enabled, pstate unit test needs to remove legacy `boost_supported` check and start to use new CPB boost control interface `amd_pstate_global_params.cpb_boost`. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate-ut.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c index f04ae67dda37..b3601b0e6dd3 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -226,7 +226,7 @@ static void amd_pstate_ut_check_freq(u32 index) goto skip_test; } - if (cpudata->boost_supported) { + if (amd_pstate_global_params.cpb_boost) { if ((policy->max == cpudata->max_freq) || (policy->max == cpudata->nominal_freq)) amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_PASS;