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Tue, 19 Mar 2024 03:44:41 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id a5-20020a5d4d45000000b0033e03a6b1ecsm12029459wru.18.2024.03.19.03.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 03:44:41 -0700 (PDT) From: Neil Armstrong Date: Tue, 19 Mar 2024 11:44:27 +0100 Subject: [PATCH 1/7] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-1-926d7a4ccd80@linaro.org> References: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> In-Reply-To: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. Signed-off-by: Neil Armstrong --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++++++++++++++++--- include/dt-bindings/phy/phy-qcom-qmp.h | 4 ++++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index ba966a78a128..14ac341b1577 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -88,11 +88,11 @@ properties: - description: offset of PCIe 4-lane configuration register - description: offset of configuration bit for this PHY - "#clock-cells": - const: 0 + "#clock-cells": true clock-output-names: - maxItems: 1 + minItems: 1 + maxItems: 2 "#phy-cells": const: 0 @@ -213,6 +213,27 @@ allOf: reset-names: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-qmp-gen4x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy + - qcom,sm8650-qmp-gen4x2-pcie-phy + then: + properties: + clock-output-names: + minItems: 2 + "#clock-cells": + const: 1 + else: + properties: + clock-output-names: + maxItems: 1 + "#clock-cells": + const: 0 + examples: - | #include diff --git a/include/dt-bindings/phy/phy-qcom-qmp.h b/include/dt-bindings/phy/phy-qcom-qmp.h index 4edec4c5b224..6b43ea9e0051 100644 --- a/include/dt-bindings/phy/phy-qcom-qmp.h +++ b/include/dt-bindings/phy/phy-qcom-qmp.h @@ -17,4 +17,8 @@ #define QMP_USB43DP_USB3_PHY 0 #define QMP_USB43DP_DP_PHY 1 +/* QMP PCIE PHYs */ +#define QMP_PCIE_PIPE_CLK 0 +#define QMP_PCIE_PHY_AUX_CLK 1 + #endif /* _DT_BINDINGS_PHY_QMP */ From patchwork Tue Mar 19 10:44:29 2024 Content-Type: text/plain; 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Tue, 19 Mar 2024 03:44:43 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id a5-20020a5d4d45000000b0033e03a6b1ecsm12029459wru.18.2024.03.19.03.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 03:44:42 -0700 (PDT) From: Neil Armstrong Date: Tue, 19 Mar 2024 11:44:29 +0100 Subject: [PATCH 3/7] phy: qcom: qmp-pcie: register second optional PHY AUX clock Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-3-926d7a4ccd80@linaro.org> References: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> In-Reply-To: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, add the code to register it for PHYs configs that sets a aux_clock_rate. In order to get the right clock, add qmp_pcie_clk_hw_get() which uses the newly introduced QMP_PCIE_PIPE_CLK & QMP_PCIE_PHY_AUX_CLK clock IDs and also supports the legacy bindings by returning the PIPE clock. Signed-off-by: Neil Armstrong --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 70 ++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 079b3e306489..2d05226ae200 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -22,6 +22,8 @@ #include #include +#include + #include "phy-qcom-qmp-common.h" #include "phy-qcom-qmp.h" @@ -2389,6 +2391,9 @@ struct qmp_phy_cfg { /* QMP PHY pipe clock interface rate */ unsigned long pipe_clock_rate; + + /* QMP PHY AUX clock interface rate */ + unsigned long aux_clock_rate; }; struct qmp_pcie { @@ -2420,6 +2425,7 @@ struct qmp_pcie { int mode; struct clk_fixed_rate pipe_clk_fixed; + struct clk_fixed_rate aux_clk_fixed; }; static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -3681,6 +3687,62 @@ static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) return devm_clk_hw_register(qmp->dev, &fixed->hw); } +/* + * Register a fixed rate PHY aux clock. + * + * The _phy_aux_clksrc generated by PHY goes to the GCC that gate + * controls it. The _phy_aux_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _phy_aux_clksrc here. The gcc driver takes care + * of assigning this _phy_aux_clksrc as parent to _phy_aux_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) +{ + struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np); + return ret; + } + + init.ops = &clk_fixed_rate_ops; + + fixed->fixed_rate = qmp->cfg->aux_clock_rate; + fixed->hw.init = &init; + + return devm_clk_hw_register(qmp->dev, &fixed->hw); +} + +static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data) +{ + struct qmp_pcie *qmp = data; + + /* Support legacy bindings */ + if (!clkspec->args_count) + return &qmp->pipe_clk_fixed.hw; + + switch (clkspec->args[0]) { + case QMP_PCIE_PIPE_CLK: + return &qmp->pipe_clk_fixed.hw; + case QMP_PCIE_PHY_AUX_CLK: + return &qmp->aux_clk_fixed.hw; + } + + return ERR_PTR(-EINVAL); +} + static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np) { int ret; @@ -3689,6 +3751,14 @@ static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np if (ret) return ret; + if (qmp->cfg->aux_clock_rate) { + ret = phy_aux_clk_register(qmp, np); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(qmp->dev, qmp_pcie_clk_hw_get, qmp); + } + return devm_of_clk_add_hw_provider(qmp->dev, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); } From patchwork Tue Mar 19 10:44:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 781187 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96CBE7EF14 for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy provided QMP_PCIE_PHY_AUX_CLK. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b86be34a912b..32361af98936 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,8 +754,8 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <0>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1988,8 +1988,8 @@ pcie1_phy: phy@1c0e000 { "rchng", "pipe"; - clock-output-names = "pcie_1_pipe_clk"; - #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; + #clock-cells = <1>; #phy-cells = <0>; From patchwork Tue Mar 19 10:44:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 781186 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC0D97F7C9 for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy provided QMP_PCIE_PHY_AUX_CLK. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 ++++--------- 3 files changed, 4 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 4450273f9667..95d0c2baef2b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -645,10 +645,6 @@ &mdss_mdp { status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..c6e907e40af1 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -831,10 +831,6 @@ &mdss_mdp { status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index ba72d8f38420..6e4362bbcc3a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -60,11 +60,6 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-mult = <1>; clock-div = <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; }; cpus { @@ -758,8 +753,8 @@ gcc: clock-controller@100000 { <&bi_tcxo_ao_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -2449,8 +2444,8 @@ pcie1_phy: phy@1c0e000 { power-domains = <&gcc PCIE_1_PHY_GDSC>; - #clock-cells = <0>; - clock-output-names = "pcie1_pipe_clk"; + #clock-cells = <1>; + clock-output-names = "pcie1_pipe_clk", "pcie1_phy_aux_clk"; #phy-cells = <0>;