From patchwork Sun Mar 24 18:50:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 782256 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03039D502 for ; Sun, 24 Mar 2024 18:50:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711306241; cv=none; b=L78y3kI9EYXSNKz1b2DGw0Vvt3AB642seg5qZhLa1apmoAki2R1cFZOUIrxjRmkDfPhUyPTJKkGAIPiZsyBhugO7oNFsI3CXAwEtBjRC1bgC3KD+KANcHNPWpQ1+WcXGI0q+u0ghL08e/OSpF/mzbo3hExXdcsoflqFddwFu2II= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711306241; c=relaxed/simple; bh=UEn883fEvn74EKDrMBY5HRtTZ852wPrXNTB+0TMl9N8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tP+MGv935akqVZsRn+ehdRPl9tNyN4+RO6/flT5JSTQ0rlhOgZp+Yv64gjuK5zafZ6gWnBbwnMQrEgU/arsh6Q37pRkNZ2IOzGZ1C+z35NoYijYRQCu6Uc0w05L7T2Il6Z8nyFIbFfp9+QbJIIRjfjujYCDtefUsGK1sb+kdy9M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=pwRKFTw6; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="pwRKFTw6" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-a474c4faf5eso79309866b.2 for ; Sun, 24 Mar 2024 11:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711306238; x=1711911038; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YXniBx4zGce2I+zUvQZeh9F9TJPf5+YSFwkB/zgLcpo=; b=pwRKFTw6OdAohH71ob1uq/UqdOJvYF52hhVVkrZnWlQj3sj5+LTQnV5sAR/ljLGFEB 7zExttgTxbWreEslBKzqwR4MQAtiy7TYzlK0H3+ct1HcD9tz1zOMPuSEusqXGCWsCWJv 7Yq0WdWU9T0FzKi00sK3d2na44vWWXZbnQZaR3Sf2eaDDlHgN7aq9ujLLnesIuEQ9bd9 uzhA5KEJ6U2T1Z/2Yc+pc+nCI/IHM+Pc7T+PEBqT8p5OjhE+y//sQ7ydMVLpWwt+ix+G 8LwD9csIvw1X8BS8etqYvaTncGgkeCRl9aC8tcEcPRnvDg5clokKCg/SP1T5as6KYvMV 9U9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711306238; x=1711911038; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YXniBx4zGce2I+zUvQZeh9F9TJPf5+YSFwkB/zgLcpo=; b=EoH9PM1/xaaor/77BDWyZtClHPnmXTIgLKGtmtCh8J1PrEJ2QRUkoJsEH5WHIcbud0 WugXA8Q86KS9FKCnMSuUuIRMAS/x0Yyd2w4ZKq8DrRzWD2b/cnVOpnr+dGFHfTo/SJLh /avOEpaYmLorcTGsuvj1FvgduJ4YQxZZR/NqYrSKU+35vS566+jLMclcZxhMDaJq8P/H ycLb8+15tTq8gswM6qX8qoFIgVQ4LcpHyAGRkVG31tZl5FohUyJxTawSpajU/RCadkNF mfxqV+iMX2Bd+E0iDWTloIhGbbn052trNijKYY2sX/x/SWaN0ECmdYw2H5CjHVryQzk6 le6Q== X-Forwarded-Encrypted: i=1; AJvYcCUG//HCZnQhzbRBG3p0SfoQh59b4vdeJCr/NBJiiDXlP7FoCtNDr/hnrX90xr1piecFVKpD5FHi03CqmeaaNqypzeuR4hyjpzP1qc+Dng== X-Gm-Message-State: AOJu0YyUNbgwTa7FYDvUhwc/l/W4hFSJGbNy6RuQRvRRjjwDm/4y43C5 74r/z62mseLlukjcK4xLLBUOnrlUD1jUupRLhH0sN+Xpdg8LJUtlsSc6/2Af1zA= X-Google-Smtp-Source: AGHT+IFpaLpaD9DR9dWYOMiX2pj9Pu71KXZWIlpnsJOHVrOCZWTzkvOiza0oO/K+MJBGHCvg3UERWw== X-Received: by 2002:a17:906:b243:b0:a47:1d01:bb8f with SMTP id ce3-20020a170906b24300b00a471d01bb8fmr2788482ejb.31.1711306237970; Sun, 24 Mar 2024 11:50:37 -0700 (PDT) Received: from [127.0.1.1] ([79.114.172.194]) by smtp.gmail.com with ESMTPSA id kn5-20020a170906aa4500b00a46524d06afsm2188136ejb.8.2024.03.24.11.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 11:50:37 -0700 (PDT) From: Abel Vesa Date: Sun, 24 Mar 2024 20:50:17 +0200 Subject: [PATCH RESEND v5 1/2] phy: Add Embedded DisplayPort and DisplayPort submodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240324-x1e80100-phy-edp-compatible-refactor-v5-1-a0db5f3150bc@linaro.org> References: <20240324-x1e80100-phy-edp-compatible-refactor-v5-0-a0db5f3150bc@linaro.org> In-Reply-To: <20240324-x1e80100-phy-edp-compatible-refactor-v5-0-a0db5f3150bc@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Johan Hovold Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=715; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=UEn883fEvn74EKDrMBY5HRtTZ852wPrXNTB+0TMl9N8=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBmAHX4iS0d2pQK1abiEyUGqEBZHZJ2E94lwhHzy SV+OHdxdqWJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZgB1+AAKCRAbX0TJAJUV VgDTD/9P5eObpOH3NwGOJBXgjEhwh08WrSARxONu7d4ai2ARgbmiOc4l2h4FgMxpr5QtIxwb1D1 BJEJHZl0KBpFK/5HNn3ZZQtgGGcpp1/LzYNvIB6P5TgRR7yxabH9LzeB5pBXaK48V/t7+UM8B9S PNhuJ/W6PYW/Nj0so7WCfKG/7XAHxxO6M2VcJ5rMyes9mTdzoeBXeMwguHamavAJ/0+UNPqPyBa OLD1Oe64pW/duvMqhoF4s2PYVvKBDUVMUMfPvQ8+yhizbdNM7fYaDxrI89yRO4F7QjSNMSxQLo+ Hq/orrnfowW7rQK7EFTGVYRuxLiQnDwj221uHLG6sDHLnAnNdH7h3GPJf+tWkAyMSYNHmOCW3TC FSTSs65vOz7gvtDKWqdFkpoKC1v0/X824VcWGEDx6bs2oPdDm609wVAWN/1RbMyP84uhRH93clP E+c4/DciD0NHcQtBW0KgdlcKZtLdoDbVT/GrhTaV53VWHAasH+ffqwWtlbW7qQyNvYw2ndy/9Qo 1sOkrPQ0b+ZOb/s62BouBwGjDA01UyKE8qXhbl9pEJmzCFjI7pkjftCgKPMZgwDVZNqd+a5ot6d MV1odRIF6p7D2V0qMyTt+YEoQMdVH5OU0JQ8khnO5aW2nyH1kVPWmEiZMqx1Wg8JEwaFB7l6yyr y83z4hvCjBDyKZg== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE In some cases, a DP PHY needs to be configured to work in eDP mode. So add submodes for both DP and eDP so they can be used by the controllers for specifying the mode the PHY should be configured in. Signed-off-by: Abel Vesa --- include/linux/phy/phy-dp.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h index 18cad23642cd..9cce5766bc0b 100644 --- a/include/linux/phy/phy-dp.h +++ b/include/linux/phy/phy-dp.h @@ -8,6 +8,9 @@ #include +#define PHY_SUBMODE_DP 0 +#define PHY_SUBMODE_EDP 1 + /** * struct phy_configure_opts_dp - DisplayPort PHY configuration set * From patchwork Sun Mar 24 18:50:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 782797 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56608DDA3 for ; Sun, 24 Mar 2024 18:50:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711306243; cv=none; b=eC1khCwAZpdMaaOkkWAfmjJ3eeif6grYb4rZ68mLQACu77yiRDmAUm+yyKlXlG30Ty/POXr0s7C8h1ND2hpYOca9PgyLQksyRBToWpuORemU2KfB6KcDTn7B7y+TL8b0SpfSorZ2dWe7+/3ml5vNmdHpNxGcfk4fhbXwqfFZXIc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711306243; c=relaxed/simple; bh=x/sM1oxfZUCPHoOMyY6oHfzmE1AvTxeArqfwZBquDmQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m5NoR7rf+fr5KjlXm301ewBkMLobkHCnE5Jx+VklhIrAA7prCKf+SJPV3n6S8kS0Tjd7Cq5oFXar02axH9Q7GkS5eAxW+KPV++ehRh1D7lXE5ktdVLWFi4osRpthPE+hFkUSguqrjdctBIzN2EkIkD9IOkYlc9V6TelcYYrmDEE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=jK7CNAoJ; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jK7CNAoJ" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a46ba938de0so497497866b.3 for ; Sun, 24 Mar 2024 11:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711306239; x=1711911039; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PGRRI7sgcjcdwbFUQNyGAZlpRlxjS+UkjJwbRkuNFeY=; b=jK7CNAoJOp5MLAPsBc+NeZHhxMxxkppSx8M05bOJkdhYVNlWOChYGA/9oZOECsZyZo m1qodtpeidRxZk42fabGY4jphFVWgLlor5BkWTu/cpOMbuM7IX+wyzQj73uamyv5xLgZ 7nBK8anGqqoTZ1lKrIXoERAHYQAjl0Oejn+IZ76FlVEQfq3G/OAD38QtAPsEG7N05bKP JXdRU3SKbgdKRLsckYMJ+mKKt+KNjjZ+QZiIjAMO3+CWm9EdbNfH74ayEtFY5uNWz9K6 MNQa4FnnNVFUsQZaueigLYfGvbk3j/jjU8qHTcMX2oRXVen9Xwxl0L9egKAnmj4j1dwN 01gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711306239; x=1711911039; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PGRRI7sgcjcdwbFUQNyGAZlpRlxjS+UkjJwbRkuNFeY=; b=JB+rQt0LVaGDgHFrWoDOyqe3af7Tehs7ozm+1en7CwzUetSoialOmHsne94G45cFaR 2LpGTHZ7vIWFLJhGYDJG5ii4JWUayiUeuZx2N55NqvDWuetNwgZ11+Y6kvESK3ismAVX Lr9QUNfgZeScDGZy99vCw+3GkM7WTslyTmZc+1xTtq1u65yj4BvS6iSMV2tkgnPqyIdZ Xz7g4kIF6YIPscgyk1OOUQKpeIITmkTKfGeuGUsimydRz3Shy3ArQiXklYFJwGnrofMD SlpAr/E+BTCA4L9z5+15p8Oth3Y9Str3fcANqx6rBuNWnrjBZCf9YcO0zKhVM5t47/jR e25g== X-Forwarded-Encrypted: i=1; AJvYcCXBF1letOQSqaPRsBpbtsetnRCkdh4U6KSKIfdAPxrHGfsalkZLs9LCOuMx++VVwXDsf2Fz1PsCuhcqNpVI1KRJEDY++nTuoVVPBmVBsQ== X-Gm-Message-State: AOJu0Yw+UK2TgutgcWRTdLR/uM/D3FcO0ylU5s+PdBvWasbQjUE9rlhA FwzSmfQpD0EvfqgF17jdj4sh6aQ4IkPIMdnGu+l/gIHaEGwG4NjOnMpTy4tZQYE= X-Google-Smtp-Source: AGHT+IHENUP27u6sa62ZGc7R/U3q3t+RoXnS6nZuB469wkPjZZSiKMv28mYur6G6Nspvxntqm2vzww== X-Received: by 2002:a17:906:593:b0:a46:c510:261e with SMTP id 19-20020a170906059300b00a46c510261emr3353082ejn.49.1711306239357; Sun, 24 Mar 2024 11:50:39 -0700 (PDT) Received: from [127.0.1.1] ([79.114.172.194]) by smtp.gmail.com with ESMTPSA id kn5-20020a170906aa4500b00a46524d06afsm2188136ejb.8.2024.03.24.11.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 11:50:38 -0700 (PDT) From: Abel Vesa Date: Sun, 24 Mar 2024 20:50:18 +0200 Subject: [PATCH RESEND v5 2/2] phy: qcom: edp: Add set_mode op for configuring eDP/DP submode Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240324-x1e80100-phy-edp-compatible-refactor-v5-2-a0db5f3150bc@linaro.org> References: <20240324-x1e80100-phy-edp-compatible-refactor-v5-0-a0db5f3150bc@linaro.org> In-Reply-To: <20240324-x1e80100-phy-edp-compatible-refactor-v5-0-a0db5f3150bc@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Johan Hovold Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7178; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=x/sM1oxfZUCPHoOMyY6oHfzmE1AvTxeArqfwZBquDmQ=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBmAHX61R4tDBW5Qjfmg/uK7sPX821geyy9RlYGB 38jOeifwlGJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCZgB1+gAKCRAbX0TJAJUV VuFkD/4yic+2C+wp+RSoc2Dg5xuN6t94FcQe1zHPQ0lBPAF+rf6wrKfmRDv/0yT7IcRrfFkRN1i dOvNq9tso6UqYVnro+T8SGWNMIVHpXk36E+0TN7LQYkBUOINYHkmtyhadFdwMVjidWP2YLtMrht BPAVZJ4GPyHxjBg3Jn+lXzVWw10z87Zi+LmZtuYtfexeT0xnssbdMDCLyjPoooBtwKCTTC515aW GEMPIqXvgc2mpVjHFAg1eS9DZWHakRzcl9QbeygSXZWBzuFt145UZNGHQg9eBj8Kpo78WC8o4MD CDRCkFfX86lZAX54TV5579q9o2hHYhA4Wx5qJ2aLQOeJA3TswK3sKRuPrJU9+oB6OGMBHid5bbD hcZeAEPes+R77RETXxp6uLaLtR7sdX4DMZtq3TOMmIcqAdolG0emOWIznrJ7WXAelDDMKEEqV+P p5WmrnII6OzK+tloQ0jX/BdDkEhZ6ucQSLEAwhgi3LVjX6IGNC382BW7a8Itu516lZt4ajaP4PM bpZqaIwaOOjX9YRtDu8to07NmPCPsIP8LyMKYxGxs91Ae9POMk5w8zRmsplZQhJxqybgBU0kDbQ VtWK9o7VSy8nq2bacpl7Xbx71OD7w/vkuSyNijrlfk+pz7bshOyB6hDLruMUW1x/lWjdsMvI73N WVYZ4R9SKW8un9Q== X-Developer-Key: i=abel.vesa@linaro.org; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Future platforms should not use different compatibles to differentiate between eDP and DP mode. Instead, they should use a single compatible as the IP block is the same. It will be the job of the controller to set the submode of the PHY accordingly. The existing platforms will remain with separate compatibles for each mode. Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 76 +++++++++++++++++++++++++++---------- 1 file changed, 56 insertions(+), 20 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index 9818d994c68b..621d0453bf76 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -69,19 +70,21 @@ #define TXn_TRAN_DRVR_EMP_EN 0x0078 -struct qcom_edp_cfg { - bool is_dp; - - /* DP PHY swing and pre_emphasis tables */ +struct qcom_edp_swing_pre_emph_cfg { const u8 (*swing_hbr_rbr)[4][4]; const u8 (*swing_hbr3_hbr2)[4][4]; const u8 (*pre_emphasis_hbr_rbr)[4][4]; const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; }; +struct qcom_edp_phy_cfg { + bool is_edp; + const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; +}; + struct qcom_edp { struct device *dev; - const struct qcom_edp_cfg *cfg; + const struct qcom_edp_phy_cfg *cfg; struct phy *phy; @@ -97,6 +100,8 @@ struct qcom_edp { struct clk_bulk_data clks[2]; struct regulator_bulk_data supplies[2]; + + bool is_edp; }; static const u8 dp_swing_hbr_rbr[4][4] = { @@ -127,8 +132,7 @@ static const u8 dp_pre_emp_hbr2_hbr3[4][4] = { { 0x04, 0xff, 0xff, 0xff } }; -static const struct qcom_edp_cfg dp_phy_cfg = { - .is_dp = true, +static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg = { .swing_hbr_rbr = &dp_swing_hbr_rbr, .swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3, .pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr, @@ -163,18 +167,28 @@ static const u8 edp_pre_emp_hbr2_hbr3[4][4] = { { 0x00, 0xff, 0xff, 0xff } }; -static const struct qcom_edp_cfg edp_phy_cfg = { - .is_dp = false, +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = { .swing_hbr_rbr = &edp_swing_hbr_rbr, .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3, .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr, .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3, }; +static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = { +}; + +static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = { + .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, +}; + +static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = { + .is_edp = true, + .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp = phy_get_drvdata(phy); - const struct qcom_edp_cfg *cfg = edp->cfg; int ret; u8 cfg8; @@ -201,7 +215,12 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); - if (cfg && cfg->is_dp) + /* + * TODO: Re-work the conditions around setting the cfg8 value + * when more information becomes available about why this is + * even needed. + */ + if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) cfg8 = 0xb7; else cfg8 = 0x37; @@ -235,7 +254,7 @@ static int qcom_edp_phy_init(struct phy *phy) static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts) { - const struct qcom_edp_cfg *cfg = edp->cfg; + const struct qcom_edp_swing_pre_emph_cfg *cfg = edp->cfg->swing_pre_emph_cfg; unsigned int v_level = 0; unsigned int p_level = 0; u8 ldo_config; @@ -246,6 +265,9 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur if (!cfg) return 0; + if (edp->is_edp) + cfg = &edp_phy_swing_pre_emph_cfg; + for (i = 0; i < dp_opts->lanes; i++) { v_level = max(v_level, dp_opts->voltage[i]); p_level = max(p_level, dp_opts->pre[i]); @@ -262,7 +284,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur if (swing == 0xff || emph == 0xff) return -EINVAL; - ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; + ldo_config = edp->is_edp ? 0x0 : 0x1; writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(swing, edp->tx0 + TXn_TX_DRV_LVL); @@ -448,10 +470,9 @@ static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp = phy_get_drvdata(phy); - const struct qcom_edp_cfg *cfg = edp->cfg; u32 bias0_en, drvr0_en, bias1_en, drvr1_en; unsigned long pixel_freq; - u8 ldo_config; + u8 ldo_config = 0x0; int timeout; int ret; u32 val; @@ -469,7 +490,8 @@ static int qcom_edp_phy_power_on(struct phy *phy) return timeout; - ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0; + if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) + ldo_config = 0x1; writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); @@ -590,6 +612,18 @@ static int qcom_edp_phy_power_off(struct phy *phy) return 0; } +static int qcom_edp_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct qcom_edp *edp = phy_get_drvdata(phy); + + if (mode != PHY_MODE_DP) + return -EINVAL; + + edp->is_edp = submode == PHY_SUBMODE_EDP; + + return 0; +} + static int qcom_edp_phy_exit(struct phy *phy) { struct qcom_edp *edp = phy_get_drvdata(phy); @@ -605,6 +639,7 @@ static const struct phy_ops qcom_edp_ops = { .configure = qcom_edp_phy_configure, .power_on = qcom_edp_phy_power_on, .power_off = qcom_edp_phy_power_off, + .set_mode = qcom_edp_phy_set_mode, .exit = qcom_edp_phy_exit, .owner = THIS_MODULE, }; @@ -782,6 +817,7 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) edp->dev = dev; edp->cfg = of_device_get_match_data(&pdev->dev); + edp->is_edp = edp->cfg->is_edp; edp->edp = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(edp->edp)) @@ -840,10 +876,10 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) } static const struct of_device_id qcom_edp_phy_match_table[] = { - { .compatible = "qcom,sc7280-edp-phy" }, - { .compatible = "qcom,sc8180x-edp-phy" }, - { .compatible = "qcom,sc8280xp-dp-phy", .data = &dp_phy_cfg }, - { .compatible = "qcom,sc8280xp-edp-phy", .data = &edp_phy_cfg }, + { .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, }, + { .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, }, + { .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, }, + { .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, }, { } }; MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table);