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([223.178.208.62]) by smtp.gmail.com with ESMTPSA id k9-20020a170902c40900b001e2c0b77b53sm1055959plk.255.2024.04.05.02.08.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 02:08:29 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v3 1/6] qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default Date: Fri, 5 Apr 2024 14:37:37 +0530 Message-Id: <20240405090742.4148304-2-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240405090742.4148304-1-sumit.garg@linaro.org> References: <20240405090742.4148304-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is loaded as a first stage bootloader. It leads to secondary CPUs bringup failure and later causing the Linux kernel to freeze. So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's actually required. Fixes: 059d526af312 ("mach-snapdragon: generalise board support") Reviewed-by: Caleb Connolly Signed-off-by: Sumit Garg --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4cdf08dd695..08ae7e51a6d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1088,7 +1088,7 @@ config ARCH_SNAPDRAGON select BOARD_LATE_INIT select OF_BOARD select SAVE_PREV_BL_FDT_ADDR - select LINUX_KERNEL_IMAGE_HEADER + select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK imply CMD_DM config ARCH_SOCFPGA From patchwork Fri Apr 5 09:07:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 786206 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1101:b0:343:f27d:c44e with SMTP id z1csp67499wrw; Fri, 5 Apr 2024 02:08:44 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVxap7vGrZOFhETzF1ZXUIya07msBFaQYmgzOwp3YPU+lyBTFxN5tw7ejcEJyDzkFzv36Qm6tIhqnjJ/eC57vMW X-Google-Smtp-Source: AGHT+IEWZbwpeoNEjtEK/sUSDOQwSAcDZUvVZQJlzTYGdn6+UJZpoc6Hoee8BwCrH2zsvuJ4eLpP X-Received: by 2002:a17:906:6a1a:b0:a4e:4278:8a01 with SMTP id qw26-20020a1709066a1a00b00a4e42788a01mr768687ejc.11.1712308123996; Fri, 05 Apr 2024 02:08:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712308123; cv=none; d=google.com; s=arc-20160816; b=LSuFmQNV+E4zSaOWpaSA2/Kpn9mRP0OXbA2gi/IxYmMMhmR/GZTT4rP6hJAYnYzssS aJGGmDSF++a71yL39WKoX1mqV9BpmP6JMU+et3iA7IKzWCFRO7e9GCJC8vm+oOVcTql1 7jKqxviswrmPZOjJF0TRNqDIoNUTHcjBp3gJ1WxfnoO4osdBQl/O8t7NzWtiQby0q46i FIDihsrM+NKD2BEbcV4lEabInZ9lpq1ncl2U501uznStElT3VjRN3Z1/5MV1NLIcr1aE m9/pf523VW6OqgFGLsYT63l1yCm8MDmDuY6Kl1cmIjz9kGEmWzNeTwyygBFH9bGm9Uz9 7/dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=W5mdOOExPAXMAEe+Bx+qErpp9/cMTqsnWS0nVCzdeW8=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=nfTCa5fWdVdn0OLY9WBD2Fhk75McNVYQ9bNuE4thXM+XQO9G2CpplzD/vRqz0kq371 I9A3jc0PAqf5OWV4Ii+jUknFVPqpZu+v1cAacjc5B7FuMojUSnnh47A4SwJ6Rm2dUGbF kJjNnGSRfOOiyyHK5xGbiq01lyieYWvSqPpwH+CWQEgxT4rypRgu7Mhs4skxUtT6Fagk 7qtdtdAv1m7CerVJEVaeo9W74UEi42MF0GiBoFeDAZt96fo8bBL8Yyk3soOcooQJXOkt LU0X5MazOuG3qiu7hrP9tIV47ZzGnUqQIcKcwl+n9bj7fkkrgjLv93eRnEm7ZIUZVdyj bI7g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CrJEkROb; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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([223.178.208.62]) by smtp.gmail.com with ESMTPSA id k9-20020a170902c40900b001e2c0b77b53sm1055959plk.255.2024.04.05.02.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 02:08:34 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v3 2/6] apq8016: Add support for UART1 clocks and pinmux Date: Fri, 5 Apr 2024 14:37:38 +0530 Message-Id: <20240405090742.4148304-3-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240405090742.4148304-1-sumit.garg@linaro.org> References: <20240405090742.4148304-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Signed-off-by: Sumit Garg Reviewed-by: Caleb Connolly --- drivers/clk/qcom/clock-apq8016.c | 38 ++++++++++++++++++-------- drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 + drivers/serial/serial_msm.c | 11 ++++++-- 3 files changed, 35 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 5a5868169c8..9556b94774a 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -31,7 +31,8 @@ #define BLSP1_AHB_CBCR 0x1008 /* Uart clock control registers */ -#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART1_APPS_CBCR (0x203C) +#define BLSP1_UART1_APPS_CMD_RCGR (0x2044) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) @@ -52,7 +53,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = { }; /* SDHCI */ -static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) +static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) { int div = 15; /* 100MHz default */ @@ -70,20 +71,35 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) } /* UART: 115200 */ -int apq8016_clk_init_uart(phys_addr_t base) +int apq8016_clk_init_uart(phys_addr_t base, unsigned long id) { + u32 cmd_rcgr, apps_cbcr; + + switch (id) { + case GCC_BLSP1_UART1_APPS_CLK: + cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR; + apps_cbcr = BLSP1_UART1_APPS_CBCR; + break; + case GCC_BLSP1_UART2_APPS_CLK: + cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR; + apps_cbcr = BLSP1_UART2_APPS_CBCR; + break; + default: + return 0; + } + /* Enable AHB clock */ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk); /* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625, - CFG_CLK_SRC_GPLL0, 16); + clk_rcg_set_rate_mnd(base, cmd_rcgr, 1, 144, 15625, CFG_CLK_SRC_GPLL0, + 16); /* Vote for gpll0 clock */ clk_enable_gpll0(base, &gpll0_vote_clk); /* Enable core clk */ - clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR); + clk_enable_cbc(base + apps_cbcr); return 0; } @@ -94,14 +110,12 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_SDCC1_APPS_CLK: /* SDC1 */ - return clk_init_sdc(priv, 0, rate); - break; + return apq8016_clk_init_sdc(priv, 0, rate); case GCC_SDCC2_APPS_CLK: /* SDC2 */ - return clk_init_sdc(priv, 1, rate); - break; + return apq8016_clk_init_sdc(priv, 1, rate); + case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */ case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return apq8016_clk_init_uart(priv->base); - break; + return apq8016_clk_init_uart(priv->base, clk->id); default: return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index a9a00f4b081..1ee8b7db1a2 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = { }; static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart1", 2}, {"blsp_uart2", 2}, }; diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index ac4280c6c4c..4de10e75191 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -248,12 +248,17 @@ static struct msm_serial_data init_serial_data = { #include /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ -//int apq8016_clk_init_uart(phys_addr_t gcc_base); +//int apq8016_clk_init_uart(phys_addr_t gcc_base, unsigned long id); static inline void _debug_uart_init(void) { - /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ - //apq8016_clk_init_uart(0x1800000); + /* + * Uncomment to turn on UART clocks when debugging U-Boot as aboot + * on MSM8916. Supported debug UART clock IDs: + * - db410c: GCC_BLSP1_UART2_APPS_CLK + * - HMIBSC: GCC_BLSP1_UART1_APPS_CLK + */ + //apq8016_clk_init_uart(0x1800000, ); uart_dm_init(&init_serial_data); } From patchwork Fri Apr 5 09:07:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 786207 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1101:b0:343:f27d:c44e with SMTP id z1csp67564wrw; Fri, 5 Apr 2024 02:08:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUHk/gXxdWRD7upCI/FXbX3I26KlSEqPpJsdylmj7vI/6t0ceHgbZ6jb3BrZw6zb3XMK8kqlyrGWFjJACQcj0kc X-Google-Smtp-Source: AGHT+IGB25gxxb/BITyjA0+Bo8YTQK1lGMUmlhoLIIITIHULwbPWmWo3SHJVoH6qtrk6wGsfbJMd X-Received: by 2002:a17:906:11da:b0:a4e:146c:ff09 with SMTP id o26-20020a17090611da00b00a4e146cff09mr616493eja.7.1712308135424; Fri, 05 Apr 2024 02:08:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712308135; cv=none; d=google.com; s=arc-20160816; b=O/HUFDltoWoNVzEU4wT5nYzM8eSaHuEZentCetUVnVXktITSU54RKIkioBS0Wl416F QQFlqFrRtriOWrgPqU/0+6a+l1JEI6mc3heUfl/gEGqjHnPf9UzPzWIPZIZwv4DecIHz foVAA/SD/1rgynSwNCuuLZiAKWl8KFFuG/IfIpdWc/s426pkxYoEEmzhLBuPsi3zCJ3e l1tWh0Kafw7nJ9/VZEv0H2INqjNoDUcFjnUchDfB7KeLaADfayk9lQi/kmmdcxmawarL FGjVEHNhkHJN+qhAU7uKEVi1/pSpDHhoMRcVfpBB1d7QRMU53aWsRAspRvmbkFtkgHU6 caKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gJGPMVDQs/+70lwOsKxB+VSM+QwlHnt8HABufnH5vsU=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=lodzKDjHM0d+g0kQs7g/UlzPjlhYgfcdwsA+kuq0y81TvUoEAwTuePbZuX6EUBMHdb PuA2epMwa1T1w8tep3ozRTVqEB7zBFl9lkLujuv2FLKXb3OjRX4EW8LI0M4eFtcIlcGN cZf9EoQ7oEgzZ6Y2pkvZRbALjrfZyj03LAQzmwjwndjIVI5Cp5yQI9+NTNQtOGHbRUxj AtKAruV+7NfjPiiurqQamzDkTS0i0KPmztowL1ObtE3Nv8IGOVfzpShNA3bWeTbzUjaz VbYCGZ3TZM7VOhxxgS6D2LsHMDuQjSCVfVhupP50mqoUGHJu1WRzLAzhqq4IF9oVTtAh +g6Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WRqq6OCK; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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([223.178.208.62]) by smtp.gmail.com with ESMTPSA id k9-20020a170902c40900b001e2c0b77b53sm1055959plk.255.2024.04.05.02.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 02:08:39 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v3 3/6] serial_msm: Enable RS232 flow control Date: Fri, 5 Apr 2024 14:37:39 +0530 Message-Id: <20240405090742.4148304-4-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240405090742.4148304-1-sumit.garg@linaro.org> References: <20240405090742.4148304-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present. Reviewed-by: Caleb Connolly Signed-off-by: Sumit Garg --- drivers/serial/serial_msm.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 4de10e75191..3142ecf7362 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -53,10 +53,11 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ -#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC -#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 -#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 -#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define MSM_UART_MR1_RX_RDY_CTL BIT(7) DECLARE_GLOBAL_DATA_PTR; @@ -182,7 +183,9 @@ static void uart_dm_init(struct msm_serial_data *priv) mdelay(5); writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); - writel(0x0, priv->base + UARTDM_MR1); + + /* Enable RS232 flow control to support RS232 db9 connector */ + writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1); writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); From patchwork Fri Apr 5 09:07:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 786208 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1101:b0:343:f27d:c44e with SMTP id z1csp67618wrw; Fri, 5 Apr 2024 02:09:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV86kXz9DKaka7PaPhjnwR9RoKrVxsdWO5W8oQkwZ+bTDDkzDL/uQsfTbRUQfFPhiOnPkUGfdObFmDnHGmvVF06 X-Google-Smtp-Source: AGHT+IH6yplQiw3jzvRApJCqitpbzM9NxqEtjV1zhvs588UaFTDB8zVa9xkVQzIDSg5XhyVzRobd X-Received: by 2002:a17:906:4550:b0:a4d:f553:c652 with SMTP id s16-20020a170906455000b00a4df553c652mr527413ejq.75.1712308146935; Fri, 05 Apr 2024 02:09:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712308146; cv=none; d=google.com; s=arc-20160816; b=V50l7eaPqex7rVBO7k4XcbYlyuJAUXBDr2fMMnc9VuTUGfi7cJ0ulnLzQI3ohZSc3R ZI71/tz3dhxJcJwlLtqv60vCcYUYwFuDXttXXU8E5Fqk7xcvCN/0btya0+OfCPiWU8KP 4yp2Cuhf3lSifW8sfSIP/+xQ50XYsBj9dmuNpp0IlpEqF0z09BqZE6tYc0+NwlMXQuKL /LRcBb1vvLwA8cjUhVH1ks2h/CXDfyuZGch/j/me1sA7cyONbm2UctmIKWwa9gTQrxLV vOm9xw8Dgdj/VCRK3SJhPfNRTHra0sIWunudEvG1cqHm9rz13CgD+BxXm3+TW6cQYKWE Bs1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OQQFm53Y6noFLmaH27wGfZfjy164/8YCVf5iflGTt5w=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=RiYPYD+TJ8l+eJUJnDhYZbaNVdVhPw880Ek/2mwo5vVeoCgfpXHqFMgBXW7beCoHIb mUzKLmsvhWNBPde/0a7kq8RCOihGySaY2arpMZSF0wlORPlBfU2yGP/47rkfpBQ0Q+Ro /QWGP9/okyIILiHgp4EMlBAaWGJxlHEjc+qgroGFQbISlHheHIc/OMvEdiRYV5CFpp5X ja9eDuuZC4VkQgqhhg51zZ0RponTZd4xfQYaCugSdqF83ogqY96ORZVeP3SbhMwnnavm TwQr7Ec6bdrAjTy3sve7zuPExLUtYfgjeR5c55rdMUqKVq3ubkJRlzfxHCO5wvfnX8+x YqSA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sffkqgmh; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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([223.178.208.62]) by smtp.gmail.com with ESMTPSA id k9-20020a170902c40900b001e2c0b77b53sm1055959plk.255.2024.04.05.02.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 02:08:44 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v3 4/6] pinctrl: qcom: Add support for driving GPIO pins output Date: Fri, 5 Apr 2024 14:37:40 +0530 Message-Id: <20240405090742.4148304-5-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240405090742.4148304-1-sumit.garg@linaro.org> References: <20240405090742.4148304-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for driving the GPIO pins as output low or high. Signed-off-by: Sumit Garg --- drivers/pinctrl/qcom/pinctrl-qcom.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 909e566acf5..e68971b37ff 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -29,15 +29,24 @@ struct msm_pinctrl_priv { #define GPIO_CONFIG_REG(priv, x) \ (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x)) -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9) +#define GPIO_IN_OUT_REG(priv, x) \ + (GPIO_CONFIG_REG(priv, x) + 0x4) + +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_OUTPUT_MASK BIT(1) +#define TLMM_GPIO_OE_MASK BIT(9) + +/* GPIO register shifts. */ +#define GPIO_OUT_SHIFT 1 static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, }; static int msm_get_functions_count(struct udevice *dev) @@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0; clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2); + TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2); return 0; } @@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_GPIO_PULL_MASK, argument); break; + case PIN_CONFIG_OUTPUT: + writel(argument << GPIO_OUT_SHIFT, + priv->base + GPIO_IN_OUT_REG(priv, pin_selector)); + setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), + TLMM_GPIO_OE_MASK); + break; default: return 0; } From patchwork Fri Apr 5 09:07:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 786209 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1101:b0:343:f27d:c44e with SMTP id z1csp67697wrw; Fri, 5 Apr 2024 02:09:18 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXHV0JOJwTiDiCMaqfpXsr/uyc9uAz4GEnw7NZNVN1W9Iq4n4ENBT6MUcosjlegf7iUoxASW91lhzXYfoxnCr9G X-Google-Smtp-Source: AGHT+IHNeznmV5566MS2fJJMPVrsIR8JO+lU9O6JK+MIQolTFZ/RPOimMgpASxAhtjUAT/5LZ6jK X-Received: by 2002:a17:906:48da:b0:a4e:ed4:1ad8 with SMTP id d26-20020a17090648da00b00a4e0ed41ad8mr723601ejt.38.1712308158566; Fri, 05 Apr 2024 02:09:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712308158; cv=none; d=google.com; s=arc-20160816; b=yfb2NHPIpPaoqyZxNNteGd3dx4RLZkTMLY24ginxgTcsw+9Qpkhx02aS62Qo9XeAvG fY1fhQtArAJ3FBqZc9KNnNAD/nk93miBhH5TqYhvE19KhQ104tWhu71vrwlKoP5mE56K WXW02MHCiGPbwhuUVSS+R28DjoleVGLMrYPrBaIeMFNG+Ir+slAM1s2+3J4cZx0LqGHY MPqihhyrf5cDIBHRx+6C9qsDKQnL5ruSGq2A+tESPUExuln+L3XDTK4hCXrWi4zu7m2F iPqPVC3GiCVqQO87oznG64G2jjrYIPKkOjBN7YCmWrn9+rDjElQIyVJNdvvkWSl+1ssJ OxbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rK9W2AGbnOfcXupe9xf5SOw7PSXaV/7az0Pvlu4dzww=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=zXdRUXwe52thMIpzY//gEZ0n8rbzdVTuGHYqWjTVaTZ2Qevti8qwn4YH51YxldTHVi o/TrxJnDV89O6DEDAO+xqpZeFi9cKp+fM7T+UVIuHQYMesRulctbVmjPNdvORT9c2RG0 faOlJpVPsoRyLn8jZNLJgU3d2VyVvawnAwg/HTBA1ixuASl/NcT7R7VmWl+QWMye25IC SnKoa4P9niHTkKsr++ZE22NJjMvDfGvur2Llhf3fy9ds5tTiM6lQv2OlRAtVdphk6i1k QKPJGbnEzPyzXp+NFcRjuo7nboxyfZi8E251nq9m/rI3ZrcVR+F743+slOKyt1HI4KWy tyeg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t8tUFo6T; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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([223.178.208.62]) by smtp.gmail.com with ESMTPSA id k9-20020a170902c40900b001e2c0b77b53sm1055959plk.255.2024.04.05.02.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 02:08:49 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v3 5/6] pinctrl: qcom: apq8016: Add GPIO pinctrl function Date: Fri, 5 Apr 2024 14:37:41 +0530 Message-Id: <20240405090742.4148304-6-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240405090742.4148304-1-sumit.garg@linaro.org> References: <20240405090742.4148304-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add GPIO pinctrl function to enable driving GPIO pins as output low or high. Signed-off-by: Sumit Garg --- drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index 1ee8b7db1a2..b14a8921af4 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = { }; static const struct pinctrl_function msm_pinctrl_functions[] = { + {"gpio", 0}, {"blsp_uart1", 2}, {"blsp_uart2", 2}, }; From patchwork Fri Apr 5 09:07:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 786210 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:1101:b0:343:f27d:c44e with SMTP id z1csp67783wrw; Fri, 5 Apr 2024 02:09:30 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV79TVXMdZRQdos2gxCS9lXH/Wjs8jDKsZflfbat6h725GLOx871W1OiniNht+PmmTWUHI/urbIe9HKxmKhUkUg X-Google-Smtp-Source: AGHT+IGPD8R8LkruuaPYpQ45Jaj8OZDVuICR4uYQ/qTM6s+u6cAfP9/3w3DC5QsveySnR6TPYllj X-Received: by 2002:a50:9fe3:0:b0:565:a6a4:2ecc with SMTP id c90-20020a509fe3000000b00565a6a42eccmr673972edf.2.1712308170547; Fri, 05 Apr 2024 02:09:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1712308170; cv=none; d=google.com; s=arc-20160816; b=fyYWVIMghZFYm0wmrP4PXpJf1qRKRxGdcJLudBVIYQtaeb9Tn2t4pf5wdNkagFTmSd DYaNBIWK+zGgD8/btHha7pE2uwQdh6w5aY0aWL9/rsL3/EomhwtZx43/RWLzZQt3DMVL k8j8QGm8M78jdL9EMhzFBD5P9wKa8NeHzsfhAXTSLgzWGOTEtysqCyU5KLl9Vlyxffyc a+46qK36VcLFLpSFnLKl7xcMYeGxUNpXLK44xC9g81MLJU1pyVtWigcPCd9b+9btFbc6 Ruhs7ffcsI7CfkfDKlMEP/maj+Y5Py2lU0+9astGCNdbPbFBquoT9PmqgEDrlf3Hv1Hi W9vA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=61Imx7zQe5/2Gt0o54qbPN/tBXjwTBljJkUO5AGu3LA=; fh=T5H15yVH0x76eljP78R1SA5aX1AOqAQ+w8cgext4uuk=; b=dp4f7O8hnqpxb0KO41NrYoHU55rgoIa2+Q4bE37uc+YTFVlEioce/xDi2mmeggfH/S 7i1QfE4Wo2ZXDHv4UlW8Zp0pqEC9hjtgtiY5prgglvUH0p+kX6/0s9RSg7E3VUd9pLVX UjkXQOR0AUZ4x6DsQ8lzNKs40FltNCUAxrup0zBGkTUETMND1pC2qiztbMZuKPUJ1UXP dThmrDeKbvGYg1ucyTjnSeFR33CGxKIEj1siaa5vq/+koJ3jXtmjy4RBGv0P0u7uN1O8 gR6y+ZxVHI20BHCKUgiBQTX2doUpWo6IlzHsglAWwFAcDusKktfU2df649lW7olTdD4w 3YXQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oAE2PESu; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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([223.178.208.62]) by smtp.gmail.com with ESMTPSA id k9-20020a170902c40900b001e2c0b77b53sm1055959plk.255.2024.04.05.02.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 02:08:54 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: caleb.connolly@linaro.org, neil.armstrong@linaro.org, trini@konsulko.com, lukma@denx.de, seanga2@gmail.com, sjg@chromium.org, laetitia.mariottini@se.com, pascal.eberhard@se.com, abdou.saker@se.com, jimmy.lalande@se.com, benjamin.missey@non.se.com, daniel.thompson@linaro.org, stephan@gerhold.net, Sumit Garg Subject: [PATCH v3 6/6] board: add support for Schneider HMIBSC board Date: Fri, 5 Apr 2024 14:37:42 +0530 Message-Id: <20240405090742.4148304-7-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240405090742.4148304-1-sumit.garg@linaro.org> References: <20240405090742.4148304-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Support for Schneider Electric HMIBSC. Features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI Features enabled in U-Boot: - RAUC updates - Environment protection - USB based ethernet adaptors Signed-off-by: Sumit Garg --- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++++++++++++++++++++++ board/schneider/hmibsc/MAINTAINERS | 6 + configs/hmibsc_defconfig | 86 ++++ doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst | 45 ++ doc/board/schneider/index.rst | 9 + include/configs/hmibsc.h | 57 +++ 7 files changed, 695 insertions(+) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h diff --git a/arch/arm/dts/apq8016-schneider-hmibsc.dts b/arch/arm/dts/apq8016-schneider-hmibsc.dts new file mode 100644 index 00000000000..75c6137e5a1 --- /dev/null +++ b/arch/arm/dts/apq8016-schneider-hmibsc.dts @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. + */ + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + model = "Schneider Electric HMIBSC Board"; + compatible = "schneider,apq8016-hmibsc", "qcom,apq8016"; + + aliases { + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + i2c4 = &blsp_i2c3; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart1; + serial1 = &blsp_uart2; + spi0 = &blsp_spi5; + usid0 = &pm8916_0; + }; + + chosen { + stdout-path = "serial0"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&msm_key_volp_n_default>; + pinctrl-names = "default"; + + button { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pm8916_mpps_leds>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + memory@80000000 { + reg = <0 0x80000000 0 0x40000000>; + }; + + reserved-memory { + ramoops@bff00000 { + compatible = "ramoops"; + reg = <0x0 0xbff00000 0x0 0x100000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + ecc-size = <16>; + }; + }; + + usb-hub { + compatible = "smsc,usb3503"; + reset-gpios = <&pm8916_gpios 1 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; +}; + +&blsp_i2c4 { + status = "okay"; + + adv_bridge: bridge@39 { + compatible = "adi,adv7533"; + reg = <0x39>; + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&pm8916_l6>; + a2vdd-supply = <&pm8916_l6>; + dvdd-supply = <&pm8916_l6>; + pvdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + pinctrl-names = "default","sleep"; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp_i2c6 { + status = "okay"; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&blsp_spi5 { + cs-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <500000>; + }; +}; + +&blsp_uart1 { + label = "UART0"; + status = "okay"; +}; + +&blsp_uart2 { + label = "UART1"; + status = "okay"; +}; + +&lpass { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; +}; + +&pm8916_codec { + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + status = "okay"; +}; + +&pm8916_gpios { + gpio-line-names = + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM", + "NC", + "NC"; + + usb_hub_reset_pm: usb-hub-reset-pm-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-high; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-low; + }; + + usb_sw_sel_pm: usb-sw-sel-pm-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = ; + input-disable; + output-high; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = ; + input-disable; + output-low; + }; +}; + +&pm8916_mpps { + gpio-line-names = + "NC", + "WLAN_LED_CTRL", + "BT_LED_CTRL", + "NC"; + + pm8916_mpps_leds: pm8916-mpps-state { + pins = "mpp2", "mpp3"; + function = "digital"; + output-low; + }; +}; + +&pm8916_resin { + linux,code = ; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sound { + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; + pinctrl-names = "default", "sleep"; + model = "HMIBSC"; + audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + status = "okay"; + + quaternary-dai-link { + link-name = "ADV7533"; + cpu { + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; + + primary-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; + }; + }; + + tertiary-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; + }; + }; +}; + +&tlmm { + pinctrl-0 = <&uart1_mux0_rs232_high &uart1_mux1_rs232_low>; + pinctrl-names = "default"; + + adv7533_int_active: adv533-int-active-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + adv7533_int_suspend: adv7533-int-suspend-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + adv7533_switch_active: adv7533-switch-active-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + adv7533_switch_suspend: adv7533-switch-suspend-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + msm_key_volp_n_default: msm-key-volp-n-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* + * UART1 being the debug console supports various modes of + * operation (RS-232/485/422) controlled via GPIOs configured + * mux as follows: + * + * gpio100 gpio99 UART mode + * 0 0 loopback + * 0 1 RS-232 + * 1 0 RS-485 + * 1 1 RS-422 + * + * The default mode configured here is RS-232 mode. + */ + uart1_mux0_rs232_high: uart1-mux0-rs232-state { + bootph-all; + pins = "gpio99"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + + uart1_mux1_rs232_low: uart1-mux1-rs232-state { + bootph-all; + pins = "gpio100"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; + pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; + pinctrl-names = "default", "device"; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + firmware-name = "qcom/apq8016/wcnss.mbn"; + status = "okay"; +}; + +&wcnss_ctrl { + firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in msm8916.dtsi */ + +/* + * 2mA drive strength is not enough when connecting multiple + * I2C devices with different pull up resistors. + */ +&blsp_i2c4_default { + drive-strength = <16>; +}; + +&blsp_i2c6_default { + drive-strength = <16>; +}; + +&blsp_uart1_default { + bootph-all; +}; + +/* Enable CoreSight */ +&cti0 { status = "okay"; }; +&cti1 { status = "okay"; }; +&cti12 { status = "okay"; }; +&cti13 { status = "okay"; }; +&cti14 { status = "okay"; }; +&cti15 { status = "okay"; }; +&debug0 { status = "okay"; }; +&debug1 { status = "okay"; }; +&debug2 { status = "okay"; }; +&debug3 { status = "okay"; }; +&etf { status = "okay"; }; +&etm0 { status = "okay"; }; +&etm1 { status = "okay"; }; +&etm2 { status = "okay"; }; +&etm3 { status = "okay"; }; +&etr { status = "okay"; }; +&funnel0 { status = "okay"; }; +&funnel1 { status = "okay"; }; +&replicator { status = "okay"; }; +&stm { status = "okay"; }; +&tpiu { status = "okay"; }; diff --git a/board/schneider/hmibsc/MAINTAINERS b/board/schneider/hmibsc/MAINTAINERS new file mode 100644 index 00000000000..0f31bbda966 --- /dev/null +++ b/board/schneider/hmibsc/MAINTAINERS @@ -0,0 +1,6 @@ +HMIBSC BOARD +M: Sumit Garg +S: Maintained +F: board/schneider/hmibsc/ +F: include/configs/hmibsc.h +F: configs/hmibsc_defconfig diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig new file mode 100644 index 00000000000..c41ed3d5925 --- /dev/null +++ b/configs/hmibsc_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="hmibsc" +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_TEXT_BASE=0x8f600000 +CONFIG_SYS_MALLOC_LEN=0x802000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DEFAULT_DEVICE_TREE="apq8016-schneider-hmibsc" +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IDENT_STRING="\nSchneider Electric-HMIBSC" +CONFIG_SYS_LOAD_ADDR=0x80080000 +CONFIG_REMAKE_ELF=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=2048 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="hmibsc => " +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_ENV_EXISTS=y +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON_QCOM_PMIC=y +CONFIG_CLK=y +CONFIG_CLK_QCOM_APQ8016=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_MSM_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_QCOM_APQ8016=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_QCOM=y +CONFIG_MSM_SERIAL=y +CONFIG_SPMI_MSM=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_PHYLIB=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d +CONFIG_CI_UDC=y diff --git a/doc/board/index.rst b/doc/board/index.rst index f0a11f84ccc..428faa810be 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc renesas/index rockchip/index samsung/index + schneider/index sielaff/index siemens/index sifive/index diff --git a/doc/board/schneider/hmibsc.rst b/doc/board/schneider/hmibsc.rst new file mode 100644 index 00000000000..f09fb5af1b3 --- /dev/null +++ b/doc/board/schneider/hmibsc.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Sumit Garg + +HMIBSC +====== + +The HMIBSC is an IIoT Edge Box Core board based on the Qualcomm APQ8016E SoC. +More information can be found on the `SE product page`_. + +U-Boot can be used as a replacement for Qualcomm's original Android bootloader +(a fork of Little Kernel/LK). Like LK, it is installed directly into the ``aboot`` +partition. Note that the U-Boot port used to be loaded as an Android boot image +through LK. This is no longer the case, now U-Boot can replace LK entirely. + +.. _SE product page: https://www.se.com/us/en/product/HMIBSCEA53D1L0T/iiot-edge-box-core-harmony-ipc-emmc-dc-linux-tpm/ + +Build steps +----------- + +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``hmibsc``:: + + $ export CROSS_COMPILE= + $ make hmibsc_defconfig + $ make + +This will build ``u-boot.elf`` in the configured output directory. + +Installation +------------ + +Although the HMIBSC does not have secure boot set up by default, the firmware +still expects firmware ELF images to be "signed". The signature does not provide +any security in this case, but it provides the firmware with some required +metadata. + +To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_:: + + $ ./qtestsign.py aboot u-boot.elf + +Then install the resulting ``u-boot-test-signed.mbn`` to the ``aboot`` partition +on your device, e.g. with ``fastboot flash aboot u-boot-test-signed.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign diff --git a/doc/board/schneider/index.rst b/doc/board/schneider/index.rst new file mode 100644 index 00000000000..55792ed3100 --- /dev/null +++ b/doc/board/schneider/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Schneider Electric +================== + +.. toctree:: + :maxdepth: 2 + + hmibsc diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h new file mode 100644 index 00000000000..66dfa549ce1 --- /dev/null +++ b/include/configs/hmibsc.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for HMIBSC + * + * (C) Copyright 2024 Sumit Garg + */ + +#ifndef __CONFIGS_HMIBSC_H +#define __CONFIGS_HMIBSC_H + +/* PHY needs a longer aneg time */ +#define PHY_ANEG_TIMEOUT 8000 + +#define HMIBSC_BOOTCOMMAND \ + "setenv devtype mmc; setenv devnum 0; " \ + "test -n \"${BOOT_ORDER}\" || setenv BOOT_ORDER \"A B\"; " \ + "test -n \"${BOOT_A_LEFT}\" || setenv BOOT_A_LEFT 3; " \ + "test -n \"${BOOT_B_LEFT}\" || setenv BOOT_B_LEFT 3; " \ + "setenv raucslot; " \ + "for BOOT_SLOT in \"${BOOT_ORDER}\"; do " \ + " if test \"x${raucslot}\" != \"x\"; then " \ + " echo \"skip remaining slots...\"; " \ + " elif test \"x${BOOT_SLOT}\" = \"xA\"; then " \ + " if test ${BOOT_A_LEFT} -gt 0; then " \ + " setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1; " \ + " echo \"Found valid RAUC slot A\"; " \ + " setenv raucslot \"rauc.slot=A\"; " \ + " setenv raucpart A; setenv distro_bootpart 6;" \ + " fi; " \ + " elif test \"x${BOOT_SLOT}\" = \"xB\"; then " \ + " if test ${BOOT_B_LEFT} -gt 0; then " \ + " setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1; " \ + " echo \"Found valid RAUC slot B\"; " \ + " setenv raucslot \"rauc.slot=B\"; " \ + " setenv raucpart B; setenv distro_bootpart 7;" \ + " fi; " \ + " fi; " \ + "done; " \ + "if test -n \"${raucslot}\"; then " \ + " setenv bootargs console=ttyMSM1 root=PARTLABEL=rootfs_${raucpart} rw rootwait ${raucslot}; " \ + " saveenv; " \ + "else " \ + " echo \"No valid RAUC slot found. Resetting tries to 3\"; " \ + " setenv BOOT_A_LEFT 3; " \ + " setenv BOOT_B_LEFT 3; " \ + " saveenv; " \ + " reset; " \ + "fi; " \ + "load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} /boot/fitImage && bootm" + +#define CFG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x90000000\0" \ + "bootcmd=" HMIBSC_BOOTCOMMAND "\0" + +#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" + +#endif