From patchwork Sat Apr 13 17:03:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 788587 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C86440BE7; Sat, 13 Apr 2024 17:03:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713027811; cv=none; b=smN7kaAdtzweOD9bttbVssfMVdaDB+8idUnMHng+6HQ7edNx6DRInh5b15aHBpThPjwdIU7vMYAOImPMLgxmUeKmDqBd8UZmUyHxVB2x4iGIyviyrDY3zaqcSjgPFBxXWgPA2fh6DQKaaLWwvWB/umdlEDZiy7N/Y5itJgiOMbs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713027811; c=relaxed/simple; bh=9pkXLlIZF374osaBV+eI1C7R/HMu//q75xIYUjjHffg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FIO2AS4P6HrZV/s87up1zhKiaxS6iAy4WWvmJ4T5Om6jRuow8gh53Wf0utQgt390e6xnLLhGW8cLTL9cU+YAdfdP43NzhWcmxkZSJJDFeS95mtqRT/U83iisKssTw98XcQJB5GC6UNkqlWm1n0dCThBGT5bdJBlh+MZ2SNgnJfQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lj93eOnv; arc=none smtp.client-ip=209.85.208.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lj93eOnv" Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-56e78970853so4471243a12.0; Sat, 13 Apr 2024 10:03:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1713027807; x=1713632607; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6fFoNwrz7Z2PTKzKuXP+UfswKZFc2fljpsBuXAAeuEI=; b=lj93eOnvy94ceWGxcNpRSnkFDYPW6HQdxQrvhv8SuSpdmA1UHKtdNjZ8PpoqaDwm+2 2m1KgqQ1sgQHQepMqIXLGUZqsxZMHqG6HMtm9JmmnlDiTddJCKcMJIPHPr7hQfnvil2r kuz6/9tuSoxZWxiSrhS/5UJ+z46A7SvDCx0MKaw4DQ3sPg9VkuaZW/KJHUSQNE7dkLNb TBK1dVYrGH7GharVxPRf8TIYDt9897jRdmfPh166O5EmVhsILkaxG4NNuzMzR098ZYoU w+ak2Yp/BRwhaIcGzyIA7Wfxerp4IU7B0T67V+EM8uQxBqsXiXq9AEHv/qKIWHwLG6SG yj9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713027807; x=1713632607; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6fFoNwrz7Z2PTKzKuXP+UfswKZFc2fljpsBuXAAeuEI=; b=ooBR8vqnDr/NP1xcfFNGr6T2tpmBY9UnS4J3yHn6dAj3rDp5CBbLwpWNmRq4IFIk7e Od3IrCjUlvK5e1ZlQtpjKyIlTzucvVF/wACQYTS0QPxYMS6ADy3fcoGW2zxLfAUq/IDk CFjxWaza+fMQgGrAYLyaRG1duDWOP+4rYoRSC6NUiRcHS6IfnMLrivlMDJy56YqDum/m 5xDt+6nzw2XMMHRTNgp4K3dPNBfgMyesFff7znHkPpnu859alLH9zoxlM7HNIu5F1PWO 62Fw5ZqaWbl2rUABJjxNb8qNtvRw/cKGUE/mo+J23piGsOoTB8URNmnpAVcLDaTYyZ76 bANg== X-Forwarded-Encrypted: i=1; AJvYcCWjyISgloh0k0kLp9lBMamrfZTx1ntCUIKh2a2AYwfCWnq9MlE2k9xQLCugeKTisp7F4Mtb99SFMrQ083zlz6E6H67l8y0I4DXdhHi4+FmnFfBz25CXU5PhVoHr9m2KBBiJHEPumqp3LvAkK6b98+LuwLHHSLl9jXfnZh24sQGNkRAA2dHTUtk= X-Gm-Message-State: AOJu0Yx5Vb+VXo+V0mXyjO3JLYAh/ecjK5tdU9cgx82wNZrI2UgdkVPw /Rso+ok0K3YbPVvzKjIB7g6efRv/0cEnw4oECsm5/QZTFOzF2erPmsYnZw== X-Google-Smtp-Source: AGHT+IHyH/OHAz0VH25NxBTjJ/zSD+y/aMVNJJZmwDCiXzfYS39Gc0ZLTQblGf135PDbpcAGv8ZOXA== X-Received: by 2002:a17:907:720c:b0:a52:1e5a:3ec4 with SMTP id dr12-20020a170907720c00b00a521e5a3ec4mr7827000ejc.5.1713027807383; Sat, 13 Apr 2024 10:03:27 -0700 (PDT) Received: from localhost.localdomain (ccu225.neoplus.adsl.tpnet.pl. [83.30.144.225]) by smtp.gmail.com with ESMTPSA id kj15-20020a170907764f00b00a51a60bf400sm3195967ejc.76.2024.04.13.10.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Apr 2024 10:03:26 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] arm64: dts: qcom: msm8976: Add IOMMU nodes Date: Sat, 13 Apr 2024 19:03:14 +0200 Message-Id: <20240413170317.34553-2-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240413170317.34553-1-a39.skl@gmail.com> References: <20240413170317.34553-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the nodes describing the apps and gpu iommu and its context banks that are found on msm8976 SoCs. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 81 +++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index d2bb1ada361a..8bdcc1438177 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -808,6 +808,87 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x30000>; }; + apps_iommu: iommu@1ee0000 { + compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; + reg = <0x01ee0000 0x3000>; + ranges = <0 0x01e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* VFE */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x15000 0x1000>; + qcom,ctx-asid = <20>; + interrupts = ; + }; + + /* VENUS NS */ + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x16000 0x1000>; + qcom,ctx-asid = <21>; + interrupts = ; + }; + + /* MDP0 */ + iommu-ctx@17000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x17000 0x1000>; + qcom,ctx-asid = <22>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01f08000 0x8000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX3D_TCU_CLK>; + clock-names = "iface", "bus"; + + power-domains = <&gcc OXILI_CX_GDSC>; + + qcom,iommu-secure-id = <18>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* gfx3d user */ + iommu-ctx@0 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x0 0x1000>; + qcom,ctx-asid = <0>; + interrupts = ; + }; + + /* gfx3d secure */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x1000 0x1000>; + qcom,ctx-asid = <2>; + interrupts = ; + }; + + /* gfx3d priv */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x2000 0x1000>; + qcom,ctx-asid = <1>; + interrupts = ; + }; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x1000>, From patchwork Sat Apr 13 17:03:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 790865 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D798B524C9; Sat, 13 Apr 2024 17:03:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713027813; cv=none; b=kuKhb4kwdrmG4iI5HN4Bic6SUgmX9GeUxGoKjl7LHQrNs4Kxmq1EZ+7q0wz8o+qzwUCOb7KKYUw5xpyEoSlGfqZbfcvptuBmZGslx2E6KkVowwrVp36qMdHOsng+si34JBmVMSHZ5yuWrJU5rmMpXC40cjOxznOUSv21qXzkkN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[83.30.144.225]) by smtp.gmail.com with ESMTPSA id kj15-20020a170907764f00b00a51a60bf400sm3195967ejc.76.2024.04.13.10.03.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Apr 2024 10:03:28 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] arm64: dts: qcom: msm8976: Add MDSS nodes Date: Sat, 13 Apr 2024 19:03:15 +0200 Message-Id: <20240413170317.34553-3-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240413170317.34553-1-a39.skl@gmail.com> References: <20240413170317.34553-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add MDSS nodes to support displays on MSM8976 SoC. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 280 +++++++++++++++++++++++++- 1 file changed, 276 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 8bdcc1438177..ce15c6ec9f4e 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -785,10 +785,10 @@ gcc: clock-controller@1800000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, - <0>, - <0>, - <0>, - <0>; + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>; clock-names = "xo", "xo_a", "dsi0pll", @@ -808,6 +808,278 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x30000>; }; + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "vsync", + "core"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible = "qcom,msm8976-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDP_TBU_CLK>, + <&gcc GCC_MDP_RT_TBU_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "tbu", + "tbu_rt"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + iommus = <&apps_iommu 22>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + mdss_mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-177780000 { + opp-hz = /bits/ 64 <177780000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_nom>; + }; + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a94000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, + <&gcc GCC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + + }; + + opp-161250000 { + opp-hz = /bits/ 64 <161250000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1: dsi@1a96000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a96000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, + <&gcc GCC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + phys = <&mdss_dsi1_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a96a00 0xd4>, + <0x01a96400 0x280>, + <0x01a96b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + apps_iommu: iommu@1ee0000 { compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; reg = <0x01ee0000 0x3000>; From patchwork Sat Apr 13 17:03:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 788586 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 648F6537F0; Sat, 13 Apr 2024 17:03:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[83.30.144.225]) by smtp.gmail.com with ESMTPSA id kj15-20020a170907764f00b00a51a60bf400sm3195967ejc.76.2024.04.13.10.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Apr 2024 10:03:30 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] arm64: dts: qcom: msm8976: Add Adreno GPU Date: Sat, 13 Apr 2024 19:03:16 +0200 Message-Id: <20240413170317.34553-4-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240413170317.34553-1-a39.skl@gmail.com> References: <20240413170317.34553-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Adreno GPU node. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 71 +++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index ce15c6ec9f4e..acb6331999bd 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1080,6 +1080,77 @@ mdss_dsi1_phy: phy@1a96a00 { }; }; + adreno_gpu: gpu@1c00000 { + compatible = "qcom,adreno-510.0", "qcom,adreno"; + + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GFX3D_OXILI_CLK>, + <&gcc GCC_GFX3D_OXILI_AHB_CLK>, + <&gcc GCC_GFX3D_OXILI_GMEM_CLK>, + <&gcc GCC_GFX3D_BIMC_CLK>, + <&gcc GCC_GFX3D_OXILI_TIMER_CLK>, + <&gcc GCC_GFX3D_OXILI_AON_CLK>; + clock-names = "core", + "iface", + "mem", + "mem_iface", + "rbbmtimer", + "alwayson"; + + power-domains = <&gcc OXILI_GX_GDSC>; + + iommus = <&gpu_iommu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-supported-hw = <0xff>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmpd_opp_svs>; + opp-supported-hw = <0xff>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmpd_opp_nom>; + opp-supported-hw = <0xff>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-supported-hw = <0xff>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0xff>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0xff>; + }; + }; + }; + apps_iommu: iommu@1ee0000 { compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; reg = <0x01ee0000 0x3000>; From patchwork Sat Apr 13 17:03:17 2024 Content-Type: text/plain; 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[83.30.144.225]) by smtp.gmail.com with ESMTPSA id kj15-20020a170907764f00b00a51a60bf400sm3195967ejc.76.2024.04.13.10.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Apr 2024 10:03:32 -0700 (PDT) From: Adam Skladowski To: Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] arm64: dts: qcom: msm8976: Add WCNSS node Date: Sat, 13 Apr 2024 19:03:17 +0200 Message-Id: <20240413170317.34553-5-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240413170317.34553-1-a39.skl@gmail.com> References: <20240413170317.34553-1-a39.skl@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add node describing wireless connectivity subsystem. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 104 ++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index acb6331999bd..1e492bcc56f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -771,6 +771,36 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { drive-strength = <2>; bias-disable; }; + + wcss_wlan_default: wcss-wlan-default-state { + wcss-wlan2-pins { + pins = "gpio40"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan1-pins { + pins = "gpio41"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan0-pins { + pins = "gpio42"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan-pins { + pins = "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -1458,6 +1488,80 @@ blsp2_i2c4: i2c@7af8000 { status = "disabled"; }; + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v3-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names = "ccu", + "dxe", + "pmu"; + + memory-region = <&wcnss_fw_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + power-domains = <&rpmpd MSM8976_VDDCX>, + <&rpmpd MSM8976_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-0 = <&wcss_wlan_default>; + pinctrl-names = "default"; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;