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Thu, 10 Oct 2019 20:25:05 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763%3]) with mapi id 15.20.2327.026; Thu, 10 Oct 2019 20:25:05 +0000 From: Robert Richter To: Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , Jason Baron , Tero Kristo CC: James Morse , Robert Richter , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Qiuxu Zhuo Subject: [PATCH 01/19] EDAC: Replace EDAC_DIMM_PTR() macro with edac_get_dimm() function Thread-Topic: [PATCH 01/19] EDAC: Replace EDAC_DIMM_PTR() macro with edac_get_dimm() function Thread-Index: AQHVf6jNve/3IMiRJ0u/d/8Li7yNMw== Date: Thu, 10 Oct 2019 20:25:05 +0000 Message-ID: <20191010202418.25098-2-rrichter@marvell.com> References: <20191010202418.25098-1-rrichter@marvell.com> In-Reply-To: <20191010202418.25098-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0336.eurprd05.prod.outlook.com (2603:10a6:7:92::31) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:165::10) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [31.208.96.227] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 8f428880-e909-4f22-0977-08d74dbfefe1 x-ms-traffictypediagnostic: MN2PR18MB2701: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:169; x-forefront-prvs: 018632C080 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(39850400004)(346002)(136003)(366004)(376002)(189003)(199004)(6436002)(6512007)(54906003)(71190400001)(110136005)(14454004)(316002)(6486002)(86362001)(71200400001)(5660300002)(2906002)(66066001)(25786009)(50226002)(478600001)(11346002)(446003)(476003)(486006)(3846002)(6116002)(2616005)(99286004)(30864003)(1076003)(6506007)(76176011)(4326008)(14444005)(386003)(7736002)(305945005)(52116002)(26005)(256004)(102836004)(81166006)(66946007)(36756003)(186003)(81156014)(66446008)(66556008)(8936002)(64756008)(8676002)(66476007); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB2701; H:MN2PR18MB3408.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: uR5kyoA54SZENaHQ0fIB4DLn4Fp6eCXX9tCGzfb+eHgtNGc90H/l6ytQfUDYfB/U+YEV9oSAqshK9bTCdzhfGG75vt7qlFwjmIwm+bUmAGrbWruEnVPyNp4FPhJk07ceK/kWITmAI/6nyh80Z2uoc02oBoSaAVT1kvdkHHbaigcMhavu7c1zTk4JOyvu12Q17tdWESCuU6pnp7G2Yt3k1z35c7xZ34l0PLwexK74fqOLqWTxZ0HwDlXOLjSZZOGoD20SaJx0sKQwiUmRnG7cCbMOE3OzXdTj1w1ohlqih2k15gEO/fOg7cV8fEq1Vpcm37/keVNB5/V7J5cdphCea0h2+ZjozPMLuMKOr7Txj0sdibkThFXwiNn2YVZAJKU2iQFucbv1qTDjuIHLIiPTw7brLS3w2ZMOwwxwWB4MDok= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 8f428880-e909-4f22-0977-08d74dbfefe1 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Oct 2019 20:25:05.6438 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JPWRK4r2lvF1voxyW6gYzDj4cyo+AfteT5YrRvZHgTCci+kHr5ik9D9ho4b3wi+E9Owftk0PnV5yz0d0uMTZfg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2701 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-10_07:2019-10-10,2019-10-10 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The EDAC_DIMM_PTR() macro takes 3 arguments from struct mem_ctl_info. Clean up this interface to only pass the mci struct and replace this macro with the new function edac_get_dimm(). Also introduce the edac_get_dimm_by_index() function for later use. This allows it to get a dimm pointer only by a given index. This can be useful if the dimm's position within the layers of the memory controller or the exact size of the layers are unknown. Small style changes made for some hunks after applying the semantic patch. Semantic patch used: @@ expression mci, a, b,c; @@ -EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, a, b, c) +edac_get_dimm(mci, a, b, c) Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 1 + drivers/edac/ghes_edac.c | 7 +-- drivers/edac/i10nm_base.c | 3 +- drivers/edac/i3200_edac.c | 3 +- drivers/edac/i5000_edac.c | 5 +- drivers/edac/i5100_edac.c | 3 +- drivers/edac/i5400_edac.c | 3 +- drivers/edac/i7300_edac.c | 3 +- drivers/edac/i7core_edac.c | 3 +- drivers/edac/ie31200_edac.c | 7 +-- drivers/edac/pnd2_edac.c | 4 +- drivers/edac/sb_edac.c | 2 +- drivers/edac/skx_base.c | 3 +- drivers/edac/ti_edac.c | 2 +- include/linux/edac.h | 92 ++++++++++++++++++++++++------------- 15 files changed, 79 insertions(+), 62 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index e6fd079783bd..3d45adb5957f 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -438,6 +438,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, goto error; mci->dimms[off] = dimm; dimm->mci = mci; + dimm->idx = off; /* * Copy DIMM location and initialize it. diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index d413a0bdc9ad..fb31e80dfe94 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -98,9 +98,7 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) if (dh->type == DMI_ENTRY_MEM_DEVICE) { struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh; - struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, - dimm_fill->count, 0, 0); + struct dimm_info *dimm = edac_get_dimm(mci, dimm_fill->count, 0, 0); u16 rdr_mask = BIT(7) | BIT(13); if (entry->size == 0xffff) { @@ -527,8 +525,7 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev) dimm_fill.mci = mci; dmi_walk(ghes_edac_dmidecode, &dimm_fill); } else { - struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, 0, 0, 0); + struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0); dimm->nr_pages = 1; dimm->grain = 128; diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index c370d5457e6b..059eccf0582b 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -154,8 +154,7 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci) ndimms = 0; for (j = 0; j < I10NM_NUM_DIMMS; j++) { - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); mtr = I10NM_GET_DIMMMTR(imc, i, j); mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i, j); edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n", diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c index 299b441647cd..432b375a4075 100644 --- a/drivers/edac/i3200_edac.c +++ b/drivers/edac/i3200_edac.c @@ -392,8 +392,7 @@ static int i3200_probe1(struct pci_dev *pdev, int dev_idx) unsigned long nr_pages; for (j = 0; j < nr_channels; j++) { - struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, i, j, 0); + struct dimm_info *dimm = edac_get_dimm(mci, i, j, 0); nr_pages = drb_to_nr_pages(drbs, stacked, j, i); if (nr_pages == 0) diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c index 078a7351bf05..1a6f69c859ab 100644 --- a/drivers/edac/i5000_edac.c +++ b/drivers/edac/i5000_edac.c @@ -1275,9 +1275,8 @@ static int i5000_init_csrows(struct mem_ctl_info *mci) if (!MTR_DIMMS_PRESENT(mtr)) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, - channel / MAX_BRANCHES, - channel % MAX_BRANCHES, slot); + dimm = edac_get_dimm(mci, channel / MAX_BRANCHES, + channel % MAX_BRANCHES, slot); csrow_megs = pvt->dimm_info[slot][channel].megabytes; dimm->grain = 8; diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c index 12bebecb203b..134586753311 100644 --- a/drivers/edac/i5100_edac.c +++ b/drivers/edac/i5100_edac.c @@ -858,8 +858,7 @@ static void i5100_init_csrows(struct mem_ctl_info *mci) if (!npages) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, - chan, rank, 0); + dimm = edac_get_dimm(mci, chan, rank, 0); dimm->nr_pages = npages; dimm->grain = 32; diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c index 8c86c6fd7da7..f131c05ade9f 100644 --- a/drivers/edac/i5400_edac.c +++ b/drivers/edac/i5400_edac.c @@ -1187,8 +1187,7 @@ static int i5400_init_dimms(struct mem_ctl_info *mci) if (!MTR_DIMMS_PRESENT(mtr)) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, - channel / 2, channel % 2, slot); + dimm = edac_get_dimm(mci, channel / 2, channel % 2, slot); size_mb = pvt->dimm_info[slot][channel].megabytes; diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c index 447d357c7a67..2e9bbe56cde9 100644 --- a/drivers/edac/i7300_edac.c +++ b/drivers/edac/i7300_edac.c @@ -794,8 +794,7 @@ static int i7300_init_csrows(struct mem_ctl_info *mci) for (ch = 0; ch < max_channel; ch++) { int channel = to_channel(ch, branch); - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, branch, ch, slot); + dimm = edac_get_dimm(mci, branch, ch, slot); dinfo = &pvt->dimm_info[slot][channel]; diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c index a71cca6eeb33..b3135b208f9a 100644 --- a/drivers/edac/i7core_edac.c +++ b/drivers/edac/i7core_edac.c @@ -585,8 +585,7 @@ static int get_dimm_config(struct mem_ctl_info *mci) if (!DIMM_PRESENT(dimm_dod[j])) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, - i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j])); rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c index d26300f9cb07..4f65073f230b 100644 --- a/drivers/edac/ie31200_edac.c +++ b/drivers/edac/ie31200_edac.c @@ -490,9 +490,7 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) if (dimm_info[j][i].dual_rank) { nr_pages = nr_pages / 2; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, (i * 2) + 1, - j, 0); + dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0); dimm->nr_pages = nr_pages; edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); dimm->grain = 8; /* just a guess */ @@ -503,8 +501,7 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) dimm->dtype = DEV_UNKNOWN; dimm->edac_mode = EDAC_UNKNOWN; } - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, i * 2, j, 0); + dimm = edac_get_dimm(mci, i * 2, j, 0); dimm->nr_pages = nr_pages; edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); dimm->grain = 8; /* same guess */ diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c index b1193be1ef1d..933f7722b893 100644 --- a/drivers/edac/pnd2_edac.c +++ b/drivers/edac/pnd2_edac.c @@ -1231,7 +1231,7 @@ static void apl_get_dimm_config(struct mem_ctl_info *mci) if (!(chan_mask & BIT(i))) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, 0, 0); + dimm = edac_get_dimm(mci, i, 0, 0); if (!dimm) { edac_dbg(0, "No allocated DIMM for channel %d\n", i); continue; @@ -1311,7 +1311,7 @@ static void dnv_get_dimm_config(struct mem_ctl_info *mci) if (!ranks_of_dimm[j]) continue; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); if (!dimm) { edac_dbg(0, "No allocated DIMM for channel %d DIMM %d\n", i, j); continue; diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index a2fd39d330d6..4957e8ee1879 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c @@ -1621,7 +1621,7 @@ static int __populate_dimms(struct mem_ctl_info *mci, } for (j = 0; j < max_dimms_per_channel; j++) { - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); if (pvt->info.type == KNIGHTS_LANDING) { pci_read_config_dword(pvt->knl.pci_channel[i], knl_mtr_reg, &mtr); diff --git a/drivers/edac/skx_base.c b/drivers/edac/skx_base.c index 0fcf3785e8f3..8895eda365ff 100644 --- a/drivers/edac/skx_base.c +++ b/drivers/edac/skx_base.c @@ -177,8 +177,7 @@ static int skx_get_dimm_config(struct mem_ctl_info *mci) pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap); pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg); for (j = 0; j < SKX_NUM_DIMMS; j++) { - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, - mci->n_layers, i, j, 0); + dimm = edac_get_dimm(mci, i, j, 0); pci_read_config_dword(imc->chan[i].cdev, 0x80 + 4 * j, &mtr); if (IS_DIMM_PRESENT(mtr)) { diff --git a/drivers/edac/ti_edac.c b/drivers/edac/ti_edac.c index 6ac26d1b929f..8be3e89a510e 100644 --- a/drivers/edac/ti_edac.c +++ b/drivers/edac/ti_edac.c @@ -135,7 +135,7 @@ static void ti_edac_setup_dimm(struct mem_ctl_info *mci, u32 type) u32 val; u32 memsize; - dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 0, 0, 0); + dimm = edac_get_dimm(mci, 0, 0, 0); val = ti_edac_readl(edac, EMIF_SDRAM_CONFIG); diff --git a/include/linux/edac.h b/include/linux/edac.h index c19483b90079..7f9804438589 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -403,37 +403,6 @@ struct edac_mc_layer { __i; \ }) -/** - * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array - * for the element given by [layer0,layer1,layer2] position - * - * @layers: a struct edac_mc_layer array, describing how many elements - * were allocated for each layer - * @var: name of the var where we want to get the pointer - * (like mci->dimms) - * @nlayers: Number of layers at the @layers array - * @layer0: layer0 position - * @layer1: layer1 position. Unused if n_layers < 2 - * @layer2: layer2 position. Unused if n_layers < 3 - * - * For 1 layer, this macro returns "var[layer0]"; - * - * For 2 layers, this macro is similar to allocate a bi-dimensional array - * and to return "var[layer0][layer1]"; - * - * For 3 layers, this macro is similar to allocate a tri-dimensional array - * and to return "var[layer0][layer1][layer2]"; - */ -#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \ - typeof(*var) __p; \ - int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \ - if (___i < 0) \ - __p = NULL; \ - else \ - __p = (var)[___i]; \ - __p; \ -}) - struct dimm_info { struct device dev; @@ -443,6 +412,7 @@ struct dimm_info { unsigned int location[EDAC_MAX_LAYERS]; struct mem_ctl_info *mci; /* the parent */ + unsigned int idx; /* index within the parent dimm array */ u32 grain; /* granularity of reported error in bytes */ enum dev_type dtype; /* memory device type */ @@ -669,4 +639,64 @@ struct mem_ctl_info { bool fake_inject_ue; u16 fake_inject_count; }; + +/** + * edac_get_dimm_by_index - Get DIMM info from a memory controller + * given by an index + * + * @mci: a struct mem_ctl_info + * @index: index in the memory controller's DIMM array + * + * Returns a struct dimm_info* or NULL on failure. + */ +static inline struct dimm_info * +edac_get_dimm_by_index(struct mem_ctl_info *mci, int index) +{ + if (index < 0 || index >= mci->tot_dimms) + return NULL; + + if (WARN_ON_ONCE(mci->dimms[index]->idx != index)) + return NULL; + + return mci->dimms[index]; +} + +/** + * edac_get_dimm - Get DIMM info from a memory controller given by + * [layer0,layer1,layer2] position + * + * @mci: a struct mem_ctl_info + * @layer0: layer0 position + * @layer1: layer1 position. Unused if n_layers < 2 + * @layer2: layer2 position. Unused if n_layers < 3 + * + * For 1 layer, this function returns "dimms[layer0]"; + * + * For 2 layers, this function is similar to allocate a bi-dimensional + * array and to return "dimms[layer0][layer1]"; + * + * For 3 layers, this function is similar to allocate a tri-dimensional array + * and to return "dimms[layer0][layer1][layer2]"; + */ +static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci, + int layer0, int layer1, int layer2) +{ + int index; + + if (layer0 < 0 + || (mci->n_layers > 1 && layer1 < 0) + || (mci->n_layers > 2 && layer2 < 0)) + return NULL; + + index = layer0; + + if (mci->n_layers > 1) + index = index * mci->layers[1].size + layer1; + + if (mci->n_layers > 2) + index = index * mci->layers[2].size + layer2; + + return edac_get_dimm_by_index(mci, index); +} + #endif From patchwork Thu Oct 10 20:25:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175829 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792299ill; Thu, 10 Oct 2019 13:25:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwncJKi534kXgf0d+6TdFlufPa6IgFdSes5MTutEAanf+PbZ/A2J/5ijkt+7R1M33UVfmfH X-Received: by 2002:a05:6402:1686:: with SMTP id a6mr10140908edv.174.1570739132947; Thu, 10 Oct 2019 13:25:32 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739132; cv=pass; d=google.com; s=arc-20160816; b=kkJ+pk7abQOOfWLS5uOjzgf7HiQRNsifbgqiRbMajloRI4RmO1lDn5ewMl4kaRtYer HX78sz5fIzYplrDyb0BYsVBku7C0XkfZCGHg3szdvd9eHqnSSWBPdO2IbTrnNzw1RVTz DXxx1wO0EUoZs7cbevimHPw5nx9vQYPRy3E7Oe939nP5qQp5qMapoElBWZFHbl7j9l6K bMHT4kaXWV+nkbtdqK18TukfMM/WloEutiajMMKQhCsArzsggn0ueqeZMj1HVTnGUO5k /cMMd6hv10qaOK/JX5qyTcIh/k+gdpB6Mx15RSkKi2pqgS0cj2OcgokUZPw26pr4sMl6 KCVw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=p+udCukPlPwswbWHZRjmj/wpHRMK1txYSnQh2Qv8kFU=; b=qLA/OCyorBTQUXCWVUIy2NpYgQKICCOOrxFcqv8KO6cSNq+EAXAryhzJ3kcRbyp6y2 Mp3zG68VScnIHQtbnJGjunV29+9YI1G3TFHr/2AFO40WYk7rlbyB77/Oh/quSVnmJTLk +HZzHR38v5D4Lei1wYHulDfLTgAQBsgyXejAPLrkeXV7GuoXC8xb4UXFnA2LYqE0Rkae y4CMwWWwlissP91xuZ2ciDNN4U2zBcMt39TgaHYq8IXz3DlFAD3Hif7q1SxsQAQO+EOu kSej5lZ6nQKsWtYPxRO9AOuEfzQitSItUsIamN3v7DaOna6gQflrIT3xjNrYju8drbwY rbpw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=q5SfKuhY; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=XzK5LIBi; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Thu, 10 Oct 2019 20:25:07 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763%3]) with mapi id 15.20.2327.026; Thu, 10 Oct 2019 20:25:07 +0000 From: Robert Richter To: Borislav Petkov , Mauro Carvalho Chehab , Tony Luck CC: James Morse , Robert Richter , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH 02/19] EDAC: Remove EDAC_DIMM_OFF() macro Thread-Topic: [PATCH 02/19] EDAC: Remove EDAC_DIMM_OFF() macro Thread-Index: AQHVf6jOVfuHIna6UUqSRNg3t3vfNQ== Date: Thu, 10 Oct 2019 20:25:07 +0000 Message-ID: <20191010202418.25098-3-rrichter@marvell.com> References: <20191010202418.25098-1-rrichter@marvell.com> In-Reply-To: <20191010202418.25098-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0336.eurprd05.prod.outlook.com (2603:10a6:7:92::31) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:165::10) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [31.208.96.227] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ecd990db-9d6d-47dd-5f65-08d74dbff129 x-ms-traffictypediagnostic: MN2PR18MB2701: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4502; 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This can be much simplified now as the offset is already stored in struct dimm_info. Use it directly and completely remove the EDAC_DIMM_OFF() macro. Another advantage is that edac_mc_alloc() could be used even if the exact size of the layers is unknown. Only the number of DIMMs would be needed. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 15 +++++-------- drivers/edac/edac_mc_sysfs.c | 20 ++++-------------- include/linux/edac.h | 41 ------------------------------------ 3 files changed, 9 insertions(+), 67 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 3d45adb5957f..72088d49b03b 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -314,10 +314,10 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, struct dimm_info *dimm; u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; unsigned int pos[EDAC_MAX_LAYERS]; - unsigned int size, tot_dimms = 1, count = 1; + unsigned int idx, size, tot_dimms = 1, count = 1; unsigned int tot_csrows = 1, tot_channels = 1, tot_errcount = 0; void *pvt, *p, *ptr = NULL; - int i, j, row, chn, n, len, off; + int i, j, row, chn, n, len; bool per_rank = false; BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); @@ -425,20 +425,15 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, memset(&pos, 0, sizeof(pos)); row = 0; chn = 0; - for (i = 0; i < tot_dimms; i++) { + for (idx = 0; idx < tot_dimms; idx++) { chan = mci->csrows[row]->channels[chn]; - off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); - if (off < 0 || off >= tot_dimms) { - edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n"); - goto error; - } dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); if (!dimm) goto error; - mci->dimms[off] = dimm; + mci->dimms[idx] = dimm; dimm->mci = mci; - dimm->idx = off; + dimm->idx = idx; /* * Copy DIMM location and initialize it. diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 32d016f1ecd1..91e4c8f155af 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -557,14 +557,8 @@ static ssize_t dimmdev_ce_count_show(struct device *dev, { struct dimm_info *dimm = to_dimm(dev); u32 count; - int off; - - off = EDAC_DIMM_OFF(dimm->mci->layers, - dimm->mci->n_layers, - dimm->location[0], - dimm->location[1], - dimm->location[2]); - count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][off]; + + count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][dimm->idx]; return sprintf(data, "%u\n", count); } @@ -574,14 +568,8 @@ static ssize_t dimmdev_ue_count_show(struct device *dev, { struct dimm_info *dimm = to_dimm(dev); u32 count; - int off; - - off = EDAC_DIMM_OFF(dimm->mci->layers, - dimm->mci->n_layers, - dimm->location[0], - dimm->location[1], - dimm->location[2]); - count = dimm->mci->ue_per_layer[dimm->mci->n_layers-1][off]; + + count = dimm->mci->ue_per_layer[dimm->mci->n_layers-1][dimm->idx]; return sprintf(data, "%u\n", count); } diff --git a/include/linux/edac.h b/include/linux/edac.h index 7f9804438589..79c5564ee314 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -362,47 +362,6 @@ struct edac_mc_layer { */ #define EDAC_MAX_LAYERS 3 -/** - * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer - * array for the element given by [layer0,layer1,layer2] - * position - * - * @layers: a struct edac_mc_layer array, describing how many elements - * were allocated for each layer - * @nlayers: Number of layers at the @layers array - * @layer0: layer0 position - * @layer1: layer1 position. Unused if n_layers < 2 - * @layer2: layer2 position. Unused if n_layers < 3 - * - * For 1 layer, this macro returns "var[layer0] - var"; - * - * For 2 layers, this macro is similar to allocate a bi-dimensional array - * and to return "var[layer0][layer1] - var"; - * - * For 3 layers, this macro is similar to allocate a tri-dimensional array - * and to return "var[layer0][layer1][layer2] - var". - * - * A loop could be used here to make it more generic, but, as we only have - * 3 layers, this is a little faster. - * - * By design, layers can never be 0 or more than 3. If that ever happens, - * a NULL is returned, causing an OOPS during the memory allocation routine, - * with would point to the developer that he's doing something wrong. - */ -#define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \ - int __i; \ - if ((nlayers) == 1) \ - __i = layer0; \ - else if ((nlayers) == 2) \ - __i = (layer1) + ((layers[1]).size * (layer0)); \ - else if ((nlayers) == 3) \ - __i = (layer2) + ((layers[2]).size * ((layer1) + \ - ((layers[1]).size * (layer0)))); \ - else \ - __i = -EINVAL; \ - __i; \ -}) - struct dimm_info { struct device dev; From patchwork Thu Oct 10 20:25:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175828 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792282ill; Thu, 10 Oct 2019 13:25:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwY/I/DfEd9FYTjBloh71KGHv9oopv4MaR+SoHCxfNeSN3jDVLOTcEE0QxIRUtcDp6T735B X-Received: by 2002:a17:906:1e43:: with SMTP id i3mr9648999ejj.77.1570739131537; Thu, 10 Oct 2019 13:25:31 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739131; cv=pass; d=google.com; s=arc-20160816; b=RDzdSWzTLyycCdJ9lMNwfXzrYQYbmtvgvGTLcF6sxXYdhRMA9v3Inkce5Q6feg+OC5 QlKF7L1nKWqen4aMTAWZzPI45POj5Qc4CslFtiHli79CXln/SK2y6URGNNhEvNcwExOj e3aDUIQ1sRPPB496hb2g93uoO6x+uuoBhJJjoxjqUBJZB8WV8P+ScTGDYFKN73uk3sxJ O7hOuvoja08I9EKCt1YGB9Tbkx0XcTNG61ad38bkjFpBX/RrWFBZNsaBY+HJ070SFMoO hYoNq0Hn88qAG0TP44lE5cCzvfIJISmHiQaPtZfKLJwHOcGwNLELUJFvU2sPV+b0Np46 oeNw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=PbiTKjBv+GvgBhzbCoXdSUHSbvOXcSIXFrsTD8XzAdU=; b=agCk0vYzRkPy0GWWqOGn7TRkUjrEal3GTn8s7of+HNdyNbB8o9QvRR9tKu2K6LDGU+ zdwuSm2z7CaOLmJno6cD1JaBwOYrg4b8AJRFhA8/W8xI1i74fMEq/aMTm3gKdyGDMjpQ QGh9gdhb3ZcoQ0HjZTaND2AvCMoEssf/NQA7nvC62Wh0CsBzZWJkH9FZss4lbBQXMxt7 4gvu8NFJYuh+Ndh0PrG/8w9/AYCISQl0joM+DQMQDR28yie86tJ7/9FWc3gqSYq5xql6 64YQLlQKVuavnNpLZJi9Bq8N17GXfT5vk3V5hH7cqrUnL80tqU4dD9bjAeAic53yMdCG BIAg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=rLpGKEIr; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=A8uK2oET; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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It returns a pointer to a struct dimm_info. This makes the declaration and use of an index obsolete and avoids access to internal data of struct mci (direct array access etc). Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 19 +++++++++++-------- drivers/edac/edac_mc_sysfs.c | 29 ++++++++++++----------------- drivers/edac/ghes_edac.c | 8 ++++---- drivers/edac/i5100_edac.c | 13 +++++-------- include/linux/edac.h | 7 +++++++ 5 files changed, 39 insertions(+), 37 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 72088d49b03b..c5240bb4c6c0 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -145,15 +145,18 @@ static void edac_mc_dump_channel(struct rank_info *chan) edac_dbg(4, " channel->dimm = %p\n", chan->dimm); } -static void edac_mc_dump_dimm(struct dimm_info *dimm, int number) +static void edac_mc_dump_dimm(struct dimm_info *dimm) { char location[80]; + if (!dimm->nr_pages) + return; + edac_dimm_info_location(dimm, location, sizeof(location)); edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", dimm->mci->csbased ? "rank" : "dimm", - number, location, dimm->csrow, dimm->cschannel); + dimm->idx, location, dimm->csrow, dimm->cschannel); edac_dbg(4, " dimm = %p\n", dimm); edac_dbg(4, " dimm->label = '%s'\n", dimm->label); edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); @@ -702,6 +705,7 @@ EXPORT_SYMBOL_GPL(edac_get_owner); int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, const struct attribute_group **groups) { + struct dimm_info *dimm; int ret = -EINVAL; edac_dbg(0, "\n"); @@ -726,9 +730,9 @@ int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, if (csrow->channels[j]->dimm->nr_pages) edac_mc_dump_channel(csrow->channels[j]); } - for (i = 0; i < mci->tot_dimms; i++) - if (mci->dimms[i]->nr_pages) - edac_mc_dump_dimm(mci->dimms[i], i); + + mci_for_each_dimm(mci, dimm) + edac_mc_dump_dimm(dimm); } #endif mutex_lock(&mem_ctls_mutex); @@ -1086,6 +1090,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, const char *msg, const char *other_detail) { + struct dimm_info *dimm; char *p; int row = -1, chan = -1; int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; @@ -1146,9 +1151,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, p = e->label; *p = '\0'; - for (i = 0; i < mci->tot_dimms; i++) { - struct dimm_info *dimm = mci->dimms[i]; - + mci_for_each_dimm(mci, dimm) { if (top_layer >= 0 && top_layer != dimm->location[0]) continue; if (mid_layer >= 0 && mid_layer != dimm->location[1]) diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 91e4c8f155af..0367554e7437 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -621,8 +621,7 @@ static const struct device_type dimm_attr_type = { /* Create a DIMM object under specifed memory controller device */ static int edac_create_dimm_object(struct mem_ctl_info *mci, - struct dimm_info *dimm, - int index) + struct dimm_info *dimm) { int err; dimm->mci = mci; @@ -632,9 +631,9 @@ static int edac_create_dimm_object(struct mem_ctl_info *mci, dimm->dev.parent = &mci->dev; if (mci->csbased) - dev_set_name(&dimm->dev, "rank%d", index); + dev_set_name(&dimm->dev, "rank%d", dimm->idx); else - dev_set_name(&dimm->dev, "dimm%d", index); + dev_set_name(&dimm->dev, "dimm%d", dimm->idx); dev_set_drvdata(&dimm->dev, dimm); pm_runtime_forbid(&mci->dev); @@ -916,7 +915,8 @@ static const struct device_type mci_attr_type = { int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, const struct attribute_group **groups) { - int i, err; + struct dimm_info *dimm; + int err; /* get the /sys/devices/system/edac subsys reference */ mci->dev.type = &mci_attr_type; @@ -940,13 +940,12 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, /* * Create the dimm/rank devices */ - for (i = 0; i < mci->tot_dimms; i++) { - struct dimm_info *dimm = mci->dimms[i]; + mci_for_each_dimm(mci, dimm) { /* Only expose populated DIMMs */ if (!dimm->nr_pages) continue; - err = edac_create_dimm_object(mci, dimm, i); + err = edac_create_dimm_object(mci, dimm); if (err) goto fail_unregister_dimm; } @@ -961,12 +960,9 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, return 0; fail_unregister_dimm: - for (i--; i >= 0; i--) { - struct dimm_info *dimm = mci->dimms[i]; - if (!dimm->nr_pages) - continue; - - device_unregister(&dimm->dev); + mci_for_each_dimm(mci, dimm) { + if (device_is_registered(&dimm->dev)) + device_unregister(&dimm->dev); } device_unregister(&mci->dev); @@ -978,7 +974,7 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, */ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) { - int i; + struct dimm_info *dimm; edac_dbg(0, "\n"); @@ -989,8 +985,7 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) edac_delete_csrow_objects(mci); #endif - for (i = 0; i < mci->tot_dimms; i++) { - struct dimm_info *dimm = mci->dimms[i]; + mci_for_each_dimm(mci, dimm) { if (dimm->nr_pages == 0) continue; edac_dbg(1, "unregistering device %s\n", dev_name(&dimm->dev)); diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index fb31e80dfe94..842080d7b33a 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -82,11 +82,11 @@ static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg) static int get_dimm_smbios_index(u16 handle) { struct mem_ctl_info *mci = ghes_pvt->mci; - int i; + struct dimm_info *dimm; - for (i = 0; i < mci->tot_dimms; i++) { - if (mci->dimms[i]->smbios_handle == handle) - return i; + mci_for_each_dimm(mci, dimm) { + if (dimm->smbios_handle == handle) + return dimm->idx; } return -1; } diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c index 134586753311..0ddc41e47a96 100644 --- a/drivers/edac/i5100_edac.c +++ b/drivers/edac/i5100_edac.c @@ -846,20 +846,17 @@ static void i5100_init_interleaving(struct pci_dev *pdev, static void i5100_init_csrows(struct mem_ctl_info *mci) { - int i; struct i5100_priv *priv = mci->pvt_info; + struct dimm_info *dimm; - for (i = 0; i < mci->tot_dimms; i++) { - struct dimm_info *dimm; - const unsigned long npages = i5100_npages(mci, i); - const unsigned int chan = i5100_csrow_to_chan(mci, i); - const unsigned int rank = i5100_csrow_to_rank(mci, i); + mci_for_each_dimm(mci, dimm) { + const unsigned long npages = i5100_npages(mci, dimm->idx); + const unsigned int chan = i5100_csrow_to_chan(mci, dimm->idx); + const unsigned int rank = i5100_csrow_to_rank(mci, dimm->idx); if (!npages) continue; - dimm = edac_get_dimm(mci, chan, rank, 0); - dimm->nr_pages = npages; dimm->grain = 32; dimm->dtype = (priv->mtr[chan][rank].width == 4) ? diff --git a/include/linux/edac.h b/include/linux/edac.h index 79c5564ee314..8beb6e834be9 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -599,6 +599,13 @@ struct mem_ctl_info { u16 fake_inject_count; }; +#define mci_for_each_dimm(mci, dimm) \ + for ((dimm) = (mci)->dimms[0]; \ + (dimm); \ + (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \ + ? (mci)->dimms[(dimm)->idx + 1] \ + : NULL) + /** * edac_get_dimm_by_index - Get DIMM info from a memory controller * given by an index From patchwork Thu Oct 10 20:25:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175827 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792179ill; Thu, 10 Oct 2019 13:25:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqxqrM0GteI80glhftvxEYtxuz46LSTBt5zpM8jmZ8NwZe+dvWWvcwXmBzm/CFdmSOq58mBI X-Received: by 2002:a05:6402:b38:: with SMTP id bo24mr10299494edb.103.1570739125468; Thu, 10 Oct 2019 13:25:25 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739125; cv=pass; d=google.com; s=arc-20160816; b=NoAwoScEROOT+fCOL8ZOhs1UZAclooE4oTbS+Oj6PuAl/0lUIe6hNjAr1mg8YyxM44 BZ7gLZ4nMzrVuAMR8n5aBxKkKqEIyHEnp628iDKgXDmc2v6OmHpsIKIJMSrVWW/UEM4m 29x5m3q/iwhYizOonCEhKWNN6ustD9yYJIXAO4AxXMKqgrBlJLiYCzovHq+YLJJmhrm0 gWk9oUYTLQM1Z/2mIhSzg9Gmy3RQOLRAfpp5+iqeEecuYm9Up3T5yoLP0n2Pzt+EljWP wVZ/sHvhEaTjC0Ot3kFN/BpT8t631KGWff8KNXxWUx/8dNwnoCu0NOTGjhyJ/7569MRI sI8Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=a3qAQ50KnhCWWX5tKynPYvYyHc24amfLZhkhs5/cBZ0=; b=y8KVdfpF0F4kyM6YhRkzI1occnmdhgOssiO/63iWtmt1BBhDppO3Ncs5t8o/+Ilrzj ePK++/e4aI6igTYGijJ4ID5qFQs7j6DpAoHzXIntH5xCqjQHe3+DNqiee4w3AONx9Gmh +YkFfwo+gKoqDeHpf5wTV9lL59B6WtdYGETINHrCH5VsYRR+4Pq68t6TEQKJGeyHDDIv 3KUCPYUbnal0qnenVxQ5WtWJsVyNyJyD+FhdlFktwvFURsjci1/wEDyTfR1xBRrLLoOr msUwq5xw6JrdL9Bj9u/005uOLzWblgNuxHiJaMTmqGQEwNol/gJSdWQzvxpF4D2RKHj/ 98bg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b="k/9NHNY1"; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=SMysw1ko; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This would cause a checkpatch warning when touching the code later, so just fix it. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index c5240bb4c6c0..f2cbca77bc50 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -323,7 +323,9 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, int i, j, row, chn, n, len; bool per_rank = false; - BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); + if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0)) + return NULL; + /* * Calculate the total amount of dimms and csrows/cschannels while * in the old API emulation mode From patchwork Thu Oct 10 20:25:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175832 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792433ill; Thu, 10 Oct 2019 13:25:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/sY3h1SJHzXnw8MV7hw4SIlumUEHS+IHQDQWoUwFl52jzd7MV1c8v+z+Uu0mZKHIZa1kj X-Received: by 2002:aa7:c257:: with SMTP id y23mr10063166edo.39.1570739140304; Thu, 10 Oct 2019 13:25:40 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739140; cv=pass; d=google.com; s=arc-20160816; b=nQQz5UTKRz2ivBU8tFMLCgf6ZEyYb0tD+NQ+8Zq9q0ekaGzESKeD202+UGNec053sg TtbEi1Q5imCIIR+CawY9vE0wSdSbysRgzzny27CeRixatqRpVmER1hwMU9+EjF0aBhpi sltWGke8sE7KQGQAyTznWBFl/fcsu3OYJPCcM0LAnHoCXD4B0O0D+Nd5tgOoglISIIPX OMqPpm4MxKI2h62XwADLFcGtBhPDqFgLdyBdXtIrKRXD3anf09pGqbAjSns47rTzKerL 9d2fBCTxjc1amFyxdnuZ2u9SmfS5BxfXIZoebS/c+2SaEIOCQGTSdkgpSsWepLT6xcr8 6wQg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=EYTMuCOq9Y0HKhT9rS1SnxbL8uWRb/y3I05+8fGvlGY=; b=obM9V8krENOHwEAaxp9ENN4wXJ0G9uCYsGHooN0za4AacxMlr9Slxs4alTA2rFWVWG GqzcLEsksNk/ywWreqyoxSvM27ZBfsIXdSoMXqck7vOhjjhfyGr0/SFo9rofVpfrEK/8 MxCqFtJDr4O6r4J81sxoEl8fHzpAQm4+/YVqnUnQVVB92beh0p7jlVAL5iqZGK+V9s1S UZiGuicBEw9v09OCYUSV4IRgS68ogBsT+GWWgMvpY3KE9jVfTVmrjJn8JC/MRvhZgRVy mUeWqERIeG9Twt6Wl8JA7uCGaaBHHNiGUd8hF/c5MI+O1UjvfgF7/G9G3L35jInIJWeL ahng== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=tqPKyYQN; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=l4muzkvZ; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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No functional changes. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 59 +++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 29 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index f2cbca77bc50..45b02bb31964 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1171,37 +1171,38 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, * channel/memory controller/... may be affected. * Also, don't show errors for empty DIMM slots. */ - if (e->enable_per_layer_report && dimm->nr_pages) { - if (n_labels >= EDAC_MAX_LABELS) { - e->enable_per_layer_report = false; - break; - } - n_labels++; - if (p != e->label) { - strcpy(p, OTHER_LABEL); - p += strlen(OTHER_LABEL); - } - strcpy(p, dimm->label); - p += strlen(p); - *p = '\0'; + if (!e->enable_per_layer_report || !dimm->nr_pages) + continue; - /* - * get csrow/channel of the DIMM, in order to allow - * incrementing the compat API counters - */ - edac_dbg(4, "%s csrows map: (%d,%d)\n", - mci->csbased ? "rank" : "dimm", - dimm->csrow, dimm->cschannel); - if (row == -1) - row = dimm->csrow; - else if (row >= 0 && row != dimm->csrow) - row = -2; - - if (chan == -1) - chan = dimm->cschannel; - else if (chan >= 0 && chan != dimm->cschannel) - chan = -2; + if (n_labels >= EDAC_MAX_LABELS) { + e->enable_per_layer_report = false; + break; + } + n_labels++; + if (p != e->label) { + strcpy(p, OTHER_LABEL); + p += strlen(OTHER_LABEL); } + strcpy(p, dimm->label); + p += strlen(p); + *p = '\0'; + + /* + * get csrow/channel of the DIMM, in order to allow + * incrementing the compat API counters + */ + edac_dbg(4, "%s csrows map: (%d,%d)\n", + mci->csbased ? "rank" : "dimm", + dimm->csrow, dimm->cschannel); + if (row == -1) + row = dimm->csrow; + else if (row >= 0 && row != dimm->csrow) + row = -2; + + if (chan == -1) + chan = dimm->cschannel; + else if (chan >= 0 && chan != dimm->cschannel) + chan = -2; } if (!e->enable_per_layer_report) { From patchwork Thu Oct 10 20:25:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175844 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2793123ill; Thu, 10 Oct 2019 13:26:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqy1jePZpg7fvJW1OuumcpeqFxGJoQq/tdLLi8bmmdEQgK5xain7ofHphrtTCcnL6W4GgizV X-Received: by 2002:aa7:c2d7:: with SMTP id m23mr10130526edp.206.1570739187583; Thu, 10 Oct 2019 13:26:27 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739187; cv=pass; d=google.com; s=arc-20160816; b=bLeZB6L+NS8dgst+HslfQk0xdSyLT/Tf/CpGSUChe6QhXSalb6bYJ4f4WvcoRv1tVu uFxNFfF/9j6N/402uHGJ9pzh/FkIMEUy5S4GsuhNSbw22IKYFCgknGUrHQij3zKxUd4v q2XHe+Gho8961KU1qgdWzOvVwy6sVq0CyAPMkGlTf3LD8PqV2+q7zFDcK7b1sY6letNv N+LK5Os/lOv53ZaXCdr1oNnV/yH/P40s0jaHPssCgeGLV6Fq8U3IwS0LAuDOIMvNgH1c mBgQ0OKv9Wq/b457NMZ+FCd3Jt+hS6Vns+1457ypeVnkOecbyaHp6E1UhXboT76Tc38g +NhQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=w9guKr/08ubmt7IJxh9IGAibAwOTlUnbhIGpJ9pcE6I=; b=wsSmLBf8TNAL9nwHbVI1KdOoXKg8Rbsy/4fGGzDgEmWSlzMza5a3uE/cwL4M00vFI4 F/9mbNE6yvDDRW+H10SDvNUrEz0zzFzXkWN0jxt4T3RUrZdcze3eEo5rhm1X6pTETvvN TLlLVOygLpxc7jccJCTJVmkFrBxpvf2WwXOJq3idfbGYb6xLrm9C7j7BuTcTCGovBJUd qF+Z0g++iJH/+tcv0lwh4jy/P/9Hn636ICRHVPBZRZwDEQGIPdbBifwVvoGLq22Ne4Xf Y+O0hnNYQLYp1YZIZsZRyj5V+a8KF6H7PCNEjcoeR51o9tw4Hlo83iMWtvuMyPwizZUe C9Pg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=EoAPRiXv; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=w8IiWAW6; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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These unused counters only add complexity, remove them. The error counter values are directly stored in struct dimm_info now. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 104 ++++++++++++----------------------- drivers/edac/edac_mc_sysfs.c | 20 +++---- drivers/edac/ghes_edac.c | 5 +- include/linux/edac.h | 7 +-- 4 files changed, 46 insertions(+), 90 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 45b02bb31964..c1e142643006 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -315,10 +315,9 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, struct csrow_info *csr; struct rank_info *chan; struct dimm_info *dimm; - u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; unsigned int pos[EDAC_MAX_LAYERS]; - unsigned int idx, size, tot_dimms = 1, count = 1; - unsigned int tot_csrows = 1, tot_channels = 1, tot_errcount = 0; + unsigned int idx, size, tot_dimms = 1; + unsigned int tot_csrows = 1, tot_channels = 1; void *pvt, *p, *ptr = NULL; int i, j, row, chn, n, len; bool per_rank = false; @@ -346,19 +345,10 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, * stringent as what the compiler would provide if we could simply * hardcode everything into a single struct. */ - mci = edac_align_ptr(&ptr, sizeof(*mci), 1); - layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); - for (i = 0; i < n_layers; i++) { - count *= layers[i].size; - edac_dbg(4, "errcount layer %d size %d\n", i, count); - ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); - ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); - tot_errcount += 2 * count; - } - - edac_dbg(4, "allocating %d error counters\n", tot_errcount); - pvt = edac_align_ptr(&ptr, sz_pvt, 1); - size = ((unsigned long)pvt) + sz_pvt; + mci = edac_align_ptr(&ptr, sizeof(*mci), 1); + layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); + pvt = edac_align_ptr(&ptr, sz_pvt, 1); + size = ((unsigned long)pvt) + sz_pvt; edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", size, @@ -374,10 +364,6 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, * rather than an imaginary chunk of memory located at address 0. */ layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); - for (i = 0; i < n_layers; i++) { - mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i])); - mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i])); - } pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; /* setup index and various internal pointers */ @@ -908,53 +894,31 @@ const char *edac_layer_name[] = { EXPORT_SYMBOL_GPL(edac_layer_name); static void edac_inc_ce_error(struct mem_ctl_info *mci, - bool enable_per_layer_report, const int pos[EDAC_MAX_LAYERS], const u16 count) { - int i, index = 0; + struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); mci->ce_mc += count; - if (!enable_per_layer_report) { + if (dimm) + dimm->ce_count += count; + else mci->ce_noinfo_count += count; - return; - } - - for (i = 0; i < mci->n_layers; i++) { - if (pos[i] < 0) - break; - index += pos[i]; - mci->ce_per_layer[i][index] += count; - - if (i < mci->n_layers - 1) - index *= mci->layers[i + 1].size; - } } static void edac_inc_ue_error(struct mem_ctl_info *mci, - bool enable_per_layer_report, const int pos[EDAC_MAX_LAYERS], const u16 count) { - int i, index = 0; + struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); mci->ue_mc += count; - if (!enable_per_layer_report) { + if (dimm) + dimm->ue_count += count; + else mci->ue_noinfo_count += count; - return; - } - - for (i = 0; i < mci->n_layers; i++) { - if (pos[i] < 0) - break; - index += pos[i]; - mci->ue_per_layer[i][index] += count; - - if (i < mci->n_layers - 1) - index *= mci->layers[i + 1].size; - } } static void edac_ce_error(struct mem_ctl_info *mci, @@ -965,7 +929,6 @@ static void edac_ce_error(struct mem_ctl_info *mci, const char *label, const char *detail, const char *other_detail, - const bool enable_per_layer_report, const unsigned long page_frame_number, const unsigned long offset_in_page, long grain) @@ -988,7 +951,7 @@ static void edac_ce_error(struct mem_ctl_info *mci, error_count, msg, msg_aux, label, location, detail); } - edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); + edac_inc_ce_error(mci, pos, error_count); if (mci->scrub_mode == SCRUB_SW_SRC) { /* @@ -1018,8 +981,7 @@ static void edac_ue_error(struct mem_ctl_info *mci, const char *location, const char *label, const char *detail, - const char *other_detail, - const bool enable_per_layer_report) + const char *other_detail) { char *msg_aux = ""; @@ -1048,7 +1010,7 @@ static void edac_ue_error(struct mem_ctl_info *mci, msg, msg_aux, label, location, detail); } - edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); + edac_inc_ue_error(mci, pos, error_count); } void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, @@ -1064,16 +1026,16 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", e->page_frame_number, e->offset_in_page, e->grain, e->syndrome); - edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label, - detail, e->other_detail, e->enable_per_layer_report, + edac_ce_error(mci, e->error_count, pos, e->msg, e->location, + e->label, detail, e->other_detail, e->page_frame_number, e->offset_in_page, e->grain); } else { snprintf(detail, sizeof(detail), "page:0x%lx offset:0x%lx grain:%ld", e->page_frame_number, e->offset_in_page, e->grain); - edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label, - detail, e->other_detail, e->enable_per_layer_report); + edac_ue_error(mci, e->error_count, pos, e->msg, e->location, + e->label, detail, e->other_detail); } @@ -1099,6 +1061,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, int i, n_labels = 0; u8 grain_bits; struct edac_raw_error_desc *e = &mci->error_desc; + bool any_memory = true; edac_dbg(3, "MC%d\n", mci->mc_idx); @@ -1116,9 +1079,9 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, /* * Check if the event report is consistent and if the memory - * location is known. If it is known, enable_per_layer_report will be - * true, the DIMM(s) label info will be filled and the per-layer - * error counters will be incremented. + * location is known. If it is known, the DIMM(s) label info + * will be filled and the DIMM's error counters will be + * incremented. */ for (i = 0; i < mci->n_layers; i++) { if (pos[i] >= (int)mci->layers[i].size) { @@ -1136,7 +1099,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, pos[i] = -1; } if (pos[i] >= 0) - e->enable_per_layer_report = true; + any_memory = false; } /* @@ -1166,16 +1129,17 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, e->grain = dimm->grain; /* - * If the error is memory-controller wide, there's no need to - * seek for the affected DIMMs because the whole - * channel/memory controller/... may be affected. - * Also, don't show errors for empty DIMM slots. + * If the error is memory-controller wide, there's no + * need to seek for the affected DIMMs because the + * whole channel/memory controller/... may be + * affected. Also, don't show errors for empty DIMM + * slots. */ - if (!e->enable_per_layer_report || !dimm->nr_pages) + if (any_memory || !dimm->nr_pages) continue; if (n_labels >= EDAC_MAX_LABELS) { - e->enable_per_layer_report = false; + any_memory = true; break; } n_labels++; @@ -1205,7 +1169,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, chan = -2; } - if (!e->enable_per_layer_report) { + if (any_memory) { strcpy(e->label, "any memory"); } else { edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 0367554e7437..8682df2f7f4f 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -556,10 +556,8 @@ static ssize_t dimmdev_ce_count_show(struct device *dev, char *data) { struct dimm_info *dimm = to_dimm(dev); - u32 count; - count = dimm->mci->ce_per_layer[dimm->mci->n_layers-1][dimm->idx]; - return sprintf(data, "%u\n", count); + return sprintf(data, "%u\n", dimm->ce_count); } static ssize_t dimmdev_ue_count_show(struct device *dev, @@ -567,10 +565,8 @@ static ssize_t dimmdev_ue_count_show(struct device *dev, char *data) { struct dimm_info *dimm = to_dimm(dev); - u32 count; - count = dimm->mci->ue_per_layer[dimm->mci->n_layers-1][dimm->idx]; - return sprintf(data, "%u\n", count); + return sprintf(data, "%u\n", dimm->ue_count); } /* dimm/rank attribute files */ @@ -666,7 +662,9 @@ static ssize_t mci_reset_counters_store(struct device *dev, const char *data, size_t count) { struct mem_ctl_info *mci = to_mci(dev); - int cnt, row, chan, i; + struct dimm_info *dimm; + int row, chan; + mci->ue_mc = 0; mci->ce_mc = 0; mci->ue_noinfo_count = 0; @@ -682,11 +680,9 @@ static ssize_t mci_reset_counters_store(struct device *dev, ri->channels[chan]->ce_count = 0; } - cnt = 1; - for (i = 0; i < mci->n_layers; i++) { - cnt *= mci->layers[i].size; - memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); - memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); + mci_for_each_dimm(mci, dimm) { + dimm->ue_count = 0; + dimm->ce_count = 0; } mci->start_time = jiffies; diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 842080d7b33a..e0b90c6d7d63 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -347,11 +347,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) mem_err->mem_dev_handle); index = get_dimm_smbios_index(mem_err->mem_dev_handle); - if (index >= 0) { + if (index >= 0) e->top_layer = index; - e->enable_per_layer_report = true; - } - } if (p > e->location) *(p - 1) = '\0'; diff --git a/include/linux/edac.h b/include/linux/edac.h index 8beb6e834be9..8e72222e50b0 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -383,6 +383,9 @@ struct dimm_info { unsigned int csrow, cschannel; /* Points to the old API data */ u16 smbios_handle; /* Handle for SMBIOS type 17 */ + + u32 ce_count; + u32 ue_count; }; /** @@ -453,8 +456,6 @@ struct errcount_attribute_data { * @location: location of the error * @label: label of the affected DIMM(s) * @other_detail: other driver-specific detail about the error - * @enable_per_layer_report: if false, the error affects all layers - * (typically, a memory controller error) */ struct edac_raw_error_desc { /* @@ -475,7 +476,6 @@ struct edac_raw_error_desc { unsigned long syndrome; const char *msg; const char *other_detail; - bool enable_per_layer_report; }; /* MEMORY controller information structure @@ -565,7 +565,6 @@ struct mem_ctl_info { */ u32 ce_noinfo_count, ue_noinfo_count; u32 ue_mc, ce_mc; - u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; struct completion complete; From patchwork Thu Oct 10 20:25:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175831 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792390ill; Thu, 10 Oct 2019 13:25:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwES7OG3wp+cp8hrF24uQdEOLJjLY1R0DCWfIFCXGhqVWGg7Oa7SJLbDbnpThklJm7a6RD0 X-Received: by 2002:a50:f198:: with SMTP id x24mr10587177edl.238.1570739137909; Thu, 10 Oct 2019 13:25:37 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739137; cv=pass; d=google.com; s=arc-20160816; b=Dv8PEJPb2nwPKjXWHGsHM+1SYJ2AVUGpvMbQHo2EN9gGFVjBUl4YtPa7qLLQxE06Z+ MrSB5M1QrWHbrLHMhQMYk7ZmY5mFZhCxKWD3MFMDZlTEeEdLojV6glNoABFP3j7VuO2d PC/LC3omRx0XB4q/6VZT+EbNay9/Kl7eTIN42+fS5v+7i99qsw3MhtDs0FZxt+oPRet9 uKKWIDbrixCwnNuQMYnj70kDr8YxWiDRHwUQC6skuTpiRb26bBoTlfa3h1x+to16hrBd DAyKoFpphWrwWpprMzIid3wNxXNaWn7SCL7O0KdjmMrNYklryuR9i5BUdJYYSyJ0PTy3 /mow== ARC-Message-Signature: i=2; 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The name is more handy, esp. when searching it in the code. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index c1e142643006..a893f793be8a 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -319,7 +319,7 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, unsigned int idx, size, tot_dimms = 1; unsigned int tot_csrows = 1, tot_channels = 1; void *pvt, *p, *ptr = NULL; - int i, j, row, chn, n, len; + int j, row, chn, n, len; bool per_rank = false; if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0)) @@ -329,14 +329,14 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, * Calculate the total amount of dimms and csrows/cschannels while * in the old API emulation mode */ - for (i = 0; i < n_layers; i++) { - tot_dimms *= layers[i].size; - if (layers[i].is_virt_csrow) - tot_csrows *= layers[i].size; + for (idx = 0; idx < n_layers; idx++) { + tot_dimms *= layers[idx].size; + if (layers[idx].is_virt_csrow) + tot_csrows *= layers[idx].size; else - tot_channels *= layers[i].size; + tot_channels *= layers[idx].size; - if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) + if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT) per_rank = true; } From patchwork Thu Oct 10 20:25:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175833 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792526ill; Thu, 10 Oct 2019 13:25:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwBB7C2xsxsglj4Q9BpNOBN9ajtePq9FHSA285zhSHwQwzHGAxhpsl8P45AO2Od9QKJy0Ft X-Received: by 2002:a17:906:c35a:: with SMTP id ci26mr9616630ejb.99.1570739146092; Thu, 10 Oct 2019 13:25:46 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739146; cv=pass; d=google.com; s=arc-20160816; b=fOOInEV+2f96P8cKC4+nXL+DPSWvT8rj1MFVp0gk13V5mlKkI+BVFogjKYeRz1Txcl lAgbJ2itFTqLVzS2n2T3d9V33ZTPLFC48cFzY8I0dhkVRj2OnAhWjPgH5civmI4R4gzT c/5bSavmrH0QKyD82Ft7wcg/bpzOqZB5yQEdwLc7AprKfnBitQhAZMzCxUBLXhyWPUUV u42zQrOwnl6TI9VaV/0GQQ5Acep8QE+25bvT9Bsj71ruiZs13DlITMRrdlY/lnsm44MO fxug4emsfWg/UVoKg7Q/vsKKycRAFgYS7a8qwKYFEoYbVVZog1hAlvwfmD3Yn+yoIm0a oMYw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=udLHPpggucCdSFBTZuve5nlLyoSgWVEWuchiYCsVC2I=; b=W8CCi8ZHxH9sODHfed5SneHRBjRSq/pdgloc4Ydby9OPo42ghPfAP5f+4BY7LhAqZY mMunMQnZfwGuIDwUZMFDz82QJr5mahSK/GIHovUPda1VjkHzePrOdjwh9jSAZhsxx3tg bz5+7XYWzv6pZ1iT4lO7YPnhLiuS15d98FiRl0PS7GKX3SUhEQn3SoyGVW63v85Zz3eU itApIZ7AegSoVeCbn1evDJKSwuxUzDlj6i9AyW/yIprVKjj0AqI/fj3jR9GditmxS/Dk ImVf1mTWwJdFYRl70qqZ3Rkx+0bxQPCsdsDN73piOeoyx7G91/EwZSlEMIIcipmH3y3y Hzuw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=e1si6GUE; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=ruNyvCfy; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Factor out code by moving it to the two new functions edac_mc_alloc_csrows() and edac_mc_alloc_dimms(). Do not move code yet for better review. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 104 +++++++++++++++++++++++++++-------------- 1 file changed, 69 insertions(+), 35 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index a893f793be8a..0db504cb3419 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -305,6 +305,9 @@ static void _edac_mc_free(struct mem_ctl_info *mci) kfree(mci); } +static int edac_mc_alloc_csrows(struct mem_ctl_info *mci); +static int edac_mc_alloc_dimms(struct mem_ctl_info *mci); + struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, unsigned int n_layers, struct edac_mc_layer *layers, @@ -312,14 +315,9 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, { struct mem_ctl_info *mci; struct edac_mc_layer *layer; - struct csrow_info *csr; - struct rank_info *chan; - struct dimm_info *dimm; - unsigned int pos[EDAC_MAX_LAYERS]; unsigned int idx, size, tot_dimms = 1; unsigned int tot_csrows = 1, tot_channels = 1; - void *pvt, *p, *ptr = NULL; - int j, row, chn, n, len; + void *pvt, *ptr = NULL; bool per_rank = false; if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0)) @@ -377,16 +375,43 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, mci->num_cschannel = tot_channels; mci->csbased = per_rank; + if (edac_mc_alloc_csrows(mci)) + goto error; + + if (edac_mc_alloc_dimms(mci)) + goto error; + + mci->op_state = OP_ALLOC; + + return mci; + +error: + _edac_mc_free(mci); + + return NULL; +} +EXPORT_SYMBOL_GPL(edac_mc_alloc); + +static int edac_mc_alloc_csrows(struct mem_ctl_info *mci) +{ + unsigned int tot_csrows = mci->nr_csrows; + unsigned int tot_channels = mci->num_cschannel; + unsigned int row, chn; + /* * Alocate and fill the csrow/channels structs */ mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); if (!mci->csrows) - goto error; + return -ENOMEM; + for (row = 0; row < tot_csrows; row++) { + struct csrow_info *csr; + csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); if (!csr) - goto error; + return -ENOMEM; + mci->csrows[row] = csr; csr->csrow_idx = row; csr->mci = mci; @@ -394,34 +419,51 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), GFP_KERNEL); if (!csr->channels) - goto error; + return -ENOMEM; for (chn = 0; chn < tot_channels; chn++) { + struct rank_info *chan; + chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); if (!chan) - goto error; + return -ENOMEM; + csr->channels[chn] = chan; chan->chan_idx = chn; chan->csrow = csr; } } + return 0; +} + +static int edac_mc_alloc_dimms(struct mem_ctl_info *mci) +{ + void *p; + unsigned int pos[EDAC_MAX_LAYERS]; + unsigned int row, chn, idx; + int layer; + /* * Allocate and fill the dimm structs */ - mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); + mci->dimms = kcalloc(mci->tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); if (!mci->dimms) - goto error; + return -ENOMEM; memset(&pos, 0, sizeof(pos)); row = 0; chn = 0; - for (idx = 0; idx < tot_dimms; idx++) { + for (idx = 0; idx < mci->tot_dimms; idx++) { + struct dimm_info *dimm; + struct rank_info *chan; + int n, len; + chan = mci->csrows[row]->channels[chn]; dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); if (!dimm) - goto error; + return -ENOMEM; mci->dimms[idx] = dimm; dimm->mci = mci; dimm->idx = idx; @@ -431,16 +473,16 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, */ len = sizeof(dimm->label); p = dimm->label; - n = snprintf(p, len, "mc#%u", mc_num); + n = snprintf(p, len, "mc#%u", mci->mc_idx); p += n; len -= n; - for (j = 0; j < n_layers; j++) { + for (layer = 0; layer < mci->n_layers; layer++) { n = snprintf(p, len, "%s#%u", - edac_layer_name[layers[j].type], - pos[j]); + edac_layer_name[mci->layers[layer].type], + pos[layer]); p += n; len -= n; - dimm->location[j] = pos[j]; + dimm->location[layer] = pos[layer]; if (len <= 0) break; @@ -452,39 +494,31 @@ struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, dimm->cschannel = chn; /* Increment csrow location */ - if (layers[0].is_virt_csrow) { + if (mci->layers[0].is_virt_csrow) { chn++; - if (chn == tot_channels) { + if (chn == mci->num_cschannel) { chn = 0; row++; } } else { row++; - if (row == tot_csrows) { + if (row == mci->nr_csrows) { row = 0; chn++; } } /* Increment dimm location */ - for (j = n_layers - 1; j >= 0; j--) { - pos[j]++; - if (pos[j] < layers[j].size) + for (layer = mci->n_layers - 1; layer >= 0; layer--) { + pos[layer]++; + if (pos[layer] < mci->layers[layer].size) break; - pos[j] = 0; + pos[layer] = 0; } } - mci->op_state = OP_ALLOC; - - return mci; - -error: - _edac_mc_free(mci); - - return NULL; + return 0; } -EXPORT_SYMBOL_GPL(edac_mc_alloc); void edac_mc_free(struct mem_ctl_info *mci) { From patchwork Thu Oct 10 20:25:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175845 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2793176ill; 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No further code changes. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 171 ++++++++++++++++++++--------------------- 1 file changed, 84 insertions(+), 87 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 0db504cb3419..6d880cf4d599 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -305,93 +305,6 @@ static void _edac_mc_free(struct mem_ctl_info *mci) kfree(mci); } -static int edac_mc_alloc_csrows(struct mem_ctl_info *mci); -static int edac_mc_alloc_dimms(struct mem_ctl_info *mci); - -struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, - unsigned int n_layers, - struct edac_mc_layer *layers, - unsigned int sz_pvt) -{ - struct mem_ctl_info *mci; - struct edac_mc_layer *layer; - unsigned int idx, size, tot_dimms = 1; - unsigned int tot_csrows = 1, tot_channels = 1; - void *pvt, *ptr = NULL; - bool per_rank = false; - - if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0)) - return NULL; - - /* - * Calculate the total amount of dimms and csrows/cschannels while - * in the old API emulation mode - */ - for (idx = 0; idx < n_layers; idx++) { - tot_dimms *= layers[idx].size; - if (layers[idx].is_virt_csrow) - tot_csrows *= layers[idx].size; - else - tot_channels *= layers[idx].size; - - if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT) - per_rank = true; - } - - /* Figure out the offsets of the various items from the start of an mc - * structure. We want the alignment of each item to be at least as - * stringent as what the compiler would provide if we could simply - * hardcode everything into a single struct. - */ - mci = edac_align_ptr(&ptr, sizeof(*mci), 1); - layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); - pvt = edac_align_ptr(&ptr, sz_pvt, 1); - size = ((unsigned long)pvt) + sz_pvt; - - edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", - size, - tot_dimms, - per_rank ? "ranks" : "dimms", - tot_csrows * tot_channels); - - mci = kzalloc(size, GFP_KERNEL); - if (mci == NULL) - return NULL; - - /* Adjust pointers so they point within the memory we just allocated - * rather than an imaginary chunk of memory located at address 0. - */ - layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); - pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; - - /* setup index and various internal pointers */ - mci->mc_idx = mc_num; - mci->tot_dimms = tot_dimms; - mci->pvt_info = pvt; - mci->n_layers = n_layers; - mci->layers = layer; - memcpy(mci->layers, layers, sizeof(*layer) * n_layers); - mci->nr_csrows = tot_csrows; - mci->num_cschannel = tot_channels; - mci->csbased = per_rank; - - if (edac_mc_alloc_csrows(mci)) - goto error; - - if (edac_mc_alloc_dimms(mci)) - goto error; - - mci->op_state = OP_ALLOC; - - return mci; - -error: - _edac_mc_free(mci); - - return NULL; -} -EXPORT_SYMBOL_GPL(edac_mc_alloc); - static int edac_mc_alloc_csrows(struct mem_ctl_info *mci) { unsigned int tot_csrows = mci->nr_csrows; @@ -520,6 +433,90 @@ static int edac_mc_alloc_dimms(struct mem_ctl_info *mci) return 0; } +struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, + unsigned int n_layers, + struct edac_mc_layer *layers, + unsigned int sz_pvt) +{ + struct mem_ctl_info *mci; + struct edac_mc_layer *layer; + unsigned int idx, size, tot_dimms = 1; + unsigned int tot_csrows = 1, tot_channels = 1; + void *pvt, *ptr = NULL; + bool per_rank = false; + + if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0)) + return NULL; + + /* + * Calculate the total amount of dimms and csrows/cschannels while + * in the old API emulation mode + */ + for (idx = 0; idx < n_layers; idx++) { + tot_dimms *= layers[idx].size; + if (layers[idx].is_virt_csrow) + tot_csrows *= layers[idx].size; + else + tot_channels *= layers[idx].size; + + if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT) + per_rank = true; + } + + /* Figure out the offsets of the various items from the start of an mc + * structure. We want the alignment of each item to be at least as + * stringent as what the compiler would provide if we could simply + * hardcode everything into a single struct. + */ + mci = edac_align_ptr(&ptr, sizeof(*mci), 1); + layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); + pvt = edac_align_ptr(&ptr, sz_pvt, 1); + size = ((unsigned long)pvt) + sz_pvt; + + edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", + size, + tot_dimms, + per_rank ? "ranks" : "dimms", + tot_csrows * tot_channels); + + mci = kzalloc(size, GFP_KERNEL); + if (mci == NULL) + return NULL; + + /* Adjust pointers so they point within the memory we just allocated + * rather than an imaginary chunk of memory located at address 0. + */ + layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); + pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; + + /* setup index and various internal pointers */ + mci->mc_idx = mc_num; + mci->tot_dimms = tot_dimms; + mci->pvt_info = pvt; + mci->n_layers = n_layers; + mci->layers = layer; + memcpy(mci->layers, layers, sizeof(*layer) * n_layers); + mci->nr_csrows = tot_csrows; + mci->num_cschannel = tot_channels; + mci->csbased = per_rank; + + if (edac_mc_alloc_csrows(mci)) + goto error; + + if (edac_mc_alloc_dimms(mci)) + goto error; + + mci->op_state = OP_ALLOC; + + return mci; + +error: + _edac_mc_free(mci); + + return NULL; +} +EXPORT_SYMBOL_GPL(edac_mc_alloc); + void edac_mc_free(struct mem_ctl_info *mci) { edac_dbg(1, "\n"); From patchwork Thu Oct 10 20:25:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175834 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792542ill; Thu, 10 Oct 2019 13:25:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqzZBpayOzTQgynNhcaZAJMgiDV3zqkUSewGSz9gUvSiyXsLNl4O/jUIBoPthSYB4Kpqs9hU X-Received: by 2002:a17:906:95c2:: with SMTP id n2mr9769745ejy.296.1570739147133; Thu, 10 Oct 2019 13:25:47 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739147; cv=pass; d=google.com; s=arc-20160816; b=Or9tJpHtyILZoXDHNNr/CfU7C2KKgdZGmuigGGMSyZdZ9zgo46PZUXkRbsWlN5jzNf 1REOCXoiykznsgr+jYOT2fSRPHyM7BUj9S+63354Vf5Xwn+aG1SS/1VRk+DymHmYz+OM PpHmX6cy2MEsp1tnEgpvfwhhKTTQfzmCyzvMf4aoBGL+RQmrB3sGEc0RS18qXa/rU4sa SMtQGQ+tKqMAghAzX0s38Mw/5wOHNSVtGCiWU6wYoEw8ndjmUq+35DCEymAsu0DVAnJU 4YfMSk6vTyAy59z18dxCrnBa9gGqbalt2GZWCkeMtancWlaUCR/JTvTS/PaqBnCkj4E/ AC1w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=LxWrU3SAxvcssVNIkGuJbn/CCcLwtALrnh0Yb/egWUc=; b=kx8I6oeGjD3O/TWAWT03sKVwI08ZDz3Xu2VpmZPqRkWjSVppHojvT/0yEgDwR0TGQH Tkk2SuL9OxHjapNX6K0cG/6iD0r86leGoGeaiVfZdCLZo9LZ7sNyQlQkDqZuVCaCgpI+ 98M1On8JCRuzZEyXkIlatzLROXQb/Uhg6uKj5XU9BqcZBWK61xMXXJ+JMCeEX7jD2G7Z rEJi8JaOA7fxonLFhm6jdgbwWFzhYICOxu0ZFsUlj/ZcRcEXAjXotShlyV7kXwnabgth FVuZxmfVhXriQZng7bNwbFPqDmarJlRM8R1A3WN00wgmdLeTpQtH9ZtFUWwO465tLnGR GGaQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b="TuR+Dtq/"; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=HZHGnUrZ; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Rework those functions to use the dimm handle directly. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 28 +++++++++++++--------------- drivers/edac/edac_mc.h | 2 ++ drivers/edac/ghes_edac.c | 6 +++++- 3 files changed, 20 insertions(+), 16 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 6d880cf4d599..cdfb383f7a35 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -925,11 +925,9 @@ const char *edac_layer_name[] = { EXPORT_SYMBOL_GPL(edac_layer_name); static void edac_inc_ce_error(struct mem_ctl_info *mci, - const int pos[EDAC_MAX_LAYERS], + struct dimm_info *dimm, const u16 count) { - struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); - mci->ce_mc += count; if (dimm) @@ -939,11 +937,9 @@ static void edac_inc_ce_error(struct mem_ctl_info *mci, } static void edac_inc_ue_error(struct mem_ctl_info *mci, - const int pos[EDAC_MAX_LAYERS], - const u16 count) + struct dimm_info *dimm, + const u16 count) { - struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]); - mci->ue_mc += count; if (dimm) @@ -953,8 +949,8 @@ static void edac_inc_ue_error(struct mem_ctl_info *mci, } static void edac_ce_error(struct mem_ctl_info *mci, + struct dimm_info *dimm, const u16 error_count, - const int pos[EDAC_MAX_LAYERS], const char *msg, const char *location, const char *label, @@ -982,7 +978,7 @@ static void edac_ce_error(struct mem_ctl_info *mci, error_count, msg, msg_aux, label, location, detail); } - edac_inc_ce_error(mci, pos, error_count); + edac_inc_ce_error(mci, dimm, error_count); if (mci->scrub_mode == SCRUB_SW_SRC) { /* @@ -1006,8 +1002,8 @@ static void edac_ce_error(struct mem_ctl_info *mci, } static void edac_ue_error(struct mem_ctl_info *mci, + struct dimm_info *dimm, const u16 error_count, - const int pos[EDAC_MAX_LAYERS], const char *msg, const char *location, const char *label, @@ -1041,15 +1037,15 @@ static void edac_ue_error(struct mem_ctl_info *mci, msg, msg_aux, label, location, detail); } - edac_inc_ue_error(mci, pos, error_count); + edac_inc_ue_error(mci, dimm, error_count); } void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info *mci, + struct dimm_info *dimm, struct edac_raw_error_desc *e) { char detail[80]; - int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; /* Memory type dependent details about the error */ if (type == HW_EVENT_ERR_CORRECTED) { @@ -1057,7 +1053,7 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", e->page_frame_number, e->offset_in_page, e->grain, e->syndrome); - edac_ce_error(mci, e->error_count, pos, e->msg, e->location, + edac_ce_error(mci, dimm, e->error_count, e->msg, e->location, e->label, detail, e->other_detail, e->page_frame_number, e->offset_in_page, e->grain); } else { @@ -1065,7 +1061,7 @@ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, "page:0x%lx offset:0x%lx grain:%ld", e->page_frame_number, e->offset_in_page, e->grain); - edac_ue_error(mci, e->error_count, pos, e->msg, e->location, + edac_ue_error(mci, dimm, e->error_count, e->msg, e->location, e->label, detail, e->other_detail); } @@ -1245,6 +1241,8 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, grain_bits, e->syndrome, e->other_detail); - edac_raw_mc_handle_error(type, mci, e); + dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); + + edac_raw_mc_handle_error(type, mci, dimm, e); } EXPORT_SYMBOL_GPL(edac_mc_handle_error); diff --git a/drivers/edac/edac_mc.h b/drivers/edac/edac_mc.h index 02aac5c61d00..2c3e2fbcedc4 100644 --- a/drivers/edac/edac_mc.h +++ b/drivers/edac/edac_mc.h @@ -214,6 +214,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, * * @type: severity of the error (CE/UE/Fatal) * @mci: a struct mem_ctl_info pointer + * @dimm: a struct dimm_info pointer * @e: error description * * This raw function is used internally by edac_mc_handle_error(). It should @@ -222,6 +223,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, */ void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, struct mem_ctl_info *mci, + struct dimm_info *dimm, struct edac_raw_error_desc *e); /** diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index e0b90c6d7d63..4f5721cf4380 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -193,6 +193,7 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) { + struct dimm_info *dimm; enum hw_event_mc_err_type type; struct edac_raw_error_desc *e; struct mem_ctl_info *mci; @@ -437,7 +438,10 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, grain_bits, e->syndrome, pvt->detail_location); - edac_raw_mc_handle_error(type, mci, e); + dimm = edac_get_dimm_by_index(mci, e->top_layer); + + edac_raw_mc_handle_error(type, mci, dimm, e); + spin_unlock_irqrestore(&ghes_lock, flags); } From patchwork Thu Oct 10 20:25:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175843 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2793033ill; Thu, 10 Oct 2019 13:26:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqyHjYe87Zd04SU1C0SCtFKE5Yp+cHViIeO0Jt7ACMzdxPKXa/A3phe6ySLgWvuj3PpaoI5j X-Received: by 2002:aa7:db55:: with SMTP id n21mr10073454edt.1.1570739180239; Thu, 10 Oct 2019 13:26:20 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739180; cv=pass; d=google.com; s=arc-20160816; b=jTJ/BQZyUUlsmy7ohsckg2fjka+1t8HGlVPtfnsTiiD49YIzIOUFGU6VH55mBPw7Q3 cHmJNMx0uU4SZevSZiAF8V6V54zLYNOP7Kzf1w7RIzDs3fYu5vQErW2F4J9e5/YUpByl Cft/AHe3qgNtWwb2EsQEo8JNG/h82ljwrqX37VU6zA+Ozu0Ppg+WsDFoPIE9iUguVzsB eMnRgqeTDorKzQEBgFuonTC0BFUqKSsEaZsDs6lzI3QBlAlJ1614aDRmZcx1JYQWlD3Y cD3Wsn5qYKmtT/oiEcnFf6QWWBRqsg2ZeddUzhcMU3Uo/gkHkrNEZ+5OeJKrnwlSMa1c EqBw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=PrN+D2+F/4T4BJ7uzHGTcMzHiMC+SlavYnnXoNJrkY8=; b=UgNTBukeHLypLRNpCF6CViyaJWWObBC7Eag+YM30vk/7Q8pHmGV+DCDywJrlpsxZ4E t2S7qJTCHTNH8jIbnaVBWGMDPWKvs+WdDRdflE0nXDTR25RLb6Tu/UebKD0cRQKeAVPN sK7MqeQ2eBe4fx45N7fq9tMhT47WKmAietZWNBtCEZ7mEvulbFTDSwvkYTnJH17FcaYi r3+flRwmiuUT4ObLGjnSwtpApDiKkXKCtL/ENNYqw81Kt+WiUXyuWZFGFgnEEdRMC0k3 nxywPQUffsuvonIsDKW58sPHtWTuz6KKTUoeRgeZD4CVGHhd++lD4PKxaZyoepq08OBB Gihg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=jU0XyTVL; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=ZewkXz4x; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Remove that comment. Signed-off-by: Robert Richter --- include/linux/edac.h | 5 ----- 1 file changed, 5 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/include/linux/edac.h b/include/linux/edac.h index 8e72222e50b0..4d9673954856 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -458,15 +458,10 @@ struct errcount_attribute_data { * @other_detail: other driver-specific detail about the error */ struct edac_raw_error_desc { - /* - * NOTE: everything before grain won't be cleaned by - * edac_raw_error_desc_clean() - */ char location[LOCATION_SIZE]; char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS]; long grain; - /* the vars below and grain will be cleaned on every new error report */ u16 error_count; int top_layer; int mid_layer; From patchwork Thu Oct 10 20:25:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175842 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792976ill; Thu, 10 Oct 2019 13:26:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqxJVBwYoqTltnvtKMaqOuhUZMUzAFSsxeyMAQwG+wsVjKtTKwmb8zgCZu2LujW7ysbY3Exb X-Received: by 2002:a17:906:3009:: with SMTP id 9mr10276627ejz.124.1570739176165; Thu, 10 Oct 2019 13:26:16 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739176; cv=pass; d=google.com; s=arc-20160816; b=m3YgSSXa/tKZVIffIf/HQflDiNzGiFOudUy4lKHgDRqaixki91LWFFnfU0EijVMiYB wiTArW74d9w3uJO7YgE2mI7xMoOTJa/2xJ6dwnFG/LOUJaeA8HAmlKpJzAE5kpq4eK9i l998uniQNirFTLnoknciiEU+rP7U60OIQy9onkUrQm6cN1FWHH+k3+qevxEE+M55gPjL ID7xvnb3aX+fp4AUbaVjS3DudOEsQMeva8ylH7iIHc1CQ8L4cQGXVKTOxxfkLovi78ZI EPSwiOd8v4kCsUkTmfk+x8Y3J4dEjFBEFbQvgSVibDR3jqThBP5mxSHLI1neb2PpM+Gn vabw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=hUFrqrpJtWF5tDX2FhMkctljMgIDndlf9B9L9MFguFo=; b=XTDSIk2gjg2PKivXIjaPkS0+Pi6QyLgZvANlAyo1Fvy2Jo+ztpYMxLqzRDB+fB0e25 wUdhj7s4tCwwvU5zAE6vZ8yHSElyGviKUUo4KBVI7Ig5b0/4lKEaEjdyiAcfOPmCp7I/ VypO78Zh0svMOLlIJTqPmJnkirw5pImvaVr0YntDKxn8NT9BTc3LlBNwmYQxj+haiFLw 77XIB8g3FI54oNP7g/Abi0eNo78SqrsU5R4KaV7zw2o5Cboi9qKsZokQ4ToPa8kmISMZ dNcDnJI8S91TuRtpaDTVipBlO5QXFCJue7U9vT+9crzeZo16tsdBmgZ5DBp++HP92ozj WnHA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=upvv9xGL; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=EicBnZBw; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This makes the type parameter of edac_raw_mc_handle_error() obsolete. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 8 ++++---- drivers/edac/edac_mc.h | 4 +--- drivers/edac/ghes_edac.c | 13 ++++++------- include/linux/edac.h | 1 + 4 files changed, 12 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index cdfb383f7a35..ca206854b8ee 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1040,15 +1040,14 @@ static void edac_ue_error(struct mem_ctl_info *mci, edac_inc_ue_error(mci, dimm, error_count); } -void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, - struct mem_ctl_info *mci, +void edac_raw_mc_handle_error(struct mem_ctl_info *mci, struct dimm_info *dimm, struct edac_raw_error_desc *e) { char detail[80]; /* Memory type dependent details about the error */ - if (type == HW_EVENT_ERR_CORRECTED) { + if (e->type == HW_EVENT_ERR_CORRECTED) { snprintf(detail, sizeof(detail), "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", e->page_frame_number, e->offset_in_page, @@ -1095,6 +1094,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, /* Fills the error report buffer */ memset(e, 0, sizeof (*e)); e->error_count = error_count; + e->type = type; e->top_layer = top_layer; e->mid_layer = mid_layer; e->low_layer = low_layer; @@ -1243,6 +1243,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); - edac_raw_mc_handle_error(type, mci, dimm, e); + edac_raw_mc_handle_error(mci, dimm, e); } EXPORT_SYMBOL_GPL(edac_mc_handle_error); diff --git a/drivers/edac/edac_mc.h b/drivers/edac/edac_mc.h index 2c3e2fbcedc4..a8f1b5b5e873 100644 --- a/drivers/edac/edac_mc.h +++ b/drivers/edac/edac_mc.h @@ -212,7 +212,6 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, * edac_raw_mc_handle_error() - Reports a memory event to userspace without * doing anything to discover the error location. * - * @type: severity of the error (CE/UE/Fatal) * @mci: a struct mem_ctl_info pointer * @dimm: a struct dimm_info pointer * @e: error description @@ -221,8 +220,7 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, * only be called directly when the hardware error come directly from BIOS, * like in the case of APEI GHES driver. */ -void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, - struct mem_ctl_info *mci, +void edac_raw_mc_handle_error(struct mem_ctl_info *mci, struct dimm_info *dimm, struct edac_raw_error_desc *e); diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 4f5721cf4380..1db1c012bed9 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -194,7 +194,6 @@ static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg) void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) { struct dimm_info *dimm; - enum hw_event_mc_err_type type; struct edac_raw_error_desc *e; struct mem_ctl_info *mci; struct ghes_edac_pvt *pvt = ghes_pvt; @@ -232,17 +231,17 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) switch (sev) { case GHES_SEV_CORRECTED: - type = HW_EVENT_ERR_CORRECTED; + e->type = HW_EVENT_ERR_CORRECTED; break; case GHES_SEV_RECOVERABLE: - type = HW_EVENT_ERR_UNCORRECTED; + e->type = HW_EVENT_ERR_UNCORRECTED; break; case GHES_SEV_PANIC: - type = HW_EVENT_ERR_FATAL; + e->type = HW_EVENT_ERR_FATAL; break; default: case GHES_SEV_NO: - type = HW_EVENT_ERR_INFO; + e->type = HW_EVENT_ERR_INFO; } edac_dbg(1, "error validation_bits: 0x%08llx\n", @@ -433,14 +432,14 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) grain_bits = fls_long(e->grain); snprintf(pvt->detail_location, sizeof(pvt->detail_location), "APEI location: %s %s", e->location, e->other_detail); - trace_mc_event(type, e->msg, e->label, e->error_count, + trace_mc_event(e->type, e->msg, e->label, e->error_count, mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, grain_bits, e->syndrome, pvt->detail_location); dimm = edac_get_dimm_by_index(mci, e->top_layer); - edac_raw_mc_handle_error(type, mci, dimm, e); + edac_raw_mc_handle_error(mci, dimm, e); spin_unlock_irqrestore(&ghes_lock, flags); } diff --git a/include/linux/edac.h b/include/linux/edac.h index 4d9673954856..587c53b87fdf 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -463,6 +463,7 @@ struct edac_raw_error_desc { long grain; u16 error_count; + enum hw_event_mc_err_type type; int top_layer; int mid_layer; int low_layer; From patchwork Thu Oct 10 20:25:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175841 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792942ill; 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Thu, 10 Oct 2019 20:25:31 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763%3]) with mapi id 15.20.2327.026; Thu, 10 Oct 2019 20:25:31 +0000 From: Robert Richter To: Borislav Petkov , Mauro Carvalho Chehab , Tony Luck CC: James Morse , Robert Richter , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH 13/19] EDAC, mc: Determine mci pointer from the error descriptor Thread-Topic: [PATCH 13/19] EDAC, mc: Determine mci pointer from the error descriptor Thread-Index: AQHVf6jcZfW9FXTSyEObM2Ya6k8l+g== Date: Thu, 10 Oct 2019 20:25:31 +0000 Message-ID: <20191010202418.25098-14-rrichter@marvell.com> References: <20191010202418.25098-1-rrichter@marvell.com> In-Reply-To: <20191010202418.25098-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0336.eurprd05.prod.outlook.com (2603:10a6:7:92::31) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:165::10) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [31.208.96.227] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 27781cbd-de3b-4efe-e67f-08d74dbfff2b x-ms-traffictypediagnostic: MN2PR18MB2447: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; 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Create a function error_desc_to_mci() to determine the corresponding mci from an error descriptor. This eases the parameter list of edac_raw_mc_handle_ error() as the mci pointer do not need to be passed any longer. While at it, reorder parameters of edac_raw_mc_handle_error(). Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 13 +++++++++---- drivers/edac/edac_mc.h | 8 +++----- drivers/edac/ghes_edac.c | 2 +- 3 files changed, 13 insertions(+), 10 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index ca206854b8ee..9e8c5716a8c0 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1040,10 +1040,15 @@ static void edac_ue_error(struct mem_ctl_info *mci, edac_inc_ue_error(mci, dimm, error_count); } -void edac_raw_mc_handle_error(struct mem_ctl_info *mci, - struct dimm_info *dimm, - struct edac_raw_error_desc *e) +static struct mem_ctl_info *error_desc_to_mci(struct edac_raw_error_desc *e) +{ + return container_of(e, struct mem_ctl_info, error_desc); +} + +void edac_raw_mc_handle_error(struct edac_raw_error_desc *e, + struct dimm_info *dimm) { + struct mem_ctl_info *mci = error_desc_to_mci(e); char detail[80]; /* Memory type dependent details about the error */ @@ -1243,6 +1248,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); - edac_raw_mc_handle_error(mci, dimm, e); + edac_raw_mc_handle_error(e, dimm); } EXPORT_SYMBOL_GPL(edac_mc_handle_error); diff --git a/drivers/edac/edac_mc.h b/drivers/edac/edac_mc.h index a8f1b5b5e873..3b01d5d9d7bc 100644 --- a/drivers/edac/edac_mc.h +++ b/drivers/edac/edac_mc.h @@ -212,17 +212,15 @@ extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, * edac_raw_mc_handle_error() - Reports a memory event to userspace without * doing anything to discover the error location. * - * @mci: a struct mem_ctl_info pointer - * @dimm: a struct dimm_info pointer * @e: error description + * @dimm: a struct dimm_info pointer * * This raw function is used internally by edac_mc_handle_error(). It should * only be called directly when the hardware error come directly from BIOS, * like in the case of APEI GHES driver. */ -void edac_raw_mc_handle_error(struct mem_ctl_info *mci, - struct dimm_info *dimm, - struct edac_raw_error_desc *e); +void edac_raw_mc_handle_error(struct edac_raw_error_desc *e, + struct dimm_info *dimm); /** * edac_mc_handle_error() - Reports a memory event to userspace. diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 1db1c012bed9..8078d4ec9631 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -439,7 +439,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) dimm = edac_get_dimm_by_index(mci, e->top_layer); - edac_raw_mc_handle_error(mci, dimm, e); + edac_raw_mc_handle_error(e, dimm); spin_unlock_irqrestore(&ghes_lock, flags); } From patchwork Thu Oct 10 20:25:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175835 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792620ill; Thu, 10 Oct 2019 13:25:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqzFBQvHlgzvSf9XzvJY2hLof6l/ZW12DSzsmRbwoZVgkMVklU18SYrvDVjs3o7bmVvOQds3 X-Received: by 2002:a50:cbcd:: with SMTP id l13mr9962340edi.18.1570739151907; Thu, 10 Oct 2019 13:25:51 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739151; cv=pass; d=google.com; s=arc-20160816; b=SmrVsSd4HgaIld6W4e+LpnPlm4fUPBzHAQPEN9qmxmq0tpOjfsCgSgTwRdGYt7RrJa ZwCmSNEsYuDfGddSghwpi5PoG1ujxSYB/RuCress2iIPNCl2XiIjK0IYiZj8EECI3CbU n9f2YVg37rgcdLU7fhS5cn4UTQqWiKgyP465nvegVDct1lUeOOpdxPKWBAg3/mrETQQI 2R6tdWS92vcUfnyyzNcF63nM6xv4kdCvSnlaBAc8Ed7KRHPlSKd1yvqsBHA+B/+mWs4K 1o5Fbuj2U+P3XBJp8FL9tchnHJGTG1ZFyhLHxC/uCGq7l4uvF06NJb7+FipvdrphYCi1 L2Ew== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=r88CqJ4CRLirPG0YtAFyxOsUcnLoxZsotDSdCKrEUjA=; b=OhF3Ree959LDm6VGoTkD6kZTNNsZXYVCAF797NXdraRXQ0hvdhdTgOslvTHkHfe1VM se53D8XKgZcHYp2ju4JEFaIWQmHIKiCNcEPGwbHXjRM2FLy0wyH1YjmjGEHWNVcat3X/ A3KXXZsnBp9I+NkUtXXj14Pz0jRtCzZMxaIpJoPXseR1EplmjzaaQvQGkaIH3j154VIP b9rPPt1iL7t+iWjjNfbjsOg472ya5e25d4z+7FA2MS6jf8PhNGePsn2M5jSP20mzg7Ns +gAjy18EwYO/BuvHkfagFA26DxKt2Ru2fiEek8dnuXRRhpYzYAtPtw3U2tSAw4KQP6cd F26w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=sXHG4WtS; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=nrFaLmk1; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This better separates code and reduces the indentation level. No functional changes. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 40 +++++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 9e8c5716a8c0..3779204c0e21 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1045,6 +1045,26 @@ static struct mem_ctl_info *error_desc_to_mci(struct edac_raw_error_desc *e) return container_of(e, struct mem_ctl_info, error_desc); } +static void edac_inc_csrow(struct edac_raw_error_desc *e, int row, int chan) +{ + struct mem_ctl_info *mci = error_desc_to_mci(e); + u16 count = e->error_count; + enum hw_event_mc_err_type type = e->type; + + if (row < 0) + return; + + edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); + + if (type == HW_EVENT_ERR_CORRECTED) { + mci->csrows[row]->ce_count += count; + if (chan >= 0) + mci->csrows[row]->channels[chan]->ce_count += count; + } else { + mci->csrows[row]->ue_count += count; + } +} + void edac_raw_mc_handle_error(struct edac_raw_error_desc *e, struct dimm_info *dimm) { @@ -1201,22 +1221,12 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, chan = -2; } - if (any_memory) { + if (any_memory) strcpy(e->label, "any memory"); - } else { - edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); - if (p == e->label) - strcpy(e->label, "unknown memory"); - if (type == HW_EVENT_ERR_CORRECTED) { - if (row >= 0) { - mci->csrows[row]->ce_count += error_count; - if (chan >= 0) - mci->csrows[row]->channels[chan]->ce_count += error_count; - } - } else - if (row >= 0) - mci->csrows[row]->ue_count += error_count; - } + else if (!*e->label) + strcpy(e->label, "unknown memory"); + + edac_inc_csrow(e, row, chan); /* Fill the RAM location data */ p = e->location; From patchwork Thu Oct 10 20:25:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175840 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792885ill; Thu, 10 Oct 2019 13:26:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwW6eZnbVBPq8EQYWLXnaB8O/6A9J6BDxrQQbSI2ie8R7yAjrF/kdvQexxf5gDZ0Uv961x0 X-Received: by 2002:a05:6402:7ca:: with SMTP id u10mr10032173edy.20.1570739169636; Thu, 10 Oct 2019 13:26:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739169; cv=pass; d=google.com; s=arc-20160816; b=Pl6AsMN1pBGZTuBTZMm9Tho9aTVF2Pr/hAVJ2TE9swvUR8oqzc3IgpolS/gbq9wRis Phpp4joGPXxchD+FAdcJ3GvLwgxqZytrZH12as1Hvivpdm0bqZ/c0sCK2PuM9/E38KZf JJedGiRx2RI+3FZ7wk8KX/Q9I1wBk17JRS/rSk6Kf++K9ouHOMbJCsgswrRSoNIH6ZV0 pXxcSL68jK4SRIDWN5BGnn8I53yPS9W0fC+UVCfgzt+792Jp3Do8lMcxndgBd9aT1oCf 5irae3kTgo6gxznHW7H9jx51kKszFz12HjYMhOAV4tG+CpFyXyNM2yMJF3V5jEkW6vry 5CEQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=o1b3djdTg/nm2ISJxuGuvT21IZ/8pVHiu31rfh0Knno=; b=o3W2QhQWsbvpZdEDeh5A29IXYVjWh6DqwjZA5RfOSHAtUUUbH53vTZmJpLZgQ5xA6+ VfL+uE9tPZw0siM1thYtHTN5VAOQ0+rsVo3ibb+G2kbs+DpfsMYmX1EMABwfwqlNQsmH WNWTZdUXiGsFZyt0crDG2xZ8ARdkp0ckNb2mTC4FWkhRftDjK7HARFOO0I1wKH5Zhhrm opZUS/hnVD/ifi/VCVanrWXNHmXNcw5/x3ZcA92sKRdgHTryzRg7zmzu9ehim2GS7ZTk APv1AOqntPF5bg0e/RAZvM3OWmewt8sf2qrgxTGxOM+hvNuHjkLam/1Gti/DipiHZwzE elkw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=MbSxp9Q6; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=Mlu0HnkI; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Reviewed-by: James Morse Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 8078d4ec9631..851aad92e42d 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -309,8 +309,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) /* Error address */ if (mem_err->validation_bits & CPER_MEM_VALID_PA) { - e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT; - e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK; + e->page_frame_number = PHYS_PFN(mem_err->physical_addr); + e->offset_in_page = offset_in_page(mem_err->physical_addr); } /* Error grain */ From patchwork Thu Oct 10 20:25:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175838 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792765ill; Thu, 10 Oct 2019 13:26:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqyYGrMNtJMTGr8KmJt17QdjW1+ZNzBdqLtKbaZ4L6Pp260TnwEzETH+GP51PLf6dj7S+5r1 X-Received: by 2002:a05:6402:13d5:: with SMTP id a21mr10306021edx.242.1570739161576; Thu, 10 Oct 2019 13:26:01 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739161; cv=pass; d=google.com; s=arc-20160816; b=tTA+JbFsKn2YHANjjXyTLOoY2aLEBZUKvkGGz7lVAh/GoG/aXpCUmAFBnH4cX8EJrl CwXYzsXZ//9XSfkzgBV5OpHMdBTIoxFlV/k4mpPSbsUvJEcEzkPjUbs8RewYnIOtNyPO wEoaDNaenS7mTY8oOsyoiQIcZdCCq2RZVvGr72y/64ll5ok7D70VAIDeWTq3yF8FbaZi Am2r6wFWVU7gQ6KAaOiObQaRGmKiyCK4zGIqs8SJuA5epHWXpjoZl9XbCvLy38Dy9oIB qchpcfhtglr+U1nrjEc2hYTnsyRV12f14SlbUXHFbLcO+O2hMesdmV4vX+9PoVprs2+6 rXUg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=FzPxPqi7Fp4/j2fd+EetHBwp1eY08PYShhNu5gCcwvI=; b=pDTiqWo6WxSW+it5MU7mdsRKqAET1Zv+u7+SxVse+wZ/gli/LX/mZ4lTN48OLjqOBK VsdFtYOPqZeDSWit46Yk50ettLAW0nkslXPSUoY99ZxyjerqbN6aNj/uR1v95jFUvrAK ABw0bYk8qJhNKsIVmgAVMukNoX77R9cjjKP5Nk0pTRaUk7bBVAkj90qF8/GoZyPILL+F v3+Q6z7OEnIvBR0GL75Z0UNCgOjheziCJoiJQBz/uA4zLekcUi7HThRgxrHac7yyaIrB hS8Ybh9PtgIVG1Ek0cpvo04lDgkBRzUsRVzdzPQIt7CKNDba9cF5g9159vwBUMygtwPV 1JzQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b="EAq/rFHD"; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=dcwTUyoy; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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x-forefront-prvs: 018632C080 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(376002)(39860400002)(366004)(346002)(136003)(199004)(189003)(6512007)(476003)(8936002)(25786009)(50226002)(8676002)(81156014)(81166006)(14444005)(7736002)(305945005)(256004)(486006)(14454004)(2616005)(6436002)(86362001)(66066001)(36756003)(66946007)(66476007)(66556008)(64756008)(66446008)(11346002)(446003)(71190400001)(71200400001)(6486002)(186003)(478600001)(5660300002)(386003)(316002)(3846002)(26005)(4326008)(6116002)(2906002)(52116002)(76176011)(99286004)(54906003)(110136005)(6506007)(102836004)(1076003); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB2447; H:MN2PR18MB3408.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: fHELFrIqXap6qXvSYpqt3rZn7xGtxL/MW6Qv7uoxN83COA2GXtUhjzKNuuvno0NEsiw6zlZYhDSBRbFRWLZsYH7J3+vwwRbF36QO/rca61m91g36kSbr22gBH8KlOgF781ExzrtZHz/6dctsCYQy+XgTx6fUq03ojHtFrUXd+COgUubxKZklQbdq1bNw8/hf+wmiQPkHSCKlyRoTHhc8XfJBp/3SJM66m5mCj5sPIitwNg6lJxY7sd9UaRk4cYaqYDWtez9nfa2Bht7/k4GVZ5kg5loyWVFEY+Z/mecVUxRgW8WF7aMcdOFwJSqUHiQamgP9sUY8UxcqdrgLSvxDCxVPi3aqzbCQYO12ZY/n1/OFceyxBLozv5k4a7Z6eIWYujMEOa6hABDsRT6fjHFTVT5IRQ984EJrLQjyKId23wU= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 115b99ff-b167-4d80-f7d3-08d74dc0029d X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Oct 2019 20:25:37.0950 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ibhXKI7bs8OW53Xl3GhIAKssPltUhO0gtJ9uFqom8euH39dZgphOEr8v+fEVJCqn25fSnXpsFI4C7gB5B+Wwjg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2447 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-10_07:2019-10-10,2019-10-10 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current code to convert a physical address mask to a grain (defined as granularity in bytes) is: e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK); This is broken in several ways: 1) It calculates to wrong grain values. E.g., a physical address mask of ~0xfff should give a grain of 0x1000. Without considering PAGE_MASK, there is an off-by-one. Things are worse when also filtering it with ~PAGE_MASK. This will calculate to a grain with the upper bits set. In the example it even calculates to ~0. 2) The grain does not depend on and is unrelated to the kernel's page-size. The page-size only matters when unmapping memory in memory_failure(). Smaller grains are wrongly rounded up to the page-size, on architectures with a configurable page-size (e.g. arm64) this could round up to the even bigger page-size of the hypervisor. Fix this with: e->grain = ~mem_err->physical_addr_mask + 1; The grain_bits are defined as: grain = 1 << grain_bits; Change also the grain_bits calculation accordingly, it is the same formula as in edac_mc.c now and the code can be unified. The value in ->physical_addr_mask coming from firmware is assumed to be contiguous, but this is not sanity-checked. However, in case the mask is non-contiguous, a conversion to grain_bits effectively converts the grain bit mask to a power of 2 by rounding up. Suggested-by: James Morse Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 851aad92e42d..97242cf18a88 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -220,6 +220,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) /* Cleans the error report buffer */ memset(e, 0, sizeof (*e)); e->error_count = 1; + e->grain = 1; strcpy(e->label, "unknown label"); e->msg = pvt->msg; e->other_detail = pvt->other_detail; @@ -315,7 +316,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) /* Error grain */ if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK) - e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK); + e->grain = ~mem_err->physical_addr_mask + 1; /* Memory error location, mapped on e->location */ p = e->location; @@ -428,8 +429,13 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) if (p > pvt->other_detail) *(p - 1) = '\0'; + /* Sanity-check driver-supplied grain value. */ + if (WARN_ON_ONCE(!e->grain)) + e->grain = 1; + + grain_bits = fls_long(e->grain - 1); + /* Generate the trace event */ - grain_bits = fls_long(e->grain); snprintf(pvt->detail_location, sizeof(pvt->detail_location), "APEI location: %s %s", e->location, e->other_detail); trace_mc_event(e->type, e->msg, e->label, e->error_count, From patchwork Thu Oct 10 20:25:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175836 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792653ill; Thu, 10 Oct 2019 13:25:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqxq38fQXmelkv5dKUjvvGzwZxBGqCpEWAaFKvcyqFSo4bBUb1L1U9S6II8RQ8fQddWm7MF1 X-Received: by 2002:a50:9fcd:: with SMTP id c71mr10006158edf.139.1570739154704; Thu, 10 Oct 2019 13:25:54 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739154; cv=pass; d=google.com; s=arc-20160816; b=z35WdzOB49CTejCxNAmbTByDmlHUmUIWPm8OdcXpwQtls6X2WS7MUDJyXOSKMm7ohG lH+okdbLZ9n3aQrx8J2F6UUV53b8lxT5j9NG7CIu6uJWr0oNeHYxlMqarBWR0ZjYDdnG DhtBaigyaMtkfxrb0xGV0OYjTP6nWfHXEKJoJ3prKdeOwj8bECYUr7BooImnELRgzUt1 6TqSy2uP2u2L7+2rlhUqlNjKBe/crrZBsURTaxs2wu6srFSwz/UOcwL2pVRU0TA1Yrz8 8FwNk2JZUCqDbSkEbEvs91Wi0EBhCZTT3lECaJ4aa9cOZPPcRgmfYrQ5FNwpTSqSBsmb FSaA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=hLoups3dF+xoDLUwS/dA326mDDuYMC/B7Np78wKqtCQ=; b=d0Yz4PU/sNN5bDHkMiUH0HB96VsQ8Q8dO8rC1QHsx7ZiSaXT2se5rlGvbx/hOzo1NG OHNvHlVJgKXW92HAadqoUKmMpEJgaoGhn8t4w6Tkh1vjRXZRBtxMPtTcTWoZoUWse9jx R1HsCSq+TNJxAHo7Y3S1Mkq1HdQQDk2sP1/4g3FwdZV1RMeuriu5apEbGbhjfyI0aCKY 4W0DAyGznRntGDtQHy3Z77/Lt5gahYsXOMy3vqpOp+AvbiT3ZMLPjFhgwu8y/SzaxkpQ lb0AX6TNswgBNfVWyoV5v+VHmq3WzlnkcMHtKKCSEEMAp4Q31Ud9xGAPMoBsnJp3fEcs D4ow== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=axYka27D; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=D42kh2sd; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Thu, 10 Oct 2019 20:25:39 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763%3]) with mapi id 15.20.2327.026; Thu, 10 Oct 2019 20:25:39 +0000 From: Robert Richter To: Borislav Petkov , Mauro Carvalho Chehab , Tony Luck CC: James Morse , Robert Richter , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: [PATCH 17/19] EDAC, ghes: Remove intermediate buffer pvt->detail_location Thread-Topic: [PATCH 17/19] EDAC, ghes: Remove intermediate buffer pvt->detail_location Thread-Index: AQHVf6jhvWLXT91WTESlXtwQORRIng== Date: Thu, 10 Oct 2019 20:25:38 +0000 Message-ID: <20191010202418.25098-18-rrichter@marvell.com> References: <20191010202418.25098-1-rrichter@marvell.com> In-Reply-To: <20191010202418.25098-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0336.eurprd05.prod.outlook.com (2603:10a6:7:92::31) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:165::10) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [31.208.96.227] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3cb8bfe9-5eb1-4340-9209-08d74dc003b6 x-ms-traffictypediagnostic: MN2PR18MB2447: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1824; 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Instead of having an extra copy step, assemble the location string in other_detail[] from the beginning. Using other_detail[] to call trace_mc_event() is now the same as in edac_mc.c and code can be unified. Reviewed-by: James Morse Signed-off-by: Robert Richter --- drivers/edac/ghes_edac.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 97242cf18a88..8d9d3c4dbebb 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -21,8 +21,7 @@ struct ghes_edac_pvt { struct mem_ctl_info *mci; /* Buffers for the error handling routine */ - char detail_location[240]; - char other_detail[160]; + char other_detail[400]; char msg[80]; }; @@ -356,6 +355,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) /* All other fields are mapped on e->other_detail */ p = pvt->other_detail; + p += snprintf(p, sizeof(pvt->other_detail), + "APEI location: %s ", e->location); if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) { u64 status = mem_err->error_status; @@ -436,12 +437,10 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) grain_bits = fls_long(e->grain - 1); /* Generate the trace event */ - snprintf(pvt->detail_location, sizeof(pvt->detail_location), - "APEI location: %s %s", e->location, e->other_detail); trace_mc_event(e->type, e->msg, e->label, e->error_count, mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, - grain_bits, e->syndrome, pvt->detail_location); + grain_bits, e->syndrome, e->other_detail); dimm = edac_get_dimm_by_index(mci, e->top_layer); From patchwork Thu Oct 10 20:25:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 175837 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2792704ill; Thu, 10 Oct 2019 13:25:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqzkN8mIhBxcsN0mvbKWXGDjY3RrYZ3Cf9QhPtTPX3Ln5kYKMj+nTKT0i89chQ4rFblvUh/M X-Received: by 2002:a17:906:4948:: with SMTP id f8mr9882495ejt.318.1570739158209; Thu, 10 Oct 2019 13:25:58 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1570739158; cv=pass; d=google.com; s=arc-20160816; b=i+4fkZw+N2KXh7TKAoNqdEk5WBO25UgElCJn8YYGigYBEi0+dUKU3dXXHxow/5KavY o38mIcQukCka+OtQwkYwmShRjgYyu6Teg9uwY4npnjcPWLGtzIMmk+s8ZyMPWvEJI7C0 zUpD8cd03fkcPlxRvCR+3TzHpLfvk5dDiC2E2rR/btQGclxRmLBC9HGCa3Bv8xIYefsZ pRxBnl2jZlckgH0h7O00iajZrhc+u7XzybxpY7MvBq8ivrIdasUd94WqAEFGOaLiIjk2 d5rNB5p02Df4f/KELxMi6kcZaLtD23GuqaHogqNxLCqTIqCldB0RXN9ek0NHDtoCfAbU A+kA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :content-language:accept-language:in-reply-to:references:message-id :date:thread-index:thread-topic:subject:cc:to:from:dkim-signature :dkim-signature; bh=f1hs/py0Rr0nPNiJS554yy0yr11bWlffRM0typKOO2c=; b=VMAap6sEOOI4jT5bbdas0AEaFBlySkHtGT7+l3UNZrpc3A0sVvG8MQGeIl1+7WvS5c mtWKzwh6ecbKlbGrXhCvOzRzZbnOVqyYH4si9ZndAwpYmV8VTvqX8oyeODihPDSZ2pnV 7jPgBSmLgdcRrfw1cAi90Emzy2mIIukPMmwJB+unADM1D9rxgKUp6yBEn9m2LmpUCvSn amstHrsULPmqODUL3TqakU56c2HWNEjb7/t0LsIWUuscExeC+YKFuYkeYGZV85d42qCc HLUXmE0CM4WN96qmdzPRMT5q6Pv2QLOlWGgnzwxthwyhiDoH46cit6D2sJabyBFcAj6y +HNg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0818 header.b=x0ad6Cmm; dkim=pass header.i=@marvell.onmicrosoft.com header.s=selector2-marvell-onmicrosoft-com header.b=F7BdWps0; arc=pass (i=1 spf=pass spfdomain=marvell.com dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=marvell.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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x-forefront-prvs: 018632C080 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(376002)(39860400002)(366004)(346002)(136003)(199004)(189003)(6512007)(476003)(8936002)(25786009)(50226002)(8676002)(81156014)(81166006)(7736002)(305945005)(256004)(486006)(14454004)(2616005)(6436002)(86362001)(66066001)(36756003)(66946007)(66476007)(66556008)(64756008)(66446008)(11346002)(446003)(71190400001)(71200400001)(6486002)(186003)(478600001)(5660300002)(386003)(316002)(3846002)(26005)(4326008)(6116002)(2906002)(52116002)(76176011)(99286004)(54906003)(110136005)(6506007)(102836004)(1076003); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB2447; H:MN2PR18MB3408.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: BkTUYb53fLqcsfmqxhiylgOWqGfLlvlOxoIic/utC6d/Cuvm8wPnqCdiPXBzXnsvczO3BWuqh6YRjSAf9RzUBehubfLJyEwBc14rccgP8219tVF7hHsLDHWBYIGJVsSYnfkidXW1kDnlhM/OdBHDOLCXo1EOWK5ktBbpCn2rzgxz4ZS2FdFP4zzfRBf+eKcygRkED508+4REN3lozkNl/VplsnCg1HOCHXJH8llEXQrjm4Lbes19DsDe66hANvbICM72p3nvC3kdrdOOwaqSg8r8353uf9SrMJf8HMZXd1nLVRx+z45AvIL2kgOOpsYqrRNWAEQoquQSt2pBEx4ZULNK1Ti1yuWreRN3sGi7m/SH/9+3FVdcL0/UjC9gEqxSPGpo0nQAh9APxJnHYpJcUzMJBfcbiBVyJQQLA2DWZsk= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: ba646771-7db3-4ae2-8203-08d74dc004dd X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Oct 2019 20:25:40.8828 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /rhUAvkCsLOB1TCOWACuKtvx285MOliKpY00yes4SgsxToIwmxqA9YgiSAfSmXxr/QltbqReTzAVEV5NaU+6Pg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2447 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-10_07:2019-10-10,2019-10-10 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The code in ghes_edac.c and edac_mc.c for grain_bits calculation and calling trace_mc_event() is now the same. Move it to a single location in edac_raw_mc_handle_error(). The only difference is the missing IS_ENABLED(CONFIG_RAS) switch, but this is needed for ghes too. Signed-off-by: Robert Richter --- drivers/edac/edac_mc.c | 30 +++++++++++++++--------------- drivers/edac/ghes_edac.c | 13 ------------- 2 files changed, 15 insertions(+), 28 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 3779204c0e21..e6c6e40dc760 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -1070,6 +1070,21 @@ void edac_raw_mc_handle_error(struct edac_raw_error_desc *e, { struct mem_ctl_info *mci = error_desc_to_mci(e); char detail[80]; + u8 grain_bits; + + /* Sanity-check driver-supplied grain value. */ + if (WARN_ON_ONCE(!e->grain)) + e->grain = 1; + + grain_bits = fls_long(e->grain - 1); + + /* Report the error via the trace interface */ + if (IS_ENABLED(CONFIG_RAS)) + trace_mc_event(e->type, e->msg, e->label, e->error_count, + mci->mc_idx, e->top_layer, e->mid_layer, + e->low_layer, + (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, + grain_bits, e->syndrome, e->other_detail); /* Memory type dependent details about the error */ if (e->type == HW_EVENT_ERR_CORRECTED) { @@ -1110,7 +1125,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, int row = -1, chan = -1; int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; int i, n_labels = 0; - u8 grain_bits; struct edac_raw_error_desc *e = &mci->error_desc; bool any_memory = true; @@ -1242,20 +1256,6 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type, if (p > e->location) *(p - 1) = '\0'; - /* Sanity-check driver-supplied grain value. */ - if (WARN_ON_ONCE(!e->grain)) - e->grain = 1; - - grain_bits = fls_long(e->grain - 1); - - /* Report the error via the trace interface */ - if (IS_ENABLED(CONFIG_RAS)) - trace_mc_event(type, e->msg, e->label, e->error_count, - mci->mc_idx, e->top_layer, e->mid_layer, - e->low_layer, - (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, - grain_bits, e->syndrome, e->other_detail); - dimm = edac_get_dimm(mci, top_layer, mid_layer, low_layer); edac_raw_mc_handle_error(e, dimm); diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c index 8d9d3c4dbebb..17d5b22fe000 100644 --- a/drivers/edac/ghes_edac.c +++ b/drivers/edac/ghes_edac.c @@ -198,7 +198,6 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) struct ghes_edac_pvt *pvt = ghes_pvt; unsigned long flags; char *p; - u8 grain_bits; if (!pvt) return; @@ -430,18 +429,6 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err) if (p > pvt->other_detail) *(p - 1) = '\0'; - /* Sanity-check driver-supplied grain value. */ - if (WARN_ON_ONCE(!e->grain)) - e->grain = 1; - - grain_bits = fls_long(e->grain - 1); - - /* Generate the trace event */ - trace_mc_event(e->type, e->msg, e->label, e->error_count, - mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, - (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, - grain_bits, e->syndrome, e->other_detail); - dimm = edac_get_dimm_by_index(mci, e->top_layer); edac_raw_mc_handle_error(e, dimm); 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Thu, 10 Oct 2019 20:25:43 +0000 Received: from MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763]) by MN2PR18MB3408.namprd18.prod.outlook.com ([fe80::d16d:8855:c030:2763%3]) with mapi id 15.20.2327.026; Thu, 10 Oct 2019 20:25:43 +0000 From: Robert Richter To: Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , Jonathan Corbet CC: James Morse , Robert Richter , "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-doc@vger.kernel.org" Subject: [PATCH 19/19] EDAC, Documentation: Describe CPER module definition and DIMM ranks Thread-Topic: [PATCH 19/19] EDAC, Documentation: Describe CPER module definition and DIMM ranks Thread-Index: AQHVf6jjo1IdYWQkYEOnV71CnJn51g== Date: Thu, 10 Oct 2019 20:25:42 +0000 Message-ID: <20191010202418.25098-20-rrichter@marvell.com> References: <20191010202418.25098-1-rrichter@marvell.com> In-Reply-To: <20191010202418.25098-1-rrichter@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR05CA0336.eurprd05.prod.outlook.com (2603:10a6:7:92::31) To MN2PR18MB3408.namprd18.prod.outlook.com (2603:10b6:208:165::10) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.20.1 x-originating-ip: [31.208.96.227] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 7bc98929-74e4-4fe5-bd96-08d74dc00628 x-ms-traffictypediagnostic: MN2PR18MB2447: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; 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Signed-off-by: Robert Richter --- Documentation/admin-guide/ras.rst | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) -- 2.20.1 Reviewed-by: Mauro Carvalho Chehab diff --git a/Documentation/admin-guide/ras.rst b/Documentation/admin-guide/ras.rst index 2b20f5f7380d..26e02a59f0f4 100644 --- a/Documentation/admin-guide/ras.rst +++ b/Documentation/admin-guide/ras.rst @@ -330,9 +330,12 @@ There can be multiple csrows and multiple channels. .. [#f4] Nowadays, the term DIMM (Dual In-line Memory Module) is widely used to refer to a memory module, although there are other memory - packaging alternatives, like SO-DIMM, SIMM, etc. Along this document, - and inside the EDAC system, the term "dimm" is used for all memory - modules, even when they use a different kind of packaging. + packaging alternatives, like SO-DIMM, SIMM, etc. The UEFI + specification (Version 2.7) defines a memory module in the Common + Platform Error Record (CPER) section to be an SMBIOS Memory Device + (Type 17). Along this document, and inside the EDAC system, the term + "dimm" is used for all memory modules, even when they use a + different kind of packaging. Memory controllers allow for several csrows, with 8 csrows being a typical value. Yet, the actual number of csrows depends on the layout of @@ -349,12 +352,14 @@ controllers. The following example will assume 2 channels: | | ``ch0`` | ``ch1`` | +============+===========+===========+ | ``csrow0`` | DIMM_A0 | DIMM_B0 | - +------------+ | | - | ``csrow1`` | | | + | | rank0 | rank0 | + +------------+ - | - | + | ``csrow1`` | rank1 | rank1 | +------------+-----------+-----------+ | ``csrow2`` | DIMM_A1 | DIMM_B1 | - +------------+ | | - | ``csrow3`` | | | + | | rank0 | rank0 | + +------------+ - | - | + | ``csrow3`` | rank1 | rank1 | +------------+-----------+-----------+ In the above example, there are 4 physical slots on the motherboard @@ -374,11 +379,13 @@ which the memory DIMM is placed. Thus, when 1 DIMM is placed in each Channel, the csrows cross both DIMMs. Memory DIMMs come single or dual "ranked". A rank is a populated csrow. -Thus, 2 single ranked DIMMs, placed in slots DIMM_A0 and DIMM_B0 above -will have just one csrow (csrow0). csrow1 will be empty. On the other -hand, when 2 dual ranked DIMMs are similarly placed, then both csrow0 -and csrow1 will be populated. The pattern repeats itself for csrow2 and -csrow3. +In the example above 2 dual ranked DIMMs are similarly placed. Thus, +both csrow0 and csrow1 are populated. On the other hand, when 2 single +ranked DIMMs are placed in slots DIMM_A0 and DIMM_B0, then they will +have just one csrow (csrow0) and csrow1 will be empty. The pattern +repeats itself for csrow2 and csrow3. Also note that some memory +controller doesn't have any logic to identify the memory module, see +``rankX`` directories below. The representation of the above is reflected in the directory tree in EDAC's sysfs interface. Starting in directory