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([156.19.246.23]) by smtp.gmail.com with ESMTPSA id u8-20020a170902e80800b001e0b5d49fc7sm12215489plg.161.2024.04.24.10.09.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 10:09:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Cl=C3=A9ment_Chigot?= , qemu-stable@nongnu.org Subject: [PATCH] target/arm: Restrict translation disabled alignment check to VMSA Date: Wed, 24 Apr 2024 10:09:03 -0700 Message-Id: <20240424170908.759043-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424170908.759043-1-richard.henderson@linaro.org> References: <20240424170908.759043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For cpus using PMSA, when the MPU is disabled, the default memory type is Normal, Non-cachable. Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled") Reported-by: Clément Chigot Signed-off-by: Richard Henderson --- Since v9 will likely be tagged tomorrow without this fixed, Cc: qemu-stable@nongnu.org --- target/arm/tcg/hflags.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 5da1b0fc1d..66de30b828 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -38,8 +38,16 @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) } /* - * If translation is disabled, then the default memory type is - * Device(-nGnRnE) instead of Normal, which requires that alignment + * With PMSA, when the MPU is disabled, all memory types in the + * default map is Normal. + */ + if (arm_feature(env, ARM_FEATURE_PMSA)) { + return false; + } + + /* + * With VMSA, if translation is disabled, then the default memory type + * is Device(-nGnRnE) instead of Normal, which requires that alignment * be enforced. Since this affects all ram, it is most efficient * to handle this during translation. */ From patchwork Wed Apr 24 17:09:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 791521 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:346:15ad:a2a with SMTP id g4csp947901wrq; Wed, 24 Apr 2024 10:10:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVGP7xr4W0MYJK+AyFqHm0ipC6MYhqlMFXfAGJYI0p4I8UlD14u4tZKdrDaKEW0SS7ga5Wb0GIdoDkn/b88mttt X-Google-Smtp-Source: AGHT+IHht/auGdyDMVrUTR72RxVMa50d2ZMCdgbseSCtodampivEvYE1+WI9xF015ShQbtozqaWt X-Received: by 2002:a05:6122:3bcd:b0:4d3:3adc:b639 with SMTP id ft13-20020a0561223bcd00b004d33adcb639mr3344412vkb.6.1713978645217; Wed, 24 Apr 2024 10:10:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713978645; cv=none; d=google.com; s=arc-20160816; b=LAt6Zsgtjh7uSthCy1VmtR7Y5PzFlU8gSg3iMUprlqD4hZF2lDSFda1lf0Emu0L1bO 5373Tt/p7oVchT9i8hxg5lKlcMWZjzgGI5SwJG3sxZzL4Q1HUi6GdwFtll+916GYzCwu Btrv3wtf17gWyJkavlFpxCbkhxR5tss27z98NNU8o/kw5L2MNQHT3ijm0ZyihGS8gh8V yebRU4VUTrXacQteR0cZtaJ727r4WqvAfV/sFmYhPOcluVzyMGOuJlmVqv5vjEZW95Ys p2QK5dwHTPNpbHAAle4ChT8A3OHtSX9LNfIXOq62Jo08uRPkAXuCAELETwl2uqw/IWJT no5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=T0/wwsmOrIFP2k0lfcZhLa1SDoLg5xmY78unAbAeB00=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=g316KutChN4cbAcDNzmRiNaHUKvzuMfX/J994eTXmIjQ4DFZ63sxKdjr8WaHR1dmag pwsU5yMYZKnbYcPTwRwIjle0okU3LuNAfm88g7zYd5atJpxMS2ryZ43Zq8dNSM3NmaXb svmaVpVje4mjV1IjWfJgliI2WEWxyq2Lcb/6sSY/JCi1Xksk57Lih1DGyqSqwE4ozQTr C8ulVekZoYRbOj7S3lLyz4I8x1CvegmxQDJZQJh7ymr93MPqOZN7E1pYCgCx2RY+3Pnu k6jEw1HQrBHH8rw40Kr9ZNH5iJdiasOrEqcEyuSRqZ/S/cUMxNvKSaRwcSk0da49vpVi WR2A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H7sImLsv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([156.19.246.23]) by smtp.gmail.com with ESMTPSA id u8-20020a170902e80800b001e0b5d49fc7sm12215489plg.161.2024.04.24.10.09.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 10:09:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/5] tcg/i386: Simplify immediate 8-bit logical vector shifts Date: Wed, 24 Apr 2024 10:09:05 -0700 Message-Id: <20240424170908.759043-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424170908.759043-1-richard.henderson@linaro.org> References: <20240424170908.759043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The x86 isa does not have this operation, so we need an expansion. Use the same algorithm that we use for expanding this vector operation with integers: perform the shift with a wider type and then mask the bits that must be zero. This reduces the instruction count from 5 to 2. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 61 +++++++++------------------------------ 1 file changed, 14 insertions(+), 47 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index c6ba498623..6837c519b0 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3769,49 +3769,20 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) } } -static void expand_vec_shi(TCGType type, unsigned vece, TCGOpcode opc, +static void expand_vec_shi(TCGType type, unsigned vece, bool right, TCGv_vec v0, TCGv_vec v1, TCGArg imm) { - TCGv_vec t1, t2; + uint8_t mask; tcg_debug_assert(vece == MO_8); - - t1 = tcg_temp_new_vec(type); - t2 = tcg_temp_new_vec(type); - - /* - * Unpack to W, shift, and repack. Tricky bits: - * (1) Use punpck*bw x,x to produce DDCCBBAA, - * i.e. duplicate in other half of the 16-bit lane. - * (2) For right-shift, add 8 so that the high half of the lane - * becomes zero. For left-shift, and left-rotate, we must - * shift up and down again. - * (3) Step 2 leaves high half zero such that PACKUSWB - * (pack with unsigned saturation) does not modify - * the quantity. - */ - vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, - tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8, - tcgv_vec_arg(t2), tcgv_vec_arg(v1), tcgv_vec_arg(v1)); - - if (opc != INDEX_op_rotli_vec) { - imm += 8; - } - if (opc == INDEX_op_shri_vec) { - tcg_gen_shri_vec(MO_16, t1, t1, imm); - tcg_gen_shri_vec(MO_16, t2, t2, imm); + if (right) { + mask = 0xff >> imm; + tcg_gen_shri_vec(MO_16, v0, v1, imm); } else { - tcg_gen_shli_vec(MO_16, t1, t1, imm); - tcg_gen_shli_vec(MO_16, t2, t2, imm); - tcg_gen_shri_vec(MO_16, t1, t1, 8); - tcg_gen_shri_vec(MO_16, t2, t2, 8); + mask = 0xff << imm; + tcg_gen_shli_vec(MO_16, v0, v1, imm); } - - vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8, - tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(t2)); - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); + tcg_gen_and_vec(MO_8, v0, v0, tcg_constant_vec(type, MO_8, mask)); } static void expand_vec_sari(TCGType type, unsigned vece, @@ -3821,7 +3792,7 @@ static void expand_vec_sari(TCGType type, unsigned vece, switch (vece) { case MO_8: - /* Unpack to W, shift, and repack, as in expand_vec_shi. */ + /* Unpack to 16-bit, shift, and repack. */ t1 = tcg_temp_new_vec(type); t2 = tcg_temp_new_vec(type); vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8, @@ -3874,12 +3845,7 @@ static void expand_vec_rotli(TCGType type, unsigned vece, { TCGv_vec t; - if (vece == MO_8) { - expand_vec_shi(type, vece, INDEX_op_rotli_vec, v0, v1, imm); - return; - } - - if (have_avx512vbmi2) { + if (vece != MO_8 && have_avx512vbmi2) { vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm); return; @@ -4155,10 +4121,11 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, switch (opc) { case INDEX_op_shli_vec: - case INDEX_op_shri_vec: - expand_vec_shi(type, vece, opc, v0, v1, a2); + expand_vec_shi(type, vece, false, v0, v1, a2); + break; + case INDEX_op_shri_vec: + expand_vec_shi(type, vece, true, v0, v1, a2); break; - case INDEX_op_sari_vec: expand_vec_sari(type, vece, v0, v1, a2); break; From patchwork Wed Apr 24 17:09:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 791518 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:346:15ad:a2a with SMTP id g4csp947625wrq; Wed, 24 Apr 2024 10:10:22 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWx+LNtgl5d9VR4QFAvHeI2allNeMVmRdvOZ8jJGG3ewGJH1jFNDIcUn0dLj8uPyXY0ReTqsxTOZymhbcUP7bTO X-Google-Smtp-Source: AGHT+IGg9fonNWQawXmCsBLmACNTZa4kTf6hg3BQTpP4lMoq9+kCS+gB5PgSMqfeXvPqjQSgbajE X-Received: by 2002:a67:cfcd:0:b0:47b:bda4:c30d with SMTP id h13-20020a67cfcd000000b0047bbda4c30dmr498554vsm.3.1713978622424; Wed, 24 Apr 2024 10:10:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713978622; cv=none; d=google.com; s=arc-20160816; b=JpIcCDSm0vKnuu9NUV/Y2sDMPmf80USjj2G450eoHJONNEYJ9p2JxWHVtigNI31S5z hz+AjqPcZo0dizvwg5CRPV4aJxPNKYm7s2Z4mA21ct2wQkDsEgebVz7b398jdIECbSLG KeWmVmC1j+YsMD6mEhGjpdEYBeD7DdYKIYd4Gf4i0VZHIZ+9FckUcXbhMUoCcMLvLuYG tfJaUTeeGZhjP3XMlySEgQyaNRZmxqZWWaLayXkTb5BB5oXSLlK/rjuChYb2PxH4yf89 hJ10XXt+Hg3Q44xbAGYM+iraB8fFBLmpkf1Ls44krPU1lqzW49JBxRNrPRX4s9615S2d 1qmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=w8fmNK6lWstHDkHAiX3GTp5ypgknN5T6iIFnYWpyosQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=UWP5UOH1VmbjLXD59MxBxYWnxbYSV/sYm1l9GydpkNGkOel8bH46NE/J3g9ABouCo6 eQTpf1W7p45EyRgechSAMVDJvh4EktAli65nzbtCXxdJFw+YQ7F7MBBGC23vg0aOugXZ 1FtbmzZ++3x5XnResQrmgoBA0TPofwGUJlqf+rkiyFco5kfmAIMqraUY4v8WdfIdRPva HnIjSB43dMQ1Zch6xJq2fw+oxf972JM+TZOIG4rEreBakCYLC0mxcLrG2p1oqkOjQPrR GvmlUeip1KtJbWB8doRwlcOpuGx6DJaag/LbOKbFBucv9EwDXW4sJ0q3vLDCQpIUH4AK tdug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aJYTh7Rr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([156.19.246.23]) by smtp.gmail.com with ESMTPSA id u8-20020a170902e80800b001e0b5d49fc7sm12215489plg.161.2024.04.24.10.09.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 10:09:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/5] tcg/i386: Optimize setcond of TST{EQ,NE} with 0xffffffff Date: Wed, 24 Apr 2024 10:09:06 -0700 Message-Id: <20240424170908.759043-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424170908.759043-1-richard.henderson@linaro.org> References: <20240424170908.759043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This may be treated as a 32-bit EQ/NE comparison against 0, which is in turn treated as a LTU/GEU comparison against 1. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/i386/tcg-target.c.inc | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6837c519b0..59235b4f38 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1658,6 +1658,7 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, TCGArg dest, TCGArg arg1, TCGArg arg2, int const_arg2, bool neg) { + int cmp_rexw = rexw; bool inv = false; bool cleared; int jcc; @@ -1674,6 +1675,18 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, } break; + case TCG_COND_TSTNE: + inv = true; + /* fall through */ + case TCG_COND_TSTEQ: + /* If arg2 is -1, convert to LTU/GEU vs 1. */ + if (const_arg2 && arg2 == 0xffffffffu) { + arg2 = 1; + cmp_rexw = 0; + goto do_ltu; + } + break; + case TCG_COND_LEU: inv = true; /* fall through */ @@ -1697,7 +1710,7 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, * We can then use NEG or INC to produce the desired result. * This is always smaller than the SETCC expansion. */ - tcg_out_cmp(s, TCG_COND_LTU, arg1, arg2, const_arg2, rexw); + tcg_out_cmp(s, TCG_COND_LTU, arg1, arg2, const_arg2, cmp_rexw); /* X - X - C = -C = (C ? -1 : 0) */ tgen_arithr(s, ARITH_SBB + (neg ? rexw : 0), dest, dest); @@ -1744,7 +1757,7 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, cleared = true; } - jcc = tcg_out_cmp(s, cond, arg1, arg2, const_arg2, rexw); + jcc = tcg_out_cmp(s, cond, arg1, arg2, const_arg2, cmp_rexw); tcg_out_modrm(s, OPC_SETCC | jcc, 0, dest); if (!cleared) { From patchwork Wed Apr 24 17:09:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 791520 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:346:15ad:a2a with SMTP id g4csp947840wrq; Wed, 24 Apr 2024 10:10:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU+EU42ouRxz+j5adWKNOpNu8PxNeTqhOR2GB7mfqRxo2YnLV354qbURoYK3Qnl+9N4LsT3uoWw0doKe4SPBAbh X-Google-Smtp-Source: AGHT+IGDWuoZT4VS2WAbIU2e6dxubL1671jUc5g52tfVheFMA7aNMtsJmZgCFEarwdvh4RGKAqmP X-Received: by 2002:a05:690c:d82:b0:61b:91e3:f954 with SMTP id da2-20020a05690c0d8200b0061b91e3f954mr1316575ywb.8.1713978640389; Wed, 24 Apr 2024 10:10:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713978640; cv=none; d=google.com; s=arc-20160816; b=PBohGvPlEg+hB2LanB+d2iJdQ0gMdqie2wnm1obcmXwQ6664u2y3Qzj90o9MTTZE8k BiH/diw3ataNOUdzKn8OeWeYPtdIXdkjNPdtepqemfvrqYuHVFuj25/qKpRJOwoH9vFh 5F7PXrz62vHna2JeCR12IVnTj1Ab61q7cMcz5XQPjARVgWR1yidoXpcLs0LPfpexGQdz kfiWuHMmSiA5ALrjoHXz4H1BAg0+bhEOTv4cJRBIM/I9fFxWXU0q0/Hv64DJM5WYZG9b CuEhcP47D0iIl5gYyu6CO4Qy/q4zYDlUohJwlyOPBukJ6wsKwUuTVFOonghWxLJ0vOVl MT+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5odWkAYeVMNCe6Cty3EzFB4YygxLZJZYtuimpCAAowk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=WnVdj9aZN/DUywQxylhpydGbOJiQMso/DmpQxkYhROmwHHO0vpZua5teZnOWoihNr+ DveVJuHBitdULI45W3ng60J9QK1Py01bXXeclGeKaB5GreyFpZ3Yamg2QumH3YRhqSf8 SYElvQU0yo/qknKLFYmRXqAyY5Z+KK/KOw2TlSY7dnCtQsw2gsWoXb5ZF/BA+iR9/Qb1 azx4zfiGpSf8GY5TuU00FJMW50IkskHzyeuJ2orCFjFVh9uq7hRENKsnOPURaNdGhrLB WctZrX5BHsFAQHOcGjr9Pj9vbrlFA/vXox4H44QOmhLLg+yzei7Ckfc8LOcPwqWryKLh Fgig==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w0NXHGys; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([156.19.246.23]) by smtp.gmail.com with ESMTPSA id u8-20020a170902e80800b001e0b5d49fc7sm12215489plg.161.2024.04.24.10.09.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 10:09:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/5] tcg/optimize: Optimize setcond with zmask Date: Wed, 24 Apr 2024 10:09:07 -0700 Message-Id: <20240424170908.759043-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424170908.759043-1-richard.henderson@linaro.org> References: <20240424170908.759043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If we can show that high bits of an input are zero, then we may optimize away some comparisons. Signed-off-by: Richard Henderson --- tcg/optimize.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 2e9e5725a9..8886f7037a 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2099,6 +2099,108 @@ static bool fold_remainder(OptContext *ctx, TCGOp *op) return false; } +static bool fold_setcond_zmask(OptContext *ctx, TCGOp *op, bool neg) +{ + uint64_t a_zmask, b_val; + TCGCond cond; + + if (!arg_is_const(op->args[2])) { + return false; + } + + a_zmask = arg_info(op->args[1])->z_mask; + b_val = arg_info(op->args[2])->val; + cond = op->args[3]; + + if (ctx->type == TCG_TYPE_I32) { + a_zmask = (uint32_t)a_zmask; + b_val = (uint32_t)b_val; + } + + /* + * A with only low bits set vs B with high bits set means that A < B. + */ + if (a_zmask < b_val) { + bool inv = false; + + switch (cond) { + case TCG_COND_NE: + case TCG_COND_LEU: + case TCG_COND_LTU: + inv = true; + /* fall through */ + case TCG_COND_GTU: + case TCG_COND_GEU: + case TCG_COND_EQ: + return tcg_opt_gen_movi(ctx, op, op->args[0], neg ? -inv : inv); + default: + break; + } + } + + /* + * A with only lsb set is already boolean. + */ + if (a_zmask <= 1) { + bool convert = false; + bool inv = false; + + switch (cond) { + case TCG_COND_EQ: + inv = true; + /* fall through */ + case TCG_COND_NE: + convert = (b_val == 0); + break; + case TCG_COND_LTU: + case TCG_COND_TSTEQ: + inv = true; + /* fall through */ + case TCG_COND_GEU: + case TCG_COND_TSTNE: + convert = (b_val == 1); + break; + default: + break; + } + if (convert) { + TCGOpcode add_opc, xor_opc, neg_opc; + + if (!inv && !neg) { + return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); + } + + switch (ctx->type) { + case TCG_TYPE_I32: + add_opc = INDEX_op_add_i32; + neg_opc = INDEX_op_neg_i32; + xor_opc = INDEX_op_xor_i32; + break; + case TCG_TYPE_I64: + add_opc = INDEX_op_add_i64; + neg_opc = INDEX_op_neg_i64; + xor_opc = INDEX_op_xor_i64; + break; + default: + g_assert_not_reached(); + } + + if (!inv) { + op->opc = neg_opc; + } else if (neg) { + op->opc = add_opc; + op->args[2] = arg_new_constant(ctx, -1); + } else { + op->opc = xor_opc; + op->args[2] = arg_new_constant(ctx, 1); + } + return false; + } + } + + return false; +} + static void fold_setcond_tst_pow2(OptContext *ctx, TCGOp *op, bool neg) { TCGOpcode and_opc, sub_opc, xor_opc, neg_opc, shr_opc; @@ -2200,6 +2302,10 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) if (i >= 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], i); } + + if (fold_setcond_zmask(ctx, op, false)) { + return true; + } fold_setcond_tst_pow2(ctx, op, false); ctx->z_mask = 1; @@ -2214,6 +2320,10 @@ static bool fold_negsetcond(OptContext *ctx, TCGOp *op) if (i >= 0) { return tcg_opt_gen_movi(ctx, op, op->args[0], -i); } + + if (fold_setcond_zmask(ctx, op, true)) { + return true; + } fold_setcond_tst_pow2(ctx, op, true); /* Value is {0,-1} so all bits are repetitions of the sign. */ From patchwork Wed Apr 24 17:09:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 791517 Delivered-To: patch@linaro.org Received: by 2002:a5d:4884:0:b0:346:15ad:a2a with SMTP id g4csp947448wrq; Wed, 24 Apr 2024 10:10:07 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCURSLEGBv27h7F7j4+rbEwjZup18KOoULxeLsW4k1V1wHyWU21087yeDI1vucKEp77OpyZdJAkd+DDBBtFSxD3v X-Google-Smtp-Source: AGHT+IFjZ/rEWwgJM/CdIkVUN4uuDljyo25cv6LnsCzLQI0EaOW5GGfqp8qL5ZzYVUUDC+QYl7O8 X-Received: by 2002:a05:6358:848c:b0:183:861a:a6ff with SMTP id e12-20020a056358848c00b00183861aa6ffmr2875287rwk.1.1713978606843; Wed, 24 Apr 2024 10:10:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1713978606; cv=none; d=google.com; s=arc-20160816; b=a0uRMkzK4vqJ2ZrbI50FeRNjdFdKPLyM8bPhqGQ2tzH8MH4s17uFcrlwB8XQoAqEIa cttOzHgP6V4Qn/tHB6JucGgkxUkl7zqmD8Kn/bxz09uNfICGWZc9ZbaXVpINRBpDDwIK fI2kwDWH5EV4H+fTEEkC/jLEOVsfhqzh53A8v0KPPkDPOAwVJQYZkXpxtmx4HfYzLRpA NrhFG6P7EHAnu9wRoz1oW5TWz+4oKbD54io5k7NG+n1wIjZ4kg/T3QQCGeDHWIc/qMip u2AivJo5uYu0WYHVXHgKBDnJQ37LSXa3Yu80MIUD8V2CJNC1Il5zVqiv6qFo4EqdhnvO GaDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qLklIJJZiY2n6UNAfojZ7eG/b6Y2VQ38WZLeXE8ZXgQ=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=xRvpJ+IML4z5XbdxRXN23acztd95zDCegppNTOJx1FU5x0XQ49yEmD8pmHQmIZq0TE N0+8j4Nk02B6geNRh0QGtEomZrez8tyKiyAFEpClWDZd1qgDey/8wyNpD+J8iqr2uUsJ Gfg0U847lliPZDbuzpaKjjDCwvs1CzNjPT/ju1zIewxisF4hoK/vpSPkpwJ+3wlmlNGf lVRDCnmQtDriCLOrFJRU1mo1TyVh4BWNEOTtFOcB2ouz1Gpsrx6NfKGiXPbjp6beRR6z INEW/Q1G8BLKtDMtSaoZPgLj4tc9KWX1J2gmZHqdc0exh/8WXoxgbclFHeB4zuOQyjP5 q2dg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mExn48Vi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([156.19.246.23]) by smtp.gmail.com with ESMTPSA id u8-20020a170902e80800b001e0b5d49fc7sm12215489plg.161.2024.04.24.10.09.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 10:09:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 5/5] accel/tcg: Introduce CF_BP_PAGE Date: Wed, 24 Apr 2024 10:09:08 -0700 Message-Id: <20240424170908.759043-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424170908.759043-1-richard.henderson@linaro.org> References: <20240424170908.759043-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Record the fact that we've found a breakpoint on the page in which a TranslationBlock is running. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/translation-block.h | 1 + accel/tcg/cpu-exec.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h index 48211c890a..a6d1af6e9b 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -77,6 +77,7 @@ struct TranslationBlock { #define CF_PARALLEL 0x00008000 /* Generate code for a parallel context */ #define CF_NOIRQ 0x00010000 /* Generate an uninterruptible TB */ #define CF_PCREL 0x00020000 /* Opcodes in TB are PC-relative */ +#define CF_BP_PAGE 0x00040000 /* Breakpoint present in code page */ #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5c70748060..26bf968ff3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -368,7 +368,7 @@ static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc, * breakpoints are removed. */ if (match_page) { - *cflags = (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | 1; + *cflags = (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | CF_BP_PAGE | 1; } return false; }