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Wed, 24 Apr 2024 02:55:17 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , , Subject: [PATCH v3] gpio: tegra186: Fix tegra186_gpio_is_accessible() check Date: Wed, 24 Apr 2024 15:25:14 +0530 Message-ID: <20240424095514.24397-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB58:EE_|SA3PR12MB7904:EE_ X-MS-Office365-Filtering-Correlation-Id: bfe1e682-4bb7-45b6-efd6-08dc6444ae02 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TB0bKri1tcd3bK7nOSBl52bdp8pfCHY+OR8IoOZn+w5ZPVz34jIsKKxXKTy4SqEaqgUImMDfx9Op/G+uL83KHNhqP7l9QN6KLrResMIdvCW4LRRZap50SFDrs9KR9YbOi7nW2/ZqgUR+jWMo7JUVBbHNI7TNyM7/RrYV+VdbA0KzcBPV8OkknkviLmRuFwhoaiMrR5rD47G04PiWJJ/VIEgKBQ1PBhCAX0IOt9cIX9PTlmh3BFNtv9RTBCwWwJdq+4CC6DWS+M9MVlw/c5J6ucjUyVWJgDc9hWDq5bUOIacSn6HObP8eMwsYVCz6vorTqaN9l4xcfJ5mDaJP3Oz4frtbnYUHp6CnzBr0MV/x0qR/WPL/zDBzwq5xNqjYtsP2oNgTp6vVy1PwfnRQYVuDAo/M1cYzOgMV6WUcYUJkmmfmTkK32agWDzeGfcT0eh/viNFYwMou2qtmpseEt6Sxvmt1eFlO0I4aSvGo3sIYYKLKffLaJK/QwO4oXxMqEOmC7TyuCGwYxh+sKk0F+KSu3/54fADjYbY/3Axrn6rlpm2EbTAhWqnSukS+MXivXYt9IBhCXXh/rQ5pChWG1ejH5pF+/dB6yYBC/hMCzEjC3HHPuv/OsGmimb+nDxUNIydwFqTYKfA3P6Bi6qP+blvwvmFdFnquezXPfooELliaJXaYkSkvUQ347+9b7FT8qqAA1l3P8PTspoZ5Kt70fsBscoXsOvruUXOQghfa95oAlTkwsml1vy77+PduidF+Rt4r16LyOqlyNRLWwgcB04+TbIWheHyowqQO60KMAqd3qiC2baRqFQm4A8XTG7LXgotZD9fuWVcfA6VSlhO1wI861t7PVjbjKq23lIalJ1qH6ozXImhJe4ah3NgGhbXhd/tSooCvCjc/e6Lr0elmq9r/Y7MwgpFPSQQ/ct9ZEuLkEmGXWplXWzK4WTwXZIKX2XByw7RSECo4GwgiiFwqdXk5Y6pPZDPGGH6ARTD70yU88pINEo0TxNm3Dyoz2yYJzzXcQO+JAPitDle6qmXIoU7JFhG/ZZnppFfBNmxoNxTRZ5ngE2O4ZlpVEfy9BwyeVWBcL2w6g1keBtLIWW4nlQxad+j1iBrzKcOLPlcQ5UD6TZEVWsYH5+KTUcAjPEJiDaULPWAvJVZsRXNPheY37pBXyuT0W+UeHhLwN3yeqo2WGviE3owiryI+H3xKLITgJ2eZZtw/OwFUEhi2lu9UZrA+yDi+tbVRNNRNNNaznsbI0hpFBrJEmOBrtIe5IAEcaURZDt+RtApaRDr7u+yTuU2wsqYskNq0bnc/lVqFowVDJJ9/M1jnI9USfAZ34O6ddWzEeENO3BjWkhD6quNsT5nJJjNVH5icaEFryxHzUy9mRpNAoIHfvshC1ouTiEldhXJ5 X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230031)(1800799015)(82310400014)(376005)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2024 09:55:31.7718 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfe1e682-4bb7-45b6-efd6-08dc6444ae02 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB58.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7904 The controller has several register bits describing access control information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it means we have full read/write access to all the registers for given GPIO pin. When SCR_SEC[R|W]EN is set, it means we need to further check the accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given GPIO pin. This check was previously declaring that a GPIO pin was accessible only if either of the following conditions were met: - SCR_SEC_REN + SCR_SEC_WEN both set or - SCR_SEC_REN + SCR_SEC_WEN both set and SCR_SEC_G1R + SCR_SEC_G1W both set Update the check to properly handle cases where only one of SCR_SEC_REN or SCR_SEC_WEN is set. Fixes: b2b56a163230 ("gpio: tegra186: Check GPIO pin permission before access.") Signed-off-by: Prathamesh Shete Acked-by: Thierry Reding --- V2 -> V3: Retain Thierry's 'Acked-by' tag from V1 and add change log. V1 -> V2: Fix kernel test bot warning. drivers/gpio/gpio-tegra186.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index d87dd06db40d..9130c691a2dd 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -36,12 +36,6 @@ #define TEGRA186_GPIO_SCR_SEC_REN BIT(27) #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) -#define TEGRA186_GPIO_FULL_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \ - TEGRA186_GPIO_SCR_SEC_REN | \ - TEGRA186_GPIO_SCR_SEC_G1R | \ - TEGRA186_GPIO_SCR_SEC_G1W) -#define TEGRA186_GPIO_SCR_SEC_ENABLE (TEGRA186_GPIO_SCR_SEC_WEN | \ - TEGRA186_GPIO_SCR_SEC_REN) /* control registers */ #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 @@ -177,10 +171,18 @@ static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned value = __raw_readl(secure + TEGRA186_GPIO_SCR); - if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0) - return true; + /* + * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the + * registers for given GPIO pin. + * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying + * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given + * GPIO pin. + */ - if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS) + if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 || + ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) && + ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 || + ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W)))) return true; return false;