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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 01/20] target/arm: Split out rebuild_hflags_common Date: Fri, 11 Oct 2019 11:55:27 -0400 Message-Id: <20191011155546.14342-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_ANY bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 29 ++++++++++++++++++----------- target/arm/helper.c | 26 +++++++++++++++++++------- 2 files changed, 37 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 297ad5e47a..ad79a6153b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -231,6 +231,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3140,15 +3143,18 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) @@ -3159,13 +3165,14 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) -FIELD(TBFLAG_A32, VECLEN, 1, 3) -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. + * Not cached, because VECLEN+VECSTRIDE are not cached. */ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) /* @@ -3174,15 +3181,15 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) +FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ /* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) +FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ /* For M profile only, set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ @@ -3194,7 +3201,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) static inline bool bswap_code(bool sctlr_b) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d9a2d2ab7..8829d91ae1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11054,6 +11054,22 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif +static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, + arm_to_core_mmu_idx(mmu_idx)); + + if (arm_cpu_data_is_big_endian(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (arm_singlestep_active(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + return flags; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11145,7 +11161,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -11153,9 +11169,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { if (is_a64(env)) { if (env->pstate & PSTATE_SS) { flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); @@ -11166,10 +11182,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } } - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); From patchwork Fri Oct 11 15:55:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175985 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp941482ill; Fri, 11 Oct 2019 08:57:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqxpwr6O1pfxiB3FRI9+OpwvNstd1uP1LP/mA4NfjsJuWmzxqGQR/4BL1Xx5bmnvIHYNu2pC X-Received: by 2002:a05:6402:60e:: with SMTP id n14mr14632359edv.147.1570809440969; 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 02/20] target/arm: Split out rebuild_hflags_a64 Date: Fri, 11 Oct 2019 11:55:28 -0400 Message-Id: <20191011155546.14342-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A64 bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Note that not all BTI related flags are cached, so we have to test the BTI feature twice -- once for those bits moved out to rebuild_hflags_a64 and once for those bits that remain in cpu_get_tb_cpu_state. Signed-off-by: Richard Henderson --- target/arm/helper.c | 131 +++++++++++++++++++++++--------------------- 1 file changed, 69 insertions(+), 62 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index 8829d91ae1..69da04786e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11070,6 +11070,71 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } +static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, + ARMMMUIdx mmu_idx) +{ + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + uint32_t flags = 0; + uint64_t sctlr; + int tbii, tbid; + + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); + tbid = (p1.tbi << 1) | p0.tbi; + tbii = tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid = p0.tbi; + tbii = tbid & !p0.tbid; + } + + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { + int sve_el = sve_exception_el(env, el); + uint32_t zcr_len; + + /* + * If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el != 0 && fp_el == 0) { + zcr_len = 0; + } else { + zcr_len = sve_zcr_len_for_el(env, el); + } + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + } + + sctlr = arm_sctlr(env, el); + + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + } + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11079,67 +11144,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, uint32_t flags = 0; if (is_a64(env)) { - ARMCPU *cpu = env_archcpu(env); - uint64_t sctlr; - *pc = env->pc; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); - tbid = (p1.tbi << 1) | p0.tbi; - tbii = tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid = p0.tbi; - tbii = tbid & !p0.tbid; - } - - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el = sve_exception_el(env, current_el); - uint32_t zcr_len; - - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, current_el); - } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } - - sctlr = arm_sctlr(env, current_el); - - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ - if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } + flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } } else { @@ -11159,9 +11166,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - } - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); + } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: From patchwork Fri Oct 11 15:55:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175987 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp943345ill; Fri, 11 Oct 2019 08:59:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqwUlmzLb8Yj1pkLS6rAeWk94Z9d/TD8CKj1+LwTONKjCiKUmLNNWA3wDrpjMbcJF/OiSNeo X-Received: by 2002:ae9:e20c:: with SMTP id c12mr16560218qkc.149.1570809555932; Fri, 11 Oct 2019 08:59:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570809555; cv=none; d=google.com; s=arc-20160816; b=GvtwNTagYohz9WwtvW1afQwxh7j0NKAykLAog0F+9W/p5Sw1k+fOnUAfAij97B1Rrd qC9+A3VHjElbr5Z9DOdWNoYiAptJbtUYF/xQy7tv9jwy9DEppTwiJq11p7T37WXpCzai qbr9qQXsKoICrnxnoUnsujMgc9EkogTJcw0hYWWqlvGGOrZ2j1JoWaRLxeUEAxaqjuph P5v4tKMHSdKjn50x6sxCd1nltkU38lEYd8n6YQ9qF+m7g7E2fpu3WEatrW1eJwrs12bU H0Ai0uEqJGJ0uCDuCqOcjs8UbDjTqs1rH8Sz38t2rPBCZkj6NSfj6qnF1dRmk34wlVpU aR6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=JZ4FcxbCDDWJsqSaXfQWATqqO+tlQqneKyRyH+pvJoM=; b=x68RX/QJSC3ZyZnC/y7QVi/PzJKOdIPZ4PwQC7zdwh44KZf4AIw/Kp32JMSoeirVD+ y7RolcXT1O8JTse4la/noVYwZpxVG4wsc+0lBe7tQ0ix25CF8Z+6NxvJ4857+49HiVCA AQsPjet4j6RwYyiDuKxx20ksYCaETrzl8av5cAf7Qtr2MyQ1/5meHnHMJyXzaruk6YML RYZTwU0TPQ6/6NE4mP5AeTcVpNu7cPYhxA5Z1UbWBBFrc0HBetbQ4EO7i5t2EiGWrsLL mty0K+T31MKCGup40irV8rPP7AW7jum2w9ul8hkwaRJNPrhX8Utvktk5BAKwFwIMtt+K lc/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VoKm83e3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 03/20] target/arm: Split out rebuild_hflags_common_32 Date: Fri, 11 Oct 2019 11:55:29 -0400 Message-Id: <20191011155546.14342-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by all profiles. Signed-off-by: Richard Henderson --- target/arm/helper.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index 69da04786e..f05d042474 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11070,6 +11070,15 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } +static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11141,7 +11150,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags = 0; + uint32_t flags; if (is_a64(env)) { *pc = env->pc; @@ -11151,12 +11160,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { *pc = env->regs[15]; + flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); @@ -11166,8 +11174,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine From patchwork Fri Oct 11 15:55:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175988 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp943721ill; Fri, 11 Oct 2019 08:59:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqxuP0lSrqfmKHG7L+pjuo/QjqirbVfj70AkZ3zv2T8zCE5+8z13JCJJSUqOjmSiWVu15/NX X-Received: by 2002:ae9:c302:: with SMTP id n2mr15710599qkg.69.1570809575305; Fri, 11 Oct 2019 08:59:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570809575; cv=none; d=google.com; s=arc-20160816; b=Kh6ZFWi5L4S4IXfkyAQrY5BONcvBalsYQCphSM0elzGHnW9jKUm0tLhmQEn1Nh8a5B iLL3ZRKUdqvjPCZXDMcKuJCK9ef9AwOAS7ZK3OUtaAw198hgzBPiWp7LEefzw44OAeFJ NadFJjt9KfL3OGGI8eN9yUyP5WJ9aPy8AZNyclIKfsWakP+YrfEZV8B3n+NlJHeW9WMV 9fkA2Mk9cIw3LIwtbJyUoKvKrevxjwBLb/mOAEE0+vuAYdnVdG5SAFZfrxj6um4UR9OY i+FZq9JcPC4U2NK77eGxMkJZ/kzgykQfEG6SksEvdpduv2tvIHqIoFnhdGYYCyQ2qLvX /dpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=X98g4BsONciVZ3hWGnQlafESmVIuzpNrlu/v750SDKY=; b=zTxtURMAN4AtYWbskp/nltumh9qxPZUOlWSQCBoUk8JACb6XRzxYywrMzucBygkYwJ pl44MfKUT6PYStrvabZWmJFOejvsjC3xKtuPinQrucvZXtfxGpmJmXrg0BPjZBJiY/Gl xyI3YpG7cANb0nLxQBSNDwP2Ueu6OuuiwYGIxMkMjHKGDC4FgMhGkOjL9afxA0AuUyDR iuaR0pj5JtyoFmBFhIB4qkNcJJu1dzhFfwzaz9DoOF1Peo/y3DQCK9j6ATIMYvBAnUuu qLOHiEF6qz0qTlQggVTZVNcf3myLRGUr0PnnYzc1VVoZJQ6MLSEMh5ijhbO5Y+YQ469W myew== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wS7Ogpgp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 04/20] target/arm: Split arm_cpu_data_is_big_endian Date: Fri, 11 Oct 2019 11:55:30 -0400 Message-Id: <20191011155546.14342-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Set TBFLAG_ANY.BE_DATA in rebuild_hflags_common_32 and rebuild_hflags_a64 instead of rebuild_hflags_common, where we do not need to re-test is_a64() nor re-compute the various inputs. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 49 +++++++++++++++++++++++++++------------------ target/arm/helper.c | 16 +++++++++++---- 2 files changed, 42 insertions(+), 23 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad79a6153b..4d961474ce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3108,33 +3108,44 @@ static inline uint64_t arm_sctlr(CPUARMState *env, int el) } } +static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, + bool sctlr_b) +{ +#ifdef CONFIG_USER_ONLY + /* + * In system mode, BE32 is modelled in line with the + * architecture (as word-invariant big-endianness), where loads + * and stores are done little endian but from addresses which + * are adjusted by XORing with the appropriate constant. So the + * endianness to use for the raw data access is not affected by + * SCTLR.B. + * In user mode, however, we model BE32 as byte-invariant + * big-endianness (because user-only code cannot tell the + * difference), and so we need to use a data access endianness + * that depends on SCTLR.B. + */ + if (sctlr_b) { + return true; + } +#endif + /* In 32bit endianness is determined by looking at CPSR's E bit */ + return env->uncached_cpsr & CPSR_E; +} + +static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) +{ + return sctlr & (el ? SCTLR_EE : SCTLR_E0E); +} /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { - return -#ifdef CONFIG_USER_ONLY - /* In system mode, BE32 is modelled in line with the - * architecture (as word-invariant big-endianness), where loads - * and stores are done little endian but from addresses which - * are adjusted by XORing with the appropriate constant. So the - * endianness to use for the raw data access is not affected by - * SCTLR.B. - * In user mode, however, we model BE32 as byte-invariant - * big-endianness (because user-only code cannot tell the - * difference), and so we need to use a data access endianness - * that depends on SCTLR.B. - */ - arm_sctlr_b(env) || -#endif - ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); } else { int cur_el = arm_current_el(env); uint64_t sctlr = arm_sctlr(env, cur_el); - - return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; + return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index f05d042474..4c65476d93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11061,9 +11061,6 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } if (arm_singlestep_active(env)) { flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); } @@ -11073,7 +11070,14 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, uint32_t flags) { - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + bool sctlr_b = arm_sctlr_b(env); + + if (sctlr_b) { + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); + } + if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); return rebuild_hflags_common(env, fp_el, mmu_idx, flags); @@ -11122,6 +11126,10 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sctlr = arm_sctlr(env, el); + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { /* * In order to save space in flags, we record only whether From patchwork Fri Oct 11 15:55:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175990 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp950431ill; Fri, 11 Oct 2019 09:04:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqy5iAszBvxAy1J2s3BblRrvX8Wwgo2v7MJswmyyZaGxyZUzIdr9gMVamTE8G6QO7GNqYYIj X-Received: by 2002:aa7:c6cf:: with SMTP id b15mr14199670eds.215.1570809862084; Fri, 11 Oct 2019 09:04:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570809862; cv=none; d=google.com; s=arc-20160816; b=yVWGvEK1xQH54uSxSWwO5xjYVtDcgGacD8KAFkBHribB9Qs9UGEtkwcuptTi1UjVFg RsknVJZ+HK7FLcvmIVLXi5N0qnPnseTkM5/n/EbhJ6u4X4Tnhfs/pRKRyhfSAN9fR81Z Oe+H1dqvxwy4vXcXY04Ce4cJOqNh5agWTJKnn0u8FwIwCL4lgtLKlNyslopkJI22Fm8g pcBUlyi35z7yzwaTtVYwCaZCdwN8RhScGWGzmyd4sX8eUq3lkqdCH3hQh2zWjTG0YWod 7akpvwyNOcOhn6FL/H9RpZhDYNcX6z+oyX8P7R8EiXgjFsQJcB4rIgQ9tPHrRIrsemgd Owbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=20mv2SwJCcd4Z6z1yWs3I8qxDMrWegtCA17Quz1+Bvk=; b=sNFYk2HfaWZdi71KwvgS8quMziGkA6fHnj+yCF/Eq2hwf7ZcjkcyYSWi5XB6vLG1C5 3A8c1g8zMg5lRPmnjTiwKFELOLJSiRTOtbkpbESctHibtGy6Y1MhqoskC84UvtkqcfgE tlR19z10Fe4RFMTX5xu1AWWQw3DgidwNbFC9/msVhaFw8U6Qw2MQ7mQpkMeoMuqFFx+5 sFWOndM0GGGzvEU2yhOu2CmYT5p1Ma2wV3UZTGI1u5ObK26DvoxQ6Yym16A83Zq5kPhS SwoYyZT0ef1SaDCrdXlpRP8LgnOvSi06/A4c6ibqKTszRvvFDizk4uCwpnrynMJmxo6s xscg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wI1VxkTS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 05/20] target/arm: Split out rebuild_hflags_m32 Date: Fri, 11 Oct 2019 11:55:31 -0400 Message-Id: <20191011155546.14342-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by M-profile. Signed-off-by: Richard Henderson --- target/arm/helper.c | 45 ++++++++++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 15 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index 4c65476d93..d4303420da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11083,6 +11083,29 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + uint32_t flags = 0; + + if (arm_v7m_is_handler_mode(env)) { + flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + } + + /* + * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN + * is suppressing them because the requested execution priority + * is less than 0. + */ + if (arm_feature(env, ARM_FEATURE_V8) && + !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + } + + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11168,7 +11191,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { *pc = env->regs[15]; - flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + + if (arm_feature(env, ARM_FEATURE_M)) { + flags = rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + } + flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); @@ -11204,20 +11233,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (arm_v7m_is_handler_mode(env)) { - flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); - } - - /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is - * suppressing them because the requested execution priority is less than 0. - */ - if (arm_feature(env, ARM_FEATURE_V8) && - arm_feature(env, ARM_FEATURE_M) && - !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); - } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); From patchwork Fri Oct 11 15:55:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175989 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp943779ill; Fri, 11 Oct 2019 08:59:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqy2kVkO0aJ+R39BDPqQo9B4cLD3fRn6hMnYwzkTn4zXveIwotjfNNGQ3XyDk98ccpZgCHUw X-Received: by 2002:a0c:a947:: with SMTP id z7mr16872435qva.103.1570809578186; Fri, 11 Oct 2019 08:59:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570809578; cv=none; d=google.com; s=arc-20160816; b=A7vs1GyS4Apfwh+0ZGeAe8SQS2noCnbVKMI19WjkaRBgJSwyyTYG3Rfm4UgpYGS+5+ qy4hR7G1qnOElLwlkfk/H3qYswzjDWZqRYSF600rqXyD/2DdVeE0EQpw7EUcYrVW8lTt FVPIeDFApOB0XxNRm/6/9XQxtApQM+s0VY+DzsUAQWwbVb9699HqcXLhG0DXV5ciFVK1 iKOoVJJxeq6dnX7FGQ1jJNMe/ihHcdrHJmDWsbbhPRtZciU5Gk+P56TEyT5OFmS8PVkz Arqq9Amy0RYoumhTO+7enEW5naqLcuqwPxjWiwgda41FYZ/HeuMHqjQKTDJP4JfOebtK IDYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=c+8xcuNKYkwsEhklvjvEYe1RYCMD1KcRe25MPQQBSq8=; b=JJS0NFofekWeOyBHxEWjq7qs+K3M7sJ9BuWkUXNuyyAjUyBXGAGozR/+QWCL9Q0mz7 8gpFpujBDJm30W5gfq8hZXk338XkWIEn2ToEL1H1heem9lWsCLlkXIjfCkSFkQTun8dP zNmBl5ey1S8Ujm9jpCm2B69barjDedJCAH2BToeBf/e3qF66l6vrPxrGbNdzewIGXrov SVrcrBOSlWoAipkAyIS/n5pHUZgQM53ULoS9sMoJUXEyFD2RA71m54iLxqDb8IKFBLgq XUKnjcABFl/Il4zqIMAktirIk3xJCUYA6DU+9QysKZPX7xhN6IzNVgsyckEdwJfnjbbf J5yQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EFGmjcZB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 06/20] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state Date: Fri, 11 Oct 2019 11:55:32 -0400 Message-Id: <20191011155546.14342-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist the computation of some TBFLAG_A32 bits that only apply to M-profile under a single test for ARM_FEATURE_M. Signed-off-by: Richard Henderson --- target/arm/helper.c | 49 +++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 26 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index d4303420da..296a4b2232 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11194,6 +11194,29 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (arm_feature(env, ARM_FEATURE_M)) { flags = rebuild_hflags_m32(env, fp_el, mmu_idx); + + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) + != env->v7m.secure) { + flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + } + + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no + * active FP context; we must create a new FP context before + * executing any FP insn. + */ + flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); + } + + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + } } else { flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); } @@ -11233,32 +11256,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { - flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); - } - - if (arm_feature(env, ARM_FEATURE_M) && - (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || - (env->v7m.secure && - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { - /* - * ASPEN is set, but FPCA/SFPA indicate that there is no active - * FP context; we must create a new FP context before executing - * any FP insn. - */ - flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); - } - - if (arm_feature(env, ARM_FEATURE_M)) { - bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; - - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); - } - } - if (!arm_feature(env, ARM_FEATURE_M)) { int target_el = arm_debug_target_el(env); From patchwork Fri Oct 11 15:55:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175993 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp953644ill; Fri, 11 Oct 2019 09:06:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqyUaVWf6yGok4EP7FN0EkbRdJDPCgJoMFSLJ/KRC6YDHp1I642Gq+Jt8VABSy3rfL3JMzuu X-Received: by 2002:a37:7081:: with SMTP id l123mr17055229qkc.246.1570809993032; Fri, 11 Oct 2019 09:06:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570809993; cv=none; d=google.com; s=arc-20160816; b=pdordqFm1YhVhY7ulc6ts9PJILGLtUpVTqkvIz7Io4tcEI1Wq04iCbL1cYUpxd3DeG eWxmZs/vvDBXFrpEW7ueQzV0UGo1ApgLPmirt1ZsJYqoUFnnL0OGUY67tn0cXFfnoaRl qRIcgeUbW+30pBm/xxLplQBgSPdiNpcc1x8GZucptily6iVKKVVa2KGcLVj0TfM5T6rK wviW1lgj0udPgykYDu0dKlOqOjQZ9Kp0cvi3kdg2676aEnO5Qv1b7PRBfVbOcgbB3F3m nhZUVv80/3Sq/Im2as/lOHE1XaQYPv2jqU8aa6lP2wtnmlvqxwnXPm46P8bifDuKead7 TYcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=nFJqxK8OKOrQev/1CQPrr0VKM/9+1cXcigS/dy+zmf4=; b=qNgoKCjCYg2MGP4r5fod/Jvwuj+H6hkofbTV+tpMa5McltHjdANJwNp41M3kltaXps CZg98ZphtMbWXOJm2lZpfCzhPZBxup5Cz3m4Q/s+nnCLaMJ6c7RN1wAADh3MYJxh78WZ ON8Ih3McvwXg8Xai4MzdJz1U3Ik0rR/RaybXh3OdneNRe7WSJ0/CSlyPdsE96E6Lehaz EWWGuF27vEkEKs8Odk663zUSG68/bra6DAM0BCS7hq0p5OVpJwjyI8b1sFtlYwRTXadX HvMmd1GkFsxgSrP3S0ImxSun1d40f+KubCnaEcAsGMWP41mVFKPUGFYla+M+0DlfE/RH K1+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vls3T+ax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v69si9701103qkb.164.2019.10.11.09.06.32 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Oct 2019 09:06:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vls3T+ax; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxR1-0005og-HP for patch@linaro.org; Fri, 11 Oct 2019 12:06:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33675) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxGo-0002LU-81 for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:55:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIxGn-0007eO-4s for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:55:58 -0400 Received: from mail-yb1-xb43.google.com ([2607:f8b0:4864:20::b43]:39998) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iIxGn-0007e3-1R for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:55:57 -0400 Received: by mail-yb1-xb43.google.com with SMTP id s7so3254895ybq.7 for ; Fri, 11 Oct 2019 08:55:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nFJqxK8OKOrQev/1CQPrr0VKM/9+1cXcigS/dy+zmf4=; b=vls3T+ax6QRQgGywOLqQFOiAiTSTvgQafBGaYNxZtVrM/3E7oeVhIBRlMQZZGuqHE7 eyYrnew1A3OkIWvu0J8mxfckeIwXrl918zUEsg0AJu/0SgTSBXL3UxhA+CfmVTm/FJhN bmCM+fx1E/RuODQVfOcwN3OSyehSek5kTgC5VY+yz1vkvTivJSAJObPfhiMZ53knNzmZ 54y121qSTjSHL3YoFb64MaFOV33BCRKL9u9WB3ld68MXu/FhgbB3aevfVVsvO07eRDDg q8P5c0sJvO7mx9q20WkQ9KQUSj2AYDgLUGxtVjOKAPAhWoU/3nC89/VhRYI90Y9P+fRL insQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nFJqxK8OKOrQev/1CQPrr0VKM/9+1cXcigS/dy+zmf4=; b=k6GHrKek8K0KRdUG/Vkvq4W/RRPQIJbCAJ5M4xYLqvBI7tXj6bedwWNknqZwOfBYd+ D1ll+5/1BlE8ZRDObPVYSRrQdNt2UOKoJa0qwdrL0C096snRVxlhG0kefH+XzQuMCl7r Hv4dXiXxGimyMd7AZelrKuMStIPk8FMj+PcMWJMn5mvZcL52iIW95gczWtjFJYnYo3g5 Z2gyhHc+MMoKvHu6y3DV3IzJMLhpy1HejnL+s7ijV2uEVAEGRDQ2U0CK+SHosWTllMGU Fu4GtJIFtLhpMO9y+U1mjKEUeqsn8Kux+Ab/X6Igj5wYd1pd0xql1wR7HTRxujATOv+z SjJg== X-Gm-Message-State: APjAAAUzuV+UH+myBthuyGAhxzxzIsx7r6RjwnkuvpEQckahheO5F67D CNq1gf4hWJob8odggjqB61GZy3WzQJs= X-Received: by 2002:a25:388f:: with SMTP id f137mr10148377yba.223.1570809356070; Fri, 11 Oct 2019 08:55:56 -0700 (PDT) Received: from cloudburst.gateway.pace.com (67.216.151.25.pool.hargray.net. [67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 07/20] target/arm: Split out rebuild_hflags_a32 Date: Fri, 11 Oct 2019 11:55:33 -0400 Message-Id: <20191011155546.14342-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently a trivial wrapper for rebuild_hflags_common_32. Signed-off-by: Richard Henderson --- target/arm/helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index 296a4b2232..d1cd54cc93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11106,6 +11106,12 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11218,7 +11224,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + flags = rebuild_hflags_a32(env, fp_el, mmu_idx); } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); From patchwork Fri Oct 11 15:55:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175995 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp958134ill; Fri, 11 Oct 2019 09:10:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqwg8+yn2HS3fcFF1r2xZn63dEircvZSyA9eQFboNd9/4i/gOtc/0/yFtE8b/Qb94MhLyym1 X-Received: by 2002:a05:6000:1251:: with SMTP id j17mr13668110wrx.198.1570810202437; Fri, 11 Oct 2019 09:10:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570810202; cv=none; d=google.com; s=arc-20160816; b=a9JI9PvWXxr8lpdm6JR2TlieR1F0aXGquVO1co6JaOM/vAQtbD4KmU5mufj8uoS+m5 W7qnoZoY8qTdCWKe3i6v9YBkOfpi22lfPf1aZPciW5DB6HSWQ/uiyJosyWUHgkKaaNdt dYofCUElCxhuoKA1uIrORCrVuBqEn5p7AtefcT5/nCORNPnXLdJufsUB4JbDiLdknAq+ 6KzM3xJffsGJdaVn29aoUoZzigU2nDgbc1TZj+0ZxScheyQZEdop+Lgb4M5LaBTll3OK jcJBlNY4RefvSDqMvBSN/j+7CNjuNLzfgfh3YRFgW6d2NczTf75csP2og0bCJsSORyRp vcXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=nHlb3O+3OTrMLE5XtaApktPGFzFyl87vFrMc6HX9qtE=; b=Yn75wnXtthGsTZaMugF1SwrRSQsxNMHVHpIMd4vFk5L+TnsxcWgbRm5lhZGybGPCrU SDZvQGH9FQ4QWsjMS1BVu2PEQQ6qKpEYNkS5wXCVA5R3mGKI1eQ+vnu08zdUHLF1oUat wyuMabyu9gMU9u5quW2rIYPXRiYlsRnVkSdcGUeDVMwFpNrgGXenzlY+nYqTs9Y1Y1eF mpThjOAWoS50B9U1+BJFekwFA589Kz0+RGozitvxYiy/mC+UL2eoAE6VNEsHYRXaQHTQ kLZIRJkQruVRjoQma90x1rhNPFobsM6G4POpgrTpq8HK+WMqdqK953eAIynhKAPmjsU9 EgiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZqCEYIpK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 08/20] target/arm: Split out rebuild_hflags_aprofile Date: Fri, 11 Oct 2019 11:55:34 -0400 Message-Id: <20191011155546.14342-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_ANY bits that will be cached, and are used by A-profile. Signed-off-by: Richard Henderson --- target/arm/helper.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index d1cd54cc93..ddd21edfcf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11106,18 +11106,28 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +{ + int flags = 0; + + flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, + arm_debug_target_el(env)); + return flags; +} + static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + uint32_t flags = rebuild_hflags_aprofile(env); + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { + uint32_t flags = rebuild_hflags_aprofile(env); ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - uint32_t flags = 0; uint64_t sctlr; int tbii, tbid; @@ -11262,12 +11272,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (!arm_feature(env, ARM_FEATURE_M)) { - int target_el = arm_debug_target_el(env); - - flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el); - } - *pflags = flags; *cs_base = 0; } From patchwork Fri Oct 11 15:55:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175992 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp951254ill; Fri, 11 Oct 2019 09:04:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqx6qPa/XYPDQqSNdNEwgnL1O2PZSnWCLgGYh7/sp4AHYGvZxQx0pYEFToNUhCDcBTI53vY9 X-Received: by 2002:ac8:2fee:: with SMTP id m43mr18332488qta.263.1570809895299; Fri, 11 Oct 2019 09:04:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570809895; cv=none; d=google.com; s=arc-20160816; b=GfV5ETAHh+Zw4+bTgf4zmwVQs47CouofOxYdsonhX2WHKRZOegqEaaXNU9GI+cCa7X G0FjIPuqbfdBp3oscXTcoBc2JhvSdkB/u68PsX7+6M9Wxr71N3S+/+47WvizKSdceK2C i3A/B+wYpICw7Q8zRVh4lkyP77QfE6SW5sw+6+NDQh0E+/9mFKjOA4lg8Lh9p3NmujbH paNqBZwQqClNfcqakwdsonh24Wd0tDJdbMNJf4Jw5h8RJDsM2b0q1zwGlXxGGFX15N1M +s+L1YcVT/kvar0ffWRLmyYxLHxEHgIHaKuZPSF1uWlG4kEv94V/MngATS5qPUozlLaA 6sXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=iqTlbqaEumCeViAxHmy3brKEyzF/IL5OcylNHq80qOA=; b=m7F3heyGfS3xBY562MnWN+fzxOuVrikxt309vKx5JBcSDfC7uxj11iKTAKsw6LxoHg gWDJYwKiEqe1kIhBS7IJFnupMtucjjQA6t6HWgifjs89z1u1ZrERKdoxFoLyMIcGdIoN zEHXrw9yVJgSfRv6caBymRCRCH5No9lSOp8qC1/AC2nATN6FNcUP3ThPDCOwoCp0gORX tDezayYTxPwADsvX51Vi5/IdL4hBPzRQ/R4Qdx+EEapMyc+cZjFS0zMWIpLt4Z4dx+QC ZpFzbIDENCn/5036Tx55sP30VKKWli6ulz+H6uzndDpce0AzHqeH0KTlezXv4Ltu/woP CDbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LlaPsAfS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 09/20] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state Date: Fri, 11 Oct 2019 11:55:35 -0400 Message-Id: <20191011155546.14342-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not need to compute any of these values for M-profile. Further, XSCALE_CPAR overlaps VECSTRIDE so obviously the two sets must be mutually exclusive. Signed-off-by: Richard Henderson --- target/arm/helper.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index ddd21edfcf..e2a62cf19a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11235,21 +11235,28 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { flags = rebuild_hflags_a32(env, fp_el, mmu_idx); + + /* + * Note that XSCALE_CPAR shares bits with VECSTRIDE. + * Note that VECLEN+VECSTRIDE are RES0 for M-profile. + */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + flags = FIELD_DP32(flags, TBFLAG_A32, + XSCALE_CPAR, env->cp15.c15_cpar); + } else { + flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, + env->vfp.vec_len); + flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, + env->vfp.vec_stride); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); - flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - /* Note that XSCALE_CPAR shares bits with VECSTRIDE */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, - XSCALE_CPAR, env->cp15.c15_cpar); - } } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine From patchwork Fri Oct 11 15:55:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175991 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp951134ill; Fri, 11 Oct 2019 09:04:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqwkPhcewz+pQv87nU8nhrh88HFAf2ZwQ/qiIlTTW/H13YfXcFR/Mi2X3lwdZZBLBPyIlAVi X-Received: by 2002:ad4:4583:: with SMTP id x3mr17110587qvu.162.1570809890909; Fri, 11 Oct 2019 09:04:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570809890; cv=none; d=google.com; s=arc-20160816; b=SSnpea9af/RrqBa5iTLnFwiCFLobRZz9/UYZRfCqa4gnNVQvJxC9qn+/nE2/ArL9eV Qipd1CkQOdFrxTtuCGQZDNvxFv1zSBX5XCNMBcgkYFXEuruQEiISvTtDXRHhKW1T3iLc rtss5XLR0A3W1Yl9eT89YmipXLieVssbn/E0e0Go7td5f3X9C9M7JwG/BEU8HltzvEeo iNC0b9EDVOvfRb0waazdlKA9K45vKHs9al1xF+TjHgOLTfzA5YIWWBF7wnaZtx0ignVn kBnvPTmEqyniAspZR/YpKXQ5LsuyQEhLgKgqPiGMKhQxoObsTmISJFTN87m6yHiJckwu Y8MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=v9G2/VGbpNHx6eaShg3TTMn08v+y+t3OtnZPnrlHvrg=; b=bBHnORT2ZuSJOxQJWl6eT7IKgH8rtrTGrwh/Uh8iFUebM8+j4+47rHvMb9MZcNHqL1 pTtlcdV0Oh+47OhIgtI0MAlekCrm94eA9LJ/kJEpw5zHqUwkqG40FN4bf9WJ5g9fOGyr tDfVhYkwsz9SvBSCfSc+wC7bogJ9hnOFRUi2b4ZtX4X8MM3dztlvwKpf++isZBNHZL7W U6V4MRRGjuKebrpHaMB9psHPT48nsGG2JygNn6rHn6dviNuNGJq8Cju68JJcAXLk10pV 2QfSKJ6bkNro/8ytHseVMmSSMRSqV8iZkLY+5QSzy3DZ7a+uSDN8g5ONoicdiF2lUt3B Rhsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XtpZUPFp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j67si9189815qtb.117.2019.10.11.09.04.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Oct 2019 09:04:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XtpZUPFp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxPJ-0003oz-HN for patch@linaro.org; Fri, 11 Oct 2019 12:04:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33777) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxGs-0002VV-Qj for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIxGq-0007hf-Ov for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:02 -0400 Received: from mail-yb1-xb41.google.com ([2607:f8b0:4864:20::b41]:41915) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iIxGq-0007hG-L1 for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:00 -0400 Received: by mail-yb1-xb41.google.com with SMTP id 206so3252987ybc.8 for ; Fri, 11 Oct 2019 08:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v9G2/VGbpNHx6eaShg3TTMn08v+y+t3OtnZPnrlHvrg=; b=XtpZUPFp3W08t1JaA8a0gwAlWG96mYwUetMWaaiCpy9HSMGo6QV8Fw4jCrEVvggsQB vF6tZAvtgIjUmkKmbloMxKxEwZM+b4X7siCA2C/P6Wor8sBPopZKILt6LAi2M7orgBmA 2mfelbVM/AnO9nLlQEHhbWZlpfYUnKKMnRQ6UKhWRHaDbEidF6hjN9nfFBoJkhVcgvQE Ko5O0LeKsAfm2iPhsWrYpS6xC0wvihOaWT6hfwaiozzUWpQIHrgTI2vltkYROdOYrrKT EeJvYM/7yT6M4yHRnCgT9yo7MK1v/PpBwx5xBdIjHwpX8E2XnnzB8AFCMfstHTje3FXA Htuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v9G2/VGbpNHx6eaShg3TTMn08v+y+t3OtnZPnrlHvrg=; b=Ke05nAS2missJZ2+cC6kQYuIWZhsJyTRuH3dCvdcZ/ElUTib9rPlldsYU8ScLQQ6Bf 8rZyD2zQA8FoDB3KSeDRAflPJEHpNByDe8KtvIQuoXDNp1Nup2HqaFvYDjOnXxY4G2k0 tQOjknwm56HfyTKQWf3kOpcZ9xHh4DP/loyFnYp9ntwgcdGjmb7xydrWyWrbqMNMyywz b3GyVTJ5y1WDUT+nWUXql9oUamuVSpZb2wxL7LzUJhE82n1wuPmgvnjU7B0qqJwXpJNB hxkSAKrUBv4V9ww9I2DGHyvDp1vZvztPd/+0acmXQ2wLOLSLRfljZljzgyna2x87PqyV ncQg== X-Gm-Message-State: APjAAAWfMFKVuIlzzghLYKTS1gY9p1638yLG2CvO5Lp5/my7mzdYLAUM Q2EXFsb53nZRKChQpDxLDu7WSMuLAtE= X-Received: by 2002:a25:80c1:: with SMTP id c1mr10793698ybm.195.1570809359625; Fri, 11 Oct 2019 08:55:59 -0700 (PDT) Received: from cloudburst.gateway.pace.com (67.216.151.25.pool.hargray.net. [67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 10/20] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state Date: Fri, 11 Oct 2019 11:55:36 -0400 Message-Id: <20191011155546.14342-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist the variable load for PSTATE into the existing test vs is_a64. Signed-off-by: Richard Henderson --- target/arm/helper.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index e2a62cf19a..398e5f5d6d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11197,7 +11197,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags; + uint32_t flags, pstate_for_ss; if (is_a64(env)) { *pc = env->pc; @@ -11205,6 +11205,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; @@ -11257,9 +11258,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } + pstate_for_ss = env->uncached_cpsr; } - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State * 0 x Inactive (the TB flag for SS is always 0) @@ -11267,16 +11270,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && + (pstate_for_ss & PSTATE_SS)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } *pflags = flags; From patchwork Fri Oct 11 15:55:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175994 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp956342ill; Fri, 11 Oct 2019 09:08:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqztytR3hob3GFDE0hskwvHPMQNOFVfHAUspVfkIonBO0mFFTxS/6Pz2WCuvB7qRHfScC6fe X-Received: by 2002:ac8:1e89:: with SMTP id c9mr18044676qtm.228.1570810117033; Fri, 11 Oct 2019 09:08:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570810117; cv=none; d=google.com; s=arc-20160816; b=cmx12uRGxm1LlGw76o9NlXiVZHtCLYNx9SGKLLmVohXpNTHMpryL+hvL3ef0L0xUNk 1E335T8eEoBtrieqUG4qJ3a4mioNvLQjgKvFnvKzNba0C6QHH65oIodO5SL59CF3CBqQ DiW9ZV50bE2W42AnX19usVF4jFWoB4W7wZixlcuqMbx1XQk52P+rg2E1wkFp9w0Z5tYv f48InlM49PiAslqXtvC9gB9w96jQH2VIkqADTFXQk8MEIPaQD4bH3Lpcu2T3yfATwGNe l1D1qiO2ptVQHscyXm8CGNKMtnSAoOgSvgGWVOcMg2K/x76zhn2B5LQAN2CoENijepoa D7LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=4OOGMGav7WyY+i6Vj46PkAX7nW+w3pL8v7F+DMrUq7Y=; b=C4YFqKblKHt9UyeEs3Ku0nQ09wGxThOVKFgi5JBNrxrF4/SvTRfSNHNYlJEQp3f0Ej rQZDq5T/sK21NK9kGCAOgN+7hUGmd6IxRH3WNHJLHhplI4ug+QFn9Phi6iSGdwliaV7r U3p39+QPvq3iWTqjsIoawJ6YUZEdbnmk3vw9flswdfb/ZKwvUS7TzcyRWCZlep/difKh ABne5wU/WYOWBzDrU0XDNPo2dsGhblLRjSGkearunXVpqLVlq0mf8EIfxR/5B5w3cQTN VkTCy4U9C632r17WW5WgMdWMkc0XEVDhgwLb/yFRjlsjhL+uGlVFohFuZ6a/LlMEY5gh OrMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aILbN6xZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f2si8777301qvj.73.2019.10.11.09.08.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Oct 2019 09:08:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aILbN6xZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53290 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxT2-0007la-66 for patch@linaro.org; Fri, 11 Oct 2019 12:08:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33787) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxGt-0002W1-AE for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIxGs-0007is-2p for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:03 -0400 Received: from mail-yw1-xc44.google.com ([2607:f8b0:4864:20::c44]:36711) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iIxGr-0007iD-VW for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:02 -0400 Received: by mail-yw1-xc44.google.com with SMTP id x64so3651768ywg.3 for ; Fri, 11 Oct 2019 08:56:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4OOGMGav7WyY+i6Vj46PkAX7nW+w3pL8v7F+DMrUq7Y=; b=aILbN6xZ30EdzU7O9mibwUqzEqS2SYXFObkfEjAJZKVPFnRsKsQ7cLSrGAVHICGR4V y3o7gQPy64gjZJ4lN1GLaHIvu5Gf0AQKQp2Kwnd4hPC4LOoeQj0mDoHM0iTZOxSKp79r oKAobjVm6JkBKqFytkWOtvdf/hVVug3pjTQpSpYwLwbi31tVKZsDJg7ocTjwNGL9IMgD 6Vhs/FsABJEFrTFGsKOCCezZDFf9xrpTXRJh+VkzdHmM2YRkCVblHLmFg9nIkmj8nNdj r+/SnYZvW3gGRxeKHEts9pWMhMSsxF7ig26z4IRTkj+4733JmWbcfLjwag+9/wtvfBTI lwJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4OOGMGav7WyY+i6Vj46PkAX7nW+w3pL8v7F+DMrUq7Y=; b=HDbSdpVcYTRwoF4AoThNyJBdnKGPsu7xoTf6GSlelY5yMkEHZn8PdmC91VUXBxVUGd NuEm/gdvNFjaE15jh1jLwz98mLDBPeW8uFxchbNLs2716numavHVzJwZQXDJWYymUPp8 yHSgN/ecFLVYfUKWBEWmnn/9bTP8tgUYQIzQa70kSgcrv6Ya5kJGHQmDXNGmuAWmpi6e Ab/bcHHHQU7J3mIaGmHRaRrn7Rp6VBx8MxbZcm7tic1On51vYTeZ0FvCN9IFNpoKoSR9 1dLiW19dD8z1vibGri+h+UvuShqntoetiAu5mQ6k1rHOeZyH/MRDS936upej8ETfD36w Yrow== X-Gm-Message-State: APjAAAXGsoOSfZ2xUrNSbVgJONwvTS19+gB51vSZTH4JVRhLFxzPL6bE qUKv7+kG8n6aWJdmySMnw76SyPkM0Ak= X-Received: by 2002:a0d:d384:: with SMTP id v126mr2818553ywd.166.1570809360832; Fri, 11 Oct 2019 08:56:00 -0700 (PDT) Received: from cloudburst.gateway.pace.com (67.216.151.25.pool.hargray.net. [67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 11/20] target/arm: Hoist computation of TBFLAG_A32.VFPEN Date: Fri, 11 Oct 2019 11:55:37 -0400 Message-Id: <20191011155546.14342-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are 3 conditions that each enable this flag. M-profile always enables; A-profile with EL1 as AA64 always enables. Both of these conditions can easily be cached. The final condition relies on the FPEXC register which we are not prepared to cache. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d961474ce..9909ff89d4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3192,7 +3192,7 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 398e5f5d6d..89aa6fd933 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11088,6 +11088,9 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, { uint32_t flags = 0; + /* v8M always enables the fpu. */ + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } @@ -11119,6 +11122,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { uint32_t flags = rebuild_hflags_aprofile(env); + + if (arm_el_is_aa64(env, 1)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } @@ -11250,14 +11257,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } pstate_for_ss = env->uncached_cpsr; } From patchwork Fri Oct 11 15:55:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175996 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp959269ill; Fri, 11 Oct 2019 09:10:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqxV6vre2QA+NY5OEcQKr9MKvJCNOH8zTS49zOUr2F3JBVOmx0pqXqCdxzSC24/o3tbgb6kl X-Received: by 2002:ac8:2a66:: with SMTP id l35mr18433432qtl.340.1570810257329; Fri, 11 Oct 2019 09:10:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570810257; cv=none; d=google.com; s=arc-20160816; b=HrJmHJTTsrTyGUBGOVAsPB2p+Y7H6ftl3dTrNi2JJ42LC0ul3HlChyXaJLsVLzMYny MZwnBUbKpH9e/nSkiUin07uy1bh2vcQHMBsOa2sTDhQxekTSdAHlVu7jBcNS023rRC+j Yw6uemtoSJBktffScvsGxrwHUo6/ruoz66TTSChHg6H0pnHIOal/PdqjQPuBOaPq3QFD wTtIYSMVSVD6myvBbS0H8epfwjTx41/00E7zGIx9Oe8xyPZLDi7KCk3bg8riU22+wBLd HMd9S19czG744kbD0Ta8vstm3FODvsJ8nf7xYzfpDRiRCHDsC0J+GfLveReOAyW/zDRG Rd2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=liE7k7KCDLaE4P9fXyFmPEwyl1E5DGcmCPn5aQ0Fr1o=; b=OYYd7ZdVKwzMt//7XQYoakPF9WA8esXQBDRh/gFsa2xE5GljQ5VIMkjgnMTLm5Tj5n ReSU2E6t2K7seKgmwd3IbCXNeyPeUZOrrwYTwGEJrc2h/nKjWDm0DtgZ9mAdGr0g7o7Q yjgB+6PPBFKVBHEqnqzuToVCgXT07wnvgsOS4qoCVpK3S8K3Cs4Sh4dG7XRxaS+WGuSQ z8Xg8VAmyFVevTmI3b400YhJi+wXMREzbQKZInFV1eCGfAnNBTe9/eegec17+3G5wH+E JYOk+e9QytWaU3rWiqSy0WbhjDPfGt1kqCKW1c2sWaNoEtQJvL4kIFk6We4dj6i46Syk aLpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uOz6AHkd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 56si10069907qvn.79.2019.10.11.09.10.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Oct 2019 09:10:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uOz6AHkd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxVI-0002sl-3g for patch@linaro.org; Fri, 11 Oct 2019 12:10:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33815) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIxGu-0002Xx-7y for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIxGt-0007jY-0k for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:04 -0400 Received: from mail-yw1-xc43.google.com ([2607:f8b0:4864:20::c43]:33195) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iIxGs-0007jB-S9 for qemu-devel@nongnu.org; Fri, 11 Oct 2019 11:56:02 -0400 Received: by mail-yw1-xc43.google.com with SMTP id w140so3657474ywd.0 for ; Fri, 11 Oct 2019 08:56:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=liE7k7KCDLaE4P9fXyFmPEwyl1E5DGcmCPn5aQ0Fr1o=; b=uOz6AHkd2d3q7ZVJfUDbFm+UrMVRxVL3WE/P8wG7lVudDqO0pAIurHwyg13Zy3JwOO W38gZMAutEp/EXIBFoZI/UTgKmr/J2KzNbc7Tjr0IVUUKcqRIEvMa+g4nwbTtHUsDqwI ZbSd+S0uOUDh/WboDzSpBxJs3QltLfF5jrJQilj3gwfyZzSt847AV1ny+oSne2bD9afL mX87w3Defe3sOZaUzOAkYgk+CVw3468VRKqckP1oEyEFhv7UUIqQOgZIkXjukn1QSASI XxRRX/hzaCG4NTLPetFVPuYQZT2PcMyVhfV7HP0obG8Qh6oZ5GAgMA+dlxgr1fRYMdNJ h/eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=liE7k7KCDLaE4P9fXyFmPEwyl1E5DGcmCPn5aQ0Fr1o=; b=JEIVY9o+HnBMAxzNYNT7sE5piYjjK4PUIVzfbzMyOKPXtaIBEhlWMqtzoAe4IODPdO S7g8Ql0Mhm0AsDnDnjDX4UkUzcK25DHMXuebXsGDxJeXFnfrhadoIBP72AaIa7MOrDCO cI9NiZma3QJtZtI83+ba9g8AxtX53++i11X/RgiHVObzOAnsTERXCtjrphVWezcQZ5Pk SE014NwDNz9fUL8NV8sVv0zsqjnpF6HUfTz32pwI5ONeAYhTYwuVp3wsF4WacIQZsyZk NdSKOYir8SR4av7fyhD1S1o9HDepKwlo6k0RAKPN07qhEOLuj3OVij2eVl6Y3Azx4c8O zzIA== X-Gm-Message-State: APjAAAVOu5i51uidzUtB3AapgawPaJf24JvKZzs8xB9idkbK94FYEZut 8jNCcPjw/LzG1XdhXlCeSkRhkpyoQKo= X-Received: by 2002:a81:2cc6:: with SMTP id s189mr2934231yws.154.1570809361992; Fri, 11 Oct 2019 08:56:01 -0700 (PDT) Received: from cloudburst.gateway.pace.com (67.216.151.25.pool.hargray.net. [67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 12/20] target/arm: Add arm_rebuild_hflags Date: Fri, 11 Oct 2019 11:55:38 -0400 Message-Id: <20191011155546.14342-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function assumes nothing about the current state of the cpu, and writes the computed value to env->hflags. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 30 ++++++++++++++++++++++-------- 2 files changed, 28 insertions(+), 8 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9909ff89d4..d844ea21d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3297,6 +3297,12 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); +/** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/target/arm/helper.c b/target/arm/helper.c index 89aa6fd933..85de96d071 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11198,17 +11198,35 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_internal(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + + if (is_a64(env)) { + return rebuild_hflags_a64(env, el, fp_el, mmu_idx); + } else if (arm_feature(env, ARM_FEATURE_M)) { + return rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + return rebuild_hflags_a32(env, fp_el, mmu_idx); + } +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + env->hflags = rebuild_hflags_internal(env); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = arm_mmu_idx(env); - int current_el = arm_current_el(env); - int fp_el = fp_exception_el(env, current_el); uint32_t flags, pstate_for_ss; + flags = rebuild_hflags_internal(env); + if (is_a64(env)) { *pc = env->pc; - flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } @@ -11217,8 +11235,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->regs[15]; if (arm_feature(env, ARM_FEATURE_M)) { - flags = rebuild_hflags_m32(env, fp_el, mmu_idx); - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { @@ -11242,8 +11258,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags = rebuild_hflags_a32(env, fp_el, mmu_idx); - /* * Note that XSCALE_CPAR shares bits with VECSTRIDE. * Note that VECLEN+VECSTRIDE are RES0 for M-profile. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 13/20] target/arm: Split out arm_mmu_idx_el Date: Fri, 11 Oct 2019 11:55:39 -0400 Message-Id: <20191011155546.14342-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Avoid calling arm_current_el() twice. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 9 +++++++++ target/arm/helper.c | 12 +++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d963875..f5313dd3d4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -949,6 +949,15 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); +/** + * arm_mmu_idx_el: + * @env: The cpu environment + * @el: The EL to use. + * + * Return the full ARMMMUIdx for the translation regime for EL. + */ +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); + /** * arm_mmu_idx: * @env: The cpu environment diff --git a/target/arm/helper.c b/target/arm/helper.c index 85de96d071..3f7d3f257d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11026,15 +11026,12 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) } #endif -ARMMMUIdx arm_mmu_idx(CPUARMState *env) +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { - int el; - if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } - el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { return ARMMMUIdx_S1SE0 + el; } else { @@ -11042,6 +11039,11 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) } } +ARMMMUIdx arm_mmu_idx(CPUARMState *env) +{ + return arm_mmu_idx_el(env, arm_current_el(env)); +} + int cpu_mmu_index(CPUARMState *env, bool ifetch) { return arm_to_core_mmu_idx(arm_mmu_idx(env)); @@ -11202,7 +11204,7 @@ static uint32_t rebuild_hflags_internal(CPUARMState *env) { int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); - ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); if (is_a64(env)) { return rebuild_hflags_a64(env, el, fp_el, mmu_idx); From patchwork Fri Oct 11 15:55:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175998 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp963021ill; Fri, 11 Oct 2019 09:13:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqyE0kOUxERP5x2FFr9n530ZsQf4pJJ7Ss+hzJGuiCpj87IoovsD5zDXsKMjP+8HKrzLWYaO X-Received: by 2002:a17:906:2d49:: with SMTP id e9mr14545583eji.240.1570810423749; Fri, 11 Oct 2019 09:13:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570810423; cv=none; d=google.com; s=arc-20160816; b=WThkwd9tPsyL4on5oIqKnJ9lomz/C06cfdkYKFDd9Y1WjGTMkG6vCIGmaHwVA7KnZL UXoenW+vtyHpQpBKWOXeBI1NEFyQmuv2QGf6FQ2sTpTfifumRt0Cb6eutiMKEYHhKKen LnzvHVxRUjn7U+mH7U/qmwzJNeON7Cc8AdR18r6IDjZMuAQLP8tPzN+TzvOXB2fcuXre 5D71wdEbO2c0QwiY0E6/4vC4zo6VaWbTlmWkSY7AJ40E3WlmCUHIAxBb3Kv7J0NUbM0q 6tJ4LHYvFDLKP+tbwGtK+0k7n95DD5TFMrh0Hv5Up/KF+6MkgLh1IybzkcAWNLITdXDe vu/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=ReDLvA+WR/T82Ne1Z6mUqgY0iX8aRnhgEWdNBPA2eNw=; b=AXrUN3l54lab/MMHlJMeGAk9/11Sqty4+Qoqky1OgtA1Z8JY1P6tHFoQsHJfK6B+V+ hvOb0vZ1BiPnTMBuvR5W9y3HVD0lUGy4Vq9eBZZJ8YGzF9zKhofeQIIq3K5TrBf1q+2A R7aYcSM5qSwMkW9YARko7yyQQTmsKAGWiXXAh91NSqOnQJ68eB70+8f5kd+6iEFrhH4g MMJts1O17hIP/zx7MTEjanqbr2/NLR/Tv9XSCbCEOrCrmbONPWp0GhJYZzLgCvAzFZoR TLBiK1Qbol9QrSIUM4rVbed8vLZ9SpmKSavA6Fw8CEIzmCq2/fcSCXicQl4XZUOZpC3y JQHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wswCKfzZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 14/20] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state Date: Fri, 11 Oct 2019 11:55:40 -0400 Message-Id: <20191011155546.14342-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By performing this store early, we avoid having to save and restore the register holding the address around any function calls. Signed-off-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f7d3f257d..37424e3d4d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11225,6 +11225,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { uint32_t flags, pstate_for_ss; + *cs_base = 0; flags = rebuild_hflags_internal(env); if (is_a64(env)) { @@ -11298,7 +11299,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } *pflags = flags; - *cs_base = 0; } #ifdef TARGET_AARCH64 From patchwork Fri Oct 11 15:55:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175999 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp970165ill; Fri, 11 Oct 2019 09:19:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqwstUc605r9sTN8K1jY54WpODD4LM1wriAcLgjxoE1rrSxC3rGtx7EA0kjsDz382Lw7TMGE X-Received: by 2002:a37:b985:: with SMTP id j127mr16478470qkf.337.1570810761121; Fri, 11 Oct 2019 09:19:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570810761; cv=none; d=google.com; s=arc-20160816; b=BxZ+WyezG1LOHoda5qb41JhRhwaxzMwHgo9EOo+Tj0MnGlW20t843PFM8YvAz79SNG 82//bNMoUknpa25B8KJd4U/lYF3+RMRiDhXfotEthSOEzO3UaffNLwrXmDvfPKPC57J5 heszdip1pFtXRLee4wcsatDdTIsfc4jyfM/9r3i8rxhOPZ5Bom0H4wWQpmTa8/4EA6Qh t+Xr5cqGz1pWCTr9FoeBIJjLNX4I+SoUdBTyGiEXnmaFLEjpecQbokJQSG3gfD3KVMMr h+ydjqUhV0f5BkAmcsh4zUlx6y6eXLTcBP28Hm9LFJzAXry2vqSUi11vSP1cbBNJHWht h90Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=Iin/3YIyrPimduLw1VgVV/RDqodmDq3TgBG1S+Tb+Mo=; b=CLd4A1kxoXtoaQZJ/63W0NYvfJemVIHr4KOxHIrqLgdJNmK6TqBYOcXPA5Xl9OaEWR 1uFfUy9DyZPMYK+/n6xTBgr95INW9I8asejtDsiTaAuQ3Bi54hGRzPvgs7pAow2ZOg63 2fMLQVjLCsoyQH5SpMgYBXa8bieUH+0b52hctal9a/WCgHTsdgeKp3qNlNC8AT8fZiak okCEkxMOiCxJR4LGJp8q4R+uwWcoqfwbvz2UnO0QqJw7C1izYCHgqTOJyS7w+duyO/1W JwFuLc8Hspwu0G/l7/57iaMAHquMQ1z+LCYhgj/smawnSLpRrbfSB/dVtDkedIPV/AHJ IBYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lU7J01XE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 15/20] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) Date: Fri, 11 Oct 2019 11:55:41 -0400 Message-Id: <20191011155546.14342-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This functions are given the mode and el state of the cpu and writes the computed value to env->hflags. Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 ++++ target/arm/helper.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.h b/target/arm/helper.h index 1fb2cb5a77..3d4ec267a2 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -90,6 +90,10 @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) + DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37424e3d4d..b2d701cf00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11220,6 +11220,30 @@ void arm_rebuild_hflags(CPUARMState *env) env->hflags = rebuild_hflags_internal(env); } +void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Fri Oct 11 15:55:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176001 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp976101ill; Fri, 11 Oct 2019 09:24:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqwNFvdY7aIYm0IRUhB5XCgHu2F6f1b1IqSJqM16Xpj1FQBc3AHYCUyW0Nca5s639kfWr8+3 X-Received: by 2002:a37:614e:: with SMTP id v75mr16973574qkb.166.1570811063443; Fri, 11 Oct 2019 09:24:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570811063; cv=none; d=google.com; s=arc-20160816; b=NbYXNGJfB8/b58d5U8ieklQVk4jXyeGtWJix7+7ic1dnry85PEBT/LPz3iRxeYsUJZ OFRMpTvElTs5ZJpOje2eytrkvP3iSyn4FLrngux10NbwNvuFRnpN3kWnXe0M/xhhzJt+ Jd05oYbX7HiHqVwBgz/Qfu+n/cKSxuqxXT31V2WHaJ7A1M3mY890NKz4IIglTZD4Aflh 8aGpfM7ChUw4YdXohbe6HxfB/fSPBYYXbK8+OOlGa/5KiPaiWyXVzEfxYZMbyGVvioer xBcCLLm2TgdjgIIn3F3plet0VlZEFdLqZVCh7l2M5LL5eFMl2bQUPezClFj6zV0LmBXj EBuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=ALPpYr32kDp1ytFcWYZfVKvxKTo3nP4X483s1waY7YI=; b=XRBhi824cc99s7M1OO5xk4VANn2FgD0aScoMlorxP36LMETehwhqllnJdI2OPqxpQ+ /cVWnynkMoF3mrp9hj6+3LjtzvB1zuveHBue3tKIcZSo6wkTMGNl9rbAjWCksMNgaCOk h6Uh50mN7UxrV+5XcHOQLwxCetgxJA9CnadDnyTph4Uw530Ej6xDPuMp39WOxYvWGBfk x5xMLR3rM1V90HKb4y8pls/zX21LgRNmjrWpPaVL9qe3o536RBLJMxlkT/6qfUHqKZY+ IGVcSDyta1DOtfG69b8W6t3Tzuml8D9LL1wRUCViLn3wFUSgsM6ZwurcT9rQ6qYdE5hx 0uUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=p+a2RbvW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 16/20] target/arm: Rebuild hflags at EL changes Date: Fri, 11 Oct 2019 11:55:42 -0400 Message-Id: <20191011155546.14342-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 2 ++ target/arm/machine.c | 1 + target/arm/op_helper.c | 1 + 6 files changed, 9 insertions(+) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e2af3c1494..ebefd05140 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9982,6 +9982,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, aarch64_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); ret = vq * 16; } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2399c14471..d043e75166 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -406,6 +406,7 @@ static void arm_cpu_reset(CPUState *s) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bca80bdc38..b4cd680fc4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1025,6 +1025,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } else { env->regs[15] = new_pc & ~0x3; } + helper_rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1036,10 +1037,12 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc = new_pc; + helper_rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index b2d701cf00..aae7b62458 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7998,6 +7998,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->regs[14] = env->regs[15] + offset; } env->regs[15] = newpc; + arm_rebuild_hflags(env); } static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -8345,6 +8346,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); + helper_rebuild_hflags_a64(env, new_el); env->pc = addr; diff --git a/target/arm/machine.c b/target/arm/machine.c index 5c36707a7c..eb28b2381b 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -756,6 +756,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0fd4bd0238..ccc2cecb46 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -404,6 +404,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) * state. Do the masking now. */ env->regs[15] &= (env->thumb ? ~1 : ~3); + arm_rebuild_hflags(env); qemu_mutex_lock_iothread(); arm_call_el_change_hook(env_archcpu(env)); From patchwork Fri Oct 11 15:55:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176000 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp972991ill; Fri, 11 Oct 2019 09:21:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqxDaQNE5LOc3PUOSSpJeXCr0qCQyYCb2yMH+PZdwp/rcivf4JyIYWrqr0k9dLVSxrMC7FCz X-Received: by 2002:a05:620a:693:: with SMTP id f19mr15805275qkh.386.1570810908034; Fri, 11 Oct 2019 09:21:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570810908; cv=none; d=google.com; s=arc-20160816; b=KftrIYgzfW7pWJwCDYLZYacp92e+ygbWGrngV/q/1jXy+7Dp3ww9hxtAIuotUB9cRy Z1DIhhybvinAHEvwQMd/X6wQJkuPQSoemR9iXOULmpTwWwZkqCKqRYAzWgf3rq9mwK9F oB4Yf3x0K251+8NVPS++oLdmWLCM/qtlAB37KXxqDt7xu+9TQ3ceZllRshgS9wlAgNjh NMtxXPeJkf6pmrICwyl6vV5c4DmBs1QQcZ2Jj4V63MZZo8I0lFfROpSR0ccSodq4HNOi /jo5kcdlypj4VjVRGElcgKSPnzMuspKJl91uVK8wSZMMgRejK60zUAOAA5IZ5m5/XkQf 8yow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=cl2cwLMmZGvzhfN3CV68TLR9Wvkj57GFOp1995kUBYY=; b=gRUxr8sD/fecDpdx+fvpU2pSCYaapqQNkKeE2JPlDZEvKvx49Cg/CwVN+HSiQhYLmg I6CzN4QlhJpXP393XVCVag/9pli4OOMRg7T0Gj0WUWBV1QxnIbGxJmZxlmHsKPYKnBZG dRW75kUyxTI1FcRu3D3jFTNKsEujJTLZvQuJreJ/zuO/9nNM7sH1nMioo6EdGNZIhdt8 5xVnYO7ECbf+esXgrRhY8JWKtXpsIjEVXTcJEfXog/xM4UgZcklcWQWvJlziDUwAfgU4 iFmf9U25Md4cTR9uVc52jH3JGA6QdqpWbZ66UQsRwkoqPWkwxMnt4Rxqgu4d1pGB5dbb 7nfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="B49Z/cTC"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 17/20] target/arm: Rebuild hflags at MSR writes Date: Fri, 11 Oct 2019 11:55:43 -0400 Message-Id: <20191011155546.14342-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 13 +++++++++++-- target/arm/translate.c | 28 +++++++++++++++++++++++----- 2 files changed, 34 insertions(+), 7 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634..d4bebbe629 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1789,8 +1789,17 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ s->base.is_jmp = DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 698c594e8c..cb47cd9744 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6890,6 +6890,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -7068,14 +7070,30 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { - /* I/O operations must end the TB here (whether read or write) */ - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && + (ri->type & ARM_CP_IO)); + + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + need_exit_tb = true; + } + if (need_exit_tb) { gen_lookup_tb(s); } From patchwork Fri Oct 11 15:55:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176002 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp979154ill; Fri, 11 Oct 2019 09:26:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqyNl+ZRmhuWv7Db51M5hmh+MsZZzDPaOwlKjnE2rYF/1yQ4RGujlM9sCvjMhEH0+ox0JMsd X-Received: by 2002:a17:906:2319:: with SMTP id l25mr14735281eja.309.1570811216230; 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 18/20] target/arm: Rebuild hflags at CPSR writes Date: Fri, 11 Oct 2019 11:55:44 -0400 Message-Id: <20191011155546.14342-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- target/arm/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ccc2cecb46..b529d6c1bf 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -224,6 +224,7 @@ uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) void HELPER(setend)(CPUARMState *env) { env->uncached_cpsr ^= CPSR_E; + arm_rebuild_hflags(env); } /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. @@ -387,6 +388,8 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) { cpsr_write(env, val, mask, CPSRWriteByInstr); + /* TODO: Not all cpsr bits are relevant to hflags. */ + arm_rebuild_hflags(env); } /* Write the CPSR for a 32-bit exception return */ From patchwork Fri Oct 11 15:55:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175986 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp942722ill; Fri, 11 Oct 2019 08:58:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqx07sDj17lM0rzMdd7+oCoHIsPaG8glRaKMT62EDxWS4ntfuNY5bSVStEUeJ8PJ9Ra18tre X-Received: by 2002:a17:907:2172:: with SMTP id rl18mr14821324ejb.125.1570809515363; Fri, 11 Oct 2019 08:58:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570809515; cv=none; d=google.com; s=arc-20160816; b=tS402XuF+N1+rlDs5Sq43H41nWEBV3dHvb74oEa7N7ubO/kNCFBOthE4pOol4nNxYe 21IRyvuIhaOR+8+3cOCD91+DrAUE1XSp54cP8UyDxGSZnGn6pp4Kb6f909vMZLCPcHYM SbpY4AFlT5eloAH/1ZR2taHkzuDEb7XtVrlsjGFg+R7rJ2tqhqKUT6stS0go8Trrc4+Y C3ZxEG60Lx1NvX14Povvdu5QMwX3/aFrVu24OLVEodQSZ14XUTkTLQ/EscL0nKFdjf6U QMFJRAb+ZZSALGBS6xhZ79he69ytrW7LQtlhg5M3C0lMwSUzieDYylQm5ehGFf87OvNx 5xUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=DCSw/5tSs06WnyBBz0elixvkoTyCltSaS21y5mPKf08=; b=Yu0yLUYivBpxcQS8bO2NrZGpDBOIUolpTw38Z+LKa+MfhsVq3ApfQG7uYe4AxPUGNR zl/Dx3+8BzXj+iGgahda6urUV+lOWO2T3E3w7mmcK+zmtw6Y40AUjqOXHaJ5XDUeUNCO 2ZPCy0sBWS/0aZ4lq0Xs6Y4bWjCiLElP5DJfxlHcVOmwZQ7mFA6PnBc3XUoTOBIH6vKt ZPBYSEjJWeW6Eu6itE8jX3J2bxhKGrafLWNrtb/WAQYkA9pyu1resBXDfVHmUR4SnO3y yj9AfsUmcXoQxiGnjztvsUOUjj7+AdYFaVij5NT6fEv5Tr5gTp96rceXU6oroc1ljLVT +Fxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RZk1XQ0A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 19/20] target/arm: Rebuild hflags for M-profile. Date: Fri, 11 Oct 2019 11:55:45 -0400 Message-Id: <20191011155546.14342-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c2f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- target/arm/m_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 27cd2f3f96..f2512e448e 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -494,6 +494,7 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, dest & 1); env->thumb = 1; env->regs[15] = dest & ~1; + arm_rebuild_hflags(env); } void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) @@ -555,6 +556,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, 0); env->thumb = 1; env->regs[15] = dest; + arm_rebuild_hflags(env); } static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, @@ -895,6 +897,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, env->regs[14] = lr; env->regs[15] = addr & 0xfffffffe; env->thumb = addr & 1; + arm_rebuild_hflags(env); } static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, @@ -1765,6 +1768,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Otherwise, we have a successful exception exit. */ arm_clear_exclusive(env); + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } @@ -1837,6 +1841,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) xpsr_write(env, 0, XPSR_IT); env->thumb = newpc & 1; env->regs[15] = newpc & ~1; + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); return true; @@ -1959,6 +1964,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4; + arm_rebuild_hflags(env); return true; gen_invep: From patchwork Fri Oct 11 15:55:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 176003 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp983454ill; Fri, 11 Oct 2019 09:30:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqwxSrFjwzzXF4Pc+rAFMGeKMhKU3795uaJoQZLn/Fq2NmZJ4MqjZ21G6gFSpyw65XwtCqyl X-Received: by 2002:a17:906:6a8e:: with SMTP id p14mr14620480ejr.137.1570811429857; Fri, 11 Oct 2019 09:30:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570811429; cv=none; d=google.com; s=arc-20160816; b=W35kBkPCoKDsh1l62Z1Lha6qGQKZGdPlB8TGlWBMuD2lBgNV9Ki9YhwP6NR4SwD1bL SCcHLWf7Zuxb5j/rj1hoxXnxjXN6BTE6juhmlHF7EWwJ+vtj2D7KZuYioq2EBRZqgi6u Z2/9xVk7QYxy1oA6LHcQFUmRDJ4IZlkc10bDTB3hMsVx0O7SlsNpBO7Jeh4qXYAaGpam r9EboOWVVJCyHLhyLn6YgrFbG57gGpv73Qa8ExXi/kj2JjwIzPSStSEYFtuYB4/4DC/4 ieiI3gyDqbYYuQA88+xGQdkV/+8uRd/cUjRCvqT6i6P2HESpvXL3SDkh29AnvXEaRsVu ETcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5TK2BjuSMMDdIP7qbR+6sWroGlmanOV91VZR8RZQmXE=; b=Nm4rX0w3MmQwLMBZh8Ui4ljdFz46nP4absS8LpkAUwu8eOX9qAAeHJK3Zuq5gSmRmL Kmvzgdl9EsAVr+WYR6rjdM6/h+gJ3scoz915K772WlA3jE1hou/sbIi4AoEXZ37NXxJU BtbdATxPSiqzfLI/YBvB4brTsqdEbaj85SafkJXef++8ytQZHkEkFjTrIvYGeleYNp3E ojLaetm/+z0gYjUR+emYgK7o4Hbt/GIrOtm+AYmKj7Orzf5xtknLJaNzDJCSu1CGzSnC uvq5MwwJe4/fBIDkMSVKvbii/iWhzgtyOXBPn6iLAV1t+x7xakQAOXiXgrMOKjhmu3aA a3EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a2ptiFRh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:56:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 20/20] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state Date: Fri, 11 Oct 2019 11:55:46 -0400 Message-Id: <20191011155546.14342-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011155546.14342-1-richard.henderson@linaro.org> References: <20191011155546.14342-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the payoff. >From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both 0.55% fp_exception_el - 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state - 6.96% cpu_get_tb_cpu_state 3.63% aa64_va_parameters_both 0.60% fp_exception_el 0.53% sve_exception_el AFTER: - 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr - 13.03% helper_lookup_tb_ptr + 11.19% tb_htable_lookup 0.55% cpu_get_tb_cpu_state 0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state 0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64 Before, helper_lookup_tb_ptr is the second hottest function in the application, consuming almost a quarter of the runtime. Within the entire execution, cpu_get_tb_cpu_state consumes about 12%. After, helper_lookup_tb_ptr has dropped to the fourth hottest function, with consumption dropping to a sixth of the runtime. Within the entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the supporting function to rebuild hflags also consumes about 1%. Assertions are retained for --enable-debug-tcg. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v2: Retain asserts for future debugging. --- target/arm/helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index aae7b62458..c3e3dd2c41 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11249,12 +11249,15 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - uint32_t flags, pstate_for_ss; + uint32_t flags = env->hflags; + uint32_t pstate_for_ss; *cs_base = 0; - flags = rebuild_hflags_internal(env); +#ifdef CONFIG_DEBUG_TCG + assert(flags == rebuild_hflags_internal(env)); +#endif - if (is_a64(env)) { + if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { *pc = env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);