From patchwork Sun Oct 13 11:40:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 176071 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3236791ill; Sun, 13 Oct 2019 04:40:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqw+SvS5WQcTXMPiZ+r8GPviRslBtFjkNnMh58G7EVRcwlDNfR89vxrPDLKPljAKuxdaHq5r X-Received: by 2002:a17:906:2cca:: with SMTP id r10mr23902151ejr.108.1570966857568; Sun, 13 Oct 2019 04:40:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570966857; cv=none; d=google.com; s=arc-20160816; b=No+uXT8nN+HzpcgVxXPNvvqaLmT6Dg/0ysnB6lpTZ61vD2jS/cKOu44M9DBNm2xF+d Zm54Grw4VOh53VPyMx1BR6HkPFNYeZxSw0VChuzVnfyVDafYjXtu6jBv3Ed2APt8chGY 87yaXKokIKIz/l12+UcMUUrgftkyKwTRcyk4z72KI/b+YG1UdZTBHDPhiGxC7/B7k9Ph P2+Cl+4rndsjb5kqypWDqkv6v0iopn6QVbav3FgAxnVR/kCz37JsITA3qQBkZofSMQ4j bTZfoDsYQHcXk6sz38LiAIWpeecKvtCYy7Wk/Ilaa4h8m4qvxDuExzsUnoj8n1IcXzjH UhvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=P585Wb4GdNSdANLbtZBTejDHy0hzt6pLG6Y0SHAZ9bU=; b=x6EBbl5DF4kOHXjX2EXAVEtQQ7Tp0fKEtCucQ/7rR26hj92WiblouxeUjiQcWzyGh0 QIen67N3Bg8X/8p1jJPEozueh/vJ9A2E1DmC2+FQmp72QZOjAuswx35zHRAJ8LSV37M9 ypfTR8114NyzBYfY9uP3bVLv6f0/P66/2K0DLRiZaclGVnDodb+SkbkZDDN4lX3Zt6zS g2dN9cPpfbMj/2TiclhvUIH37mUpUCWi5IRwqhXEi8Ksy4wdjjA4xsP4PBFFcMZSjtaT 81TdCBC52wdZDiPW//HKouM35Mp6iMcmwcQUCifCkp8GtaAzi2fmkLEyR8rks+uemze8 HsMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Sq/HNP5Q"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g90si10874865edd.329.2019.10.13.04.40.57; Sun, 13 Oct 2019 04:40:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Sq/HNP5Q"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729026AbfJMLkz (ORCPT + 22 others); Sun, 13 Oct 2019 07:40:55 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:45485 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728956AbfJMLky (ORCPT ); Sun, 13 Oct 2019 07:40:54 -0400 Received: by mail-pg1-f196.google.com with SMTP id r1so7230928pgj.12 for ; Sun, 13 Oct 2019 04:40:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P585Wb4GdNSdANLbtZBTejDHy0hzt6pLG6Y0SHAZ9bU=; b=Sq/HNP5QsB5o9F9tBTKX7L0Z4FVLC9h6ADI4RXKZarXPk/p/8UNkZ86I+L11wvyGVV WW8lS+FpIJyO77xwLrV2x1AfGD6yZENx63WR/afl2Tyt4GVgcX6zmS/G67iyJNlikhf4 s+R/CfgSkBDkP+rEZhiDL3NLFfwyKzzfmUMd6ekeh0dVZER5Ro6A9nJ/dVS9craL7b1M WDfkcbovDfQ+6LC95Cl4ViIvZxDEAHrsGpeZsmnj4t4etr4FLdjkcFuzOnaFw/LzkjzP U8wiHmqErCnk7duw39vPp9nejXK5KcCFcbZQIVf01CsY/HkWyagT7sBFbM0wjaosBS4y jJbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P585Wb4GdNSdANLbtZBTejDHy0hzt6pLG6Y0SHAZ9bU=; b=YqhrONHmeefjVLk8KfpszhehY7VmI3Q0pQy0K8CyNh72ALPe2WrBc0U3zzexGX/5Fn 6qmQ+SUsE+h1DA673KeIjBghT//XJzkfXnXRq+gqTW3LU+KjwCnobxCbqV5zQAy1kVmx oTPWhD7xdu2SS8ZOcuT4E27UajLnh3J5JPnXtD8wHH5wk9N1uTuqwV9LwaylShooCkq6 iS+KlYetaaE86/Rb1NaJKeKgMd0ROGbL61FtujRRjdClDkPtQpdxdscv7STDhLBXeWBT CJp/l9LOxVOwIPzxh95VCEDFNdDlQqNCAsCdKehxa3xZh29eeHtqvG/sB2rzXPjbx4dX wR0g== X-Gm-Message-State: APjAAAW8dX2beQVmZTi6HlkTj4SJ4YFVQbIOfoXV5dTH0+IUGJXyIvUe IjSPUmwNsMntS6XxUWBZBZb/ X-Received: by 2002:a65:6408:: with SMTP id a8mr27308726pgv.357.1570966853733; Sun, 13 Oct 2019 04:40:53 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:8e:4f53:b957:652b:7622:f311]) by smtp.gmail.com with ESMTPSA id g12sm23165736pfb.97.2019.10.13.04.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2019 04:40:53 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, bgolaszewski@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, orsonzhai@gmail.com, Manivannan Sadhasivam Subject: [PATCH 1/4] dt-bindings: gpio: Add devicetree binding for RDA Micro GPIO controller Date: Sun, 13 Oct 2019 17:10:34 +0530 Message-Id: <20191013114037.9845-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191013114037.9845-1-manivannan.sadhasivam@linaro.org> References: <20191013114037.9845-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add YAML devicetree binding for RDA Micro GPIO controller. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/gpio/gpio-rda.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-rda.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/gpio/gpio-rda.yaml b/Documentation/devicetree/bindings/gpio/gpio-rda.yaml new file mode 100644 index 000000000000..6ece555f074f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-rda.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-rda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Micro GPIO controller + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: rda,8810pl-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + ngpios: + description: + Number of available gpios in a bank. + minimum: 1 + maximum: 32 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - ngpios + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +... 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Signed-off-by: Manivannan Sadhasivam --- drivers/gpio/Kconfig | 8 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rda.c | 334 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 343 insertions(+) create mode 100644 drivers/gpio/gpio-rda.c -- 2.17.1 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 38e096e6925f..71826e61fdb3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -435,6 +435,14 @@ config GPIO_RCAR help Say yes here to support GPIO on Renesas R-Car SoCs. +config GPIO_RDA + bool "RDA Micro GPIO controller support" + depends on ARCH_RDA || COMPILE_TEST + depends on OF_GPIO + select GPIOLIB_IRQCHIP + help + Say Y here to support RDA Micro GPIO controller. + config GPIO_REG bool help diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d2fd19c15bae..5c68c9a48fa3 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -115,6 +115,7 @@ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o +obj-$(CONFIG_GPIO_RDA) += gpio-rda.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_GPIO_REG) += gpio-reg.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o diff --git a/drivers/gpio/gpio-rda.c b/drivers/gpio/gpio-rda.c new file mode 100644 index 000000000000..5a4adeb25f72 --- /dev/null +++ b/drivers/gpio/gpio-rda.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RDA Micro GPIO driver + * + * Copyright (C) 2012 RDA Micro Inc. + * Copyright (C) 2019 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +#define RDA_GPIO_OEN_VAL 0x00 +#define RDA_GPIO_OEN_SET_OUT 0x04 +#define RDA_GPIO_OEN_SET_IN 0x08 +#define RDA_GPIO_VAL 0x0c +#define RDA_GPIO_SET 0x10 +#define RDA_GPIO_CLR 0x14 +#define RDA_GPIO_INT_CTRL_SET 0x18 +#define RDA_GPIO_INT_CTRL_CLR 0x1c +#define RDA_GPIO_INT_CLR 0x20 +#define RDA_GPIO_INT_STATUS 0x24 + +#define RDA_GPIO_IRQ_RISE_SHIFT 0 +#define RDA_GPIO_IRQ_FALL_SHIFT 8 +#define RDA_GPIO_DEBOUCE_SHIFT 16 +#define RDA_GPIO_LEVEL_SHIFT 24 + +#define RDA_GPIO_IRQ_MASK 0xff + +/* Each bank consists of 32 GPIOs */ +#define RDA_GPIO_BANK_NR 32 + +struct rda_gpio { + struct gpio_chip chip; + void __iomem *base; + spinlock_t lock; + struct irq_chip irq_chip; + int irq; +}; + +static void rda_gpio_update(struct gpio_chip *chip, unsigned int offset, + u16 reg, int val) +{ + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + unsigned long flags; + u32 tmp; + + spin_lock_irqsave(&rda_gpio->lock, flags); + tmp = readl_relaxed(base + reg); + + if (val) + tmp |= BIT(offset); + else + tmp &= ~BIT(offset); + + writel_relaxed(tmp, base + reg); + spin_unlock_irqrestore(&rda_gpio->lock, flags); +} + +static int rda_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + /* Not supported currently */ + return 0; +} + +static void rda_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + /* Not supported currently */ +} + +static int rda_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + rda_gpio_update(chip, offset, RDA_GPIO_OEN_SET_IN, 1); + + return 0; +} + +static int rda_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + rda_gpio_update(chip, offset, RDA_GPIO_OEN_SET_OUT, 1); + + return 0; +} + +static int rda_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + + if (readl_relaxed(base + RDA_GPIO_OEN_VAL) & BIT(offset)) + return !!(readl_relaxed(base + RDA_GPIO_VAL) & BIT(offset)); + else + return !!(readl_relaxed(base + RDA_GPIO_SET) & BIT(offset)); +} + +static void rda_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + if (value) + rda_gpio_update(chip, offset, RDA_GPIO_SET, 1); + else + rda_gpio_update(chip, offset, RDA_GPIO_CLR, 1); +} + +static void rda_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + u32 offset = irqd_to_hwirq(data); + u32 value; + + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); +} + +static void rda_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + rda_gpio_update(chip, offset, RDA_GPIO_INT_CLR, 1); +} + +static int rda_gpio_set_irq(struct gpio_chip *chip, u32 offset, + unsigned int flow_type) +{ + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + void __iomem *base = rda_gpio->base; + u32 value; + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + /* Set rising edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_EDGE_FALLING: + /* Set falling edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_EDGE_BOTH: + /* Set both edge trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + + /* Switch to edge trigger interrupt */ + value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); + break; + + case IRQ_TYPE_LEVEL_HIGH: + /* Set high level trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT; + + /* Switch to level trigger interrupt */ + value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + break; + + case IRQ_TYPE_LEVEL_LOW: + /* Set low level trigger */ + value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT; + + /* Switch to level trigger interrupt */ + value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT; + writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static void rda_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + u32 trigger = irqd_get_trigger_type(data); + + rda_gpio_set_irq(chip, offset, trigger); +} + +static int rda_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + int ret; + + ret = rda_gpio_set_irq(chip, offset, flow_type); + if (ret) + return ret; + + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + irq_set_handler_locked(data, handle_level_irq); + else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + irq_set_handler_locked(data, handle_edge_irq); + + return 0; +} + +static void rda_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct irq_chip *ic = irq_desc_get_chip(desc); + struct rda_gpio *rda_gpio = gpiochip_get_data(chip); + unsigned long status; + u32 n, girq; + + chained_irq_enter(ic, desc); + + status = readl_relaxed(rda_gpio->base + RDA_GPIO_INT_STATUS); + /* Only lower 8 bits are capable of generating interrupts */ + status &= RDA_GPIO_IRQ_MASK; + + for_each_set_bit(n, &status, RDA_GPIO_BANK_NR) { + girq = irq_find_mapping(chip->irq.domain, n); + generic_handle_irq(girq); + } + + chained_irq_exit(ic, desc); +} + +static int rda_gpio_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct gpio_irq_chip *irq; + struct rda_gpio *rda_gpio; + u32 ngpios; + int ret; + + rda_gpio = devm_kzalloc(&pdev->dev, sizeof(*rda_gpio), GFP_KERNEL); + if (!rda_gpio) + return -ENOMEM; + + ret = of_property_read_u32(np, "ngpios", &ngpios); + if (ret < 0) + return ret; + + /* + * Not all ports have interrupt capability. For instance, on + * RDA8810PL, GPIOC doesn't support interrupt. So we must handle + * those also. + */ + rda_gpio->irq = platform_get_irq(pdev, 0); + + rda_gpio->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rda_gpio->base)) + return PTR_ERR(rda_gpio->base); + + spin_lock_init(&rda_gpio->lock); + + rda_gpio->chip.label = dev_name(&pdev->dev); + rda_gpio->chip.ngpio = ngpios; + rda_gpio->chip.base = -1; + rda_gpio->chip.parent = &pdev->dev; + rda_gpio->chip.of_node = np; + rda_gpio->chip.request = rda_gpio_request; + rda_gpio->chip.free = rda_gpio_free; + rda_gpio->chip.get = rda_gpio_get; + rda_gpio->chip.set = rda_gpio_set; + rda_gpio->chip.direction_input = rda_gpio_direction_input; + rda_gpio->chip.direction_output = rda_gpio_direction_output; + + if (rda_gpio->irq >= 0) { + rda_gpio->irq_chip.name = "rda-gpio", + rda_gpio->irq_chip.irq_ack = rda_gpio_irq_ack, + rda_gpio->irq_chip.irq_mask = rda_gpio_irq_mask, + rda_gpio->irq_chip.irq_unmask = rda_gpio_irq_unmask, + rda_gpio->irq_chip.irq_set_type = rda_gpio_irq_set_type, + rda_gpio->irq_chip.flags = IRQCHIP_SKIP_SET_WAKE, + + irq = &rda_gpio->chip.irq; + irq->chip = &rda_gpio->irq_chip; + irq->handler = handle_bad_irq; + irq->default_type = IRQ_TYPE_NONE; + irq->parent_handler = rda_gpio_irq_handler; + irq->parent_handler_data = rda_gpio; + irq->num_parents = 1; + irq->parents = &rda_gpio->irq; + } + + ret = devm_gpiochip_add_data(&pdev->dev, &rda_gpio->chip, rda_gpio); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, rda_gpio); + + return 0; +} + +static const struct of_device_id rda_gpio_of_match[] = { + { .compatible = "rda,8810pl-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rda_gpio_of_match); + +static struct platform_driver rda_gpio_driver = { + .probe = rda_gpio_probe, + .driver = { + .name = "rda-gpio", + .of_match_table = rda_gpio_of_match, + }, +}; + +module_platform_driver_probe(rda_gpio_driver, rda_gpio_probe); + +MODULE_DESCRIPTION("RDA Micro GPIO driver"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL v2"); From patchwork Sun Oct 13 11:40:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 176074 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp3236971ill; Sun, 13 Oct 2019 04:41:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqymRBm+bCPG6gkplBD50aGjJdGeCR745KGpyRexw8A6SoCVbUE7x0RHJ5H970OrKFCtbZRt X-Received: by 2002:a17:906:e2ce:: with SMTP id gr14mr22987126ejb.229.1570966870526; Sun, 13 Oct 2019 04:41:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570966870; cv=none; d=google.com; s=arc-20160816; b=tRDDVoM9Dg2ZHOGEp16XgoZdz/tFhPy3VSsc5OznB1eHiogheIF1t+2NqYpIy9IZb9 E5+OrlpvE2javdkBgXfS+/bxvTxN3+W+E3ehuqF4lTwH8W29ehd8ucbaHG8+6t9sdAdw 1RNGuOFOaQqE01yNwHF8pvKWCyt+gI7Cw5lQ5h+HCV2OF8O0zHxc1+lqZOhNMM1cRdwR /0nAd636kwZN5rvliAuu6JD1SHqkKCEouX4p3vtPo4USm0vi1jZSpHbaY8TgkiAG7Wth 0rB7ZCJ2x13pb586W9W/SJhzmUzg95QsovGkoqtCzuLqxdNgsDvkB8nBVpH6ezTOv0O4 mPIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=7S85Z16eqmxjvMi+R450sz/jCD08hapdQq20bxkJhIQ=; b=Hn1NyKT162o6hss/+gQupDO05aXaagkLm612pTptwzS5WW+uTeL+HU3f0HNtYSKA7p wf/8SmWgQGRKz0UlUrCe7xYEtfuO4LnKVnRy0QaiwYCVQbf6E3MQ2K7h0odY238aAYq2 0RUxMcDsrD/kNq8b4XVE+y8JP6FC3iLvzZyaiwJmZDqErTCHdMLiYBaCy4UQolMWE+fj jDVYucym08Ci7QwYpqMZPXl6Cf+EjqtDDAv+STRTqPNDvs27UEzIyCC+oAUqhV5frR/t veTOesTACiSNBYtxaysM8gUGsy31NNgIGE+cAV3K+EZRAxjwB/h12ZfAueiiWACpj+j2 wVyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H4jNSTdI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index a69e6db80c79..0303502cd146 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2150,9 +2150,11 @@ L: linux-unisoc@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/rda8810pl-* F: drivers/clocksource/timer-rda.c +F: drivers/gpio/gpio-rda.c F: drivers/irqchip/irq-rda-intc.c F: drivers/tty/serial/rda-uart.c F: Documentation/devicetree/bindings/arm/rda.yaml +F: Documentation/devicetree/bindings/gpio/gpio-rda.yaml F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt