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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 01/14] target/s390x: Do not use unwind for per_check_exception Date: Wed, 1 May 2024 22:44:04 -0700 Message-Id: <20240502054417.234340-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Using exception unwind via tcg_s390_program_interrupt, we discard the current value of psw.addr, which discards the result of a branch. Pass in the address of the next instruction, which may not be sequential. Pass in ilen, which we would have gotten from unwind and is passed to the exception handler. Sync cc_op before the call, which we would have gotten from unwind. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/helper.h | 2 +- target/s390x/tcg/excp_helper.c | 2 +- target/s390x/tcg/misc_helper.c | 23 ++++++++++++++++++++--- target/s390x/tcg/translate.c | 13 +++++++------ 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index cc1c20e9e3..96ab71e877 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -359,7 +359,7 @@ DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32) DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env) DEF_HELPER_3(lra, i64, env, i64, i64) -DEF_HELPER_1(per_check_exception, void, env) +DEF_HELPER_FLAGS_3(per_check_exception, TCG_CALL_NO_WG, void, env, i64, i32) DEF_HELPER_FLAGS_3(per_branch, TCG_CALL_NO_RWG, void, env, i64, i64) DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_RWG, void, env, i64) DEF_HELPER_FLAGS_1(per_store_real, TCG_CALL_NO_RWG, void, env) diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index f1c33f7967..4c0b692c9e 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -209,7 +209,7 @@ static void do_program_interrupt(CPUS390XState *env) switch (env->int_pgm_code) { case PGM_PER: - advance = !(env->per_perc_atmid & PER_CODE_EVENT_NULLIFICATION); + /* advance already handled */ break; case PGM_ASCE_TYPE: case PGM_REG_FIRST_TRANS: diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 8764846ce8..8c27998ab9 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" +#include "qemu/log.h" #include "cpu.h" #include "s390x-internal.h" #include "qemu/host-utils.h" @@ -590,10 +591,26 @@ void HELPER(chsc)(CPUS390XState *env, uint64_t inst) #endif #ifndef CONFIG_USER_ONLY -void HELPER(per_check_exception)(CPUS390XState *env) +G_NORETURN static void per_raise_exception(CPUS390XState *env) { - if (env->per_perc_atmid) { - tcg_s390_program_interrupt(env, PGM_PER, GETPC()); + trigger_pgm_exception(env, PGM_PER); + cpu_loop_exit(env_cpu(env)); +} + +G_NORETURN static void per_raise_exception_log(CPUS390XState *env) +{ + qemu_log_mask(CPU_LOG_INT, "PER interrupt after %#" PRIx64 "\n", + env->per_address); + per_raise_exception(env); +} + +void HELPER(per_check_exception)(CPUS390XState *env, uint64_t next_pc, + uint32_t ilen) +{ + if (unlikely(env->per_perc_atmid)) { + env->psw.addr = next_pc; + env->int_pgm_ilen = ilen; + per_raise_exception_log(env); } } diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 90a74ee795..2319dcf259 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6426,13 +6426,14 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { - /* An exception might be triggered, save PSW if not already done. */ - if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { - tcg_gen_movi_i64(psw_addr, s->pc_tmp); - } + TCGv_i64 next_pc = psw_addr; - /* Call the helper to check for a possible PER exception. */ - gen_helper_per_check_exception(tcg_env); + if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { + next_pc = tcg_constant_i64(s->pc_tmp); + } + update_cc_op(s); + gen_helper_per_check_exception(tcg_env, next_pc, + tcg_constant_i32(s->ilen)); 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 02/14] target/s390x: Move cpu_get_tb_cpu_state out of line Date: Wed, 1 May 2024 22:44:05 -0700 Message-Id: <20240502054417.234340-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Ilya Leoshkevich --- target/s390x/cpu.h | 23 ++--------------------- target/s390x/cpu.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 21 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 414680eed1..950f84f316 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -413,27 +413,8 @@ static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) #include "tcg/tcg_s390x.h" -static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - if (env->psw.addr & 1) { - /* - * Instructions must be at even addresses. - * This needs to be checked before address translation. - */ - env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); - } - *pc = env->psw.addr; - *cs_base = env->ex_value; - *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; - if (env->cregs[0] & CR0_AFP) { - *flags |= FLAG_MASK_AFP; - } - if (env->cregs[0] & CR0_VECTOR) { - *flags |= FLAG_MASK_VECTOR; - } -} +void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); #endif /* CONFIG_TCG */ diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index f7194534ae..a8428b5a1e 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -324,6 +324,28 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" +void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + if (env->psw.addr & 1) { + /* + * Instructions must be at even addresses. + * This needs to be checked before address translation. + */ + env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); + } + *pc = env->psw.addr; + *cs_base = env->ex_value; + *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + if (env->cregs[0] & CR0_AFP) { + *flags |= FLAG_MASK_AFP; + } + if (env->cregs[0] & CR0_VECTOR) { + *flags |= FLAG_MASK_VECTOR; + } +} + static const TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, .restore_state_to_opc = s390x_restore_state_to_opc, From patchwork Thu May 2 05:44:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794100 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp78354wrr; Wed, 1 May 2024 22:47:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXze5QoOAXqyIFy4327BdFMKZu8mL4J3I4XEJOVWQlCoQ7teWWHjA9ZOcuIk2/wfbntxhBPuuGsUqPTw8FCS6tp X-Google-Smtp-Source: AGHT+IEdpo5T5x4U8ujy/LgMDr47zAhES0uNkuw/5Wgcjmt5YHhELa2xZqNAj6BTNiVnRLhqsoVf X-Received: by 2002:a05:6214:76e:b0:6a0:aac9:c56f with SMTP id f14-20020a056214076e00b006a0aac9c56fmr4744689qvz.33.1714628854412; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 03/14] target/s390x: Update CR9 bits Date: Wed, 1 May 2024 22:44:06 -0700 Message-Id: <20240502054417.234340-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Update from the PoO 14th edition. Signed-off-by: Richard Henderson Reviewed-by: Thomas Huth Reviewed-by: Ilya Leoshkevich --- target/s390x/cpu.h | 18 +++++++++++------- target/s390x/tcg/misc_helper.c | 2 +- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 950f84f316..1bb723a9d3 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -419,13 +419,17 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, #endif /* CONFIG_TCG */ /* PER bits from control register 9 */ -#define PER_CR9_EVENT_BRANCH 0x80000000 -#define PER_CR9_EVENT_IFETCH 0x40000000 -#define PER_CR9_EVENT_STORE 0x20000000 -#define PER_CR9_EVENT_STORE_REAL 0x08000000 -#define PER_CR9_EVENT_NULLIFICATION 0x01000000 -#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 -#define PER_CR9_CONTROL_ALTERATION 0x00200000 +#define PER_CR9_EVENT_BRANCH 0x80000000 +#define PER_CR9_EVENT_IFETCH 0x40000000 +#define PER_CR9_EVENT_STORE 0x20000000 +#define PER_CR9_EVENT_STORAGE_KEY_ALTERATION 0x10000000 +#define PER_CR9_EVENT_STORE_REAL 0x08000000 +#define PER_CR9_EVENT_ZERO_ADDRESS_DETECTION 0x04000000 +#define PER_CR9_EVENT_TRANSACTION_END 0x02000000 +#define PER_CR9_EVENT_IFETCH_NULLIFICATION 0x01000000 +#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 +#define PER_CR9_CONTROL_TRANSACTION_SUPRESS 0x00400000 +#define PER_CR9_CONTROL_STORAGE_ALTERATION 0x00200000 /* PER bits from the PER CODE/ATMID/AI in lowcore */ #define PER_CODE_EVENT_BRANCH 0x8000 diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 8c27998ab9..02215a7f18 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -644,7 +644,7 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr) /* If the instruction has to be nullified, trigger the exception immediately. */ - if (env->cregs[9] & PER_CR9_EVENT_NULLIFICATION) { + if (env->cregs[9] & PER_CR9_EVENT_IFETCH_NULLIFICATION) { CPUState *cs = env_cpu(env); env->per_perc_atmid |= PER_CODE_EVENT_NULLIFICATION; From patchwork Thu May 2 05:44:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794099 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp78303wrr; Wed, 1 May 2024 22:47:21 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXTHYFNvqhBdJ5JawyIPLhXF2rbqBC77RcE+4v62V2KNFUXTzcBZm+NqiEdn49ZfESEuzTUAHp/F8OK/wACEkIt X-Google-Smtp-Source: AGHT+IGbiuCftIgkt8heEc2Q3DwxmJWpjNLFk51fn+Ud2bK4ENL0wMhAdjjcUe0OGiKnpu0eIDW/ X-Received: by 2002:a05:622a:5e84:b0:439:df8f:3620 with SMTP id er4-20020a05622a5e8400b00439df8f3620mr5555799qtb.64.1714628841108; Wed, 01 May 2024 22:47:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714628841; cv=none; d=google.com; s=arc-20160816; b=UV3Rav2uNN9rABSFJiw1D1Ah93Q+zt9MgNpnmTL37soynQC3h0mUIPdAw1PtmrXt1c yJ6Ha3Nb9ukdE7Gtzm4S9aSfEQYpT2qUSytU48Lvw3Kpp+QyeQa+H0wW+dppsRdtaHTa Jlxn1lhorKrtV66dmLWciPQ2lTaDYjOsEYgOoxA8+YexvMGK9PHCIKbL9du9VJKl62Sc SIpBE32wEGvP5qjfptI/pQsS3T/w2vo7P8la4R4aiOD3/yqap+ezQ4FelNDt2GS/TjRi oPX/74mo6Xdp7Avj3Pk77sWWSqhPoH3QhPzRoPjCIxV3C7S9MdUg5tw5/0vEr/Zl3ikb y8mA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eTJgXj6BQ/JK/6rzFK+ifFZ6FT8Mr6/W4CTv9ig9Cvg=; fh=vvIHVEExtoxBacLa1w/xvEOdET6IjbTxlMJ0GExg4HQ=; b=S4cvzlHctfzIxmXeacHYxrudwRCGuWYcGo+Yn40cZ/XU+MyCDkimlgqs3THgJSCjiN fEeqaZSUkW8o5+eRxrCVQuH5W73gNXQTMCKT0Ub+ZN3mfXamB5kCdcYD+RIBomW9gF/S vzPgK6yHKT206YkQTuD+UTiyqByuVAWG2Xj6sgHhBVwEHtyW4iV+RY/eZL+4MCTpPh1d B8HJ1YzWYAI769yzfabuoe7iH0gZr2ojwNQhouXgBmYrV0VHbC90qMP66yNjF39EhUQb Jf5hY6mBnjZsy+9rxEkTNXtVUjfx4spvWt1uD0E8hYqoMxgKTiBJnbjnEi9ex6+71lAB YUHA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C9y1hu4f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 04/14] target/s390x: Record separate PER bits in TB flags Date: Wed, 1 May 2024 22:44:07 -0700 Message-Id: <20240502054417.234340-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Record successful-branching, instruction-fetching, and store-using-real-address. The other PER bits are not used during translation. Having checked these at translation time, we can remove runtime tests from the helpers. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- target/s390x/cpu.h | 42 ++++++++++++++++++++++++---------- target/s390x/cpu.c | 22 ++++++++++++++---- target/s390x/tcg/misc_helper.c | 21 +++++++---------- target/s390x/tcg/translate.c | 10 ++++---- 4 files changed, 61 insertions(+), 34 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 1bb723a9d3..d6b75ad0e0 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -342,19 +342,32 @@ extern const VMStateDescription vmstate_s390_cpu; /* tb flags */ -#define FLAG_MASK_PSW_SHIFT 31 -#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) -#define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) -#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) -#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) -#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) -#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) -#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ - | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) +#define FLAG_MASK_PSW_SHIFT 31 +#define FLAG_MASK_32 0x00000001u +#define FLAG_MASK_64 0x00000002u +#define FLAG_MASK_AFP 0x00000004u +#define FLAG_MASK_VECTOR 0x00000008u +#define FLAG_MASK_ASC 0x00018000u +#define FLAG_MASK_PSTATE 0x00020000u +#define FLAG_MASK_PER_IFETCH_NULLIFY 0x01000000u +#define FLAG_MASK_DAT 0x08000000u +#define FLAG_MASK_PER_STORE_REAL 0x20000000u +#define FLAG_MASK_PER_IFETCH 0x40000000u +#define FLAG_MASK_PER_BRANCH 0x80000000u -/* we'll use some unused PSW positions to store CR flags in tb flags */ -#define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) -#define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) +QEMU_BUILD_BUG_ON(FLAG_MASK_32 != PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT); +QEMU_BUILD_BUG_ON(FLAG_MASK_64 != PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT); +QEMU_BUILD_BUG_ON(FLAG_MASK_ASC != PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT); +QEMU_BUILD_BUG_ON(FLAG_MASK_PSTATE != PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT); +QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT); + +#define FLAG_MASK_PSW (FLAG_MASK_DAT | FLAG_MASK_PSTATE | \ + FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) +#define FLAG_MASK_CR9 (FLAG_MASK_PER_BRANCH | FLAG_MASK_PER_IFETCH) +#define FLAG_MASK_PER (FLAG_MASK_PER_BRANCH | \ + FLAG_MASK_PER_IFETCH | \ + FLAG_MASK_PER_IFETCH_NULLIFY | \ + FLAG_MASK_PER_STORE_REAL) /* Control register 0 bits */ #define CR0_LOWPROT 0x0000000010000000ULL @@ -431,6 +444,11 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, #define PER_CR9_CONTROL_TRANSACTION_SUPRESS 0x00400000 #define PER_CR9_CONTROL_STORAGE_ALTERATION 0x00200000 +QEMU_BUILD_BUG_ON(FLAG_MASK_PER_BRANCH != PER_CR9_EVENT_BRANCH); +QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH != PER_CR9_EVENT_IFETCH); +QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH_NULLIFY != + PER_CR9_EVENT_IFETCH_NULLIFICATION); + /* PER bits from the PER CODE/ATMID/AI in lowcore */ #define PER_CODE_EVENT_BRANCH 0x8000 #define PER_CODE_EVENT_IFETCH 0x4000 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index a8428b5a1e..2bbeaca36e 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -325,8 +325,10 @@ static void s390_cpu_reset_full(DeviceState *dev) #include "hw/core/tcg-cpu-ops.h" void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) + uint64_t *cs_base, uint32_t *pflags) { + uint32_t flags; + if (env->psw.addr & 1) { /* * Instructions must be at even addresses. @@ -335,15 +337,27 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); } + *pc = env->psw.addr; *cs_base = env->ex_value; - *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + + flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + if (env->psw.mask & PSW_MASK_PER) { + flags |= env->cregs[9] & (FLAG_MASK_PER_BRANCH | + FLAG_MASK_PER_IFETCH | + FLAG_MASK_PER_IFETCH_NULLIFY); + if ((env->cregs[9] & PER_CR9_EVENT_STORE) && + (env->cregs[9] & PER_CR9_EVENT_STORE_REAL)) { + flags |= FLAG_MASK_PER_STORE_REAL; + } + } if (env->cregs[0] & CR0_AFP) { - *flags |= FLAG_MASK_AFP; + flags |= FLAG_MASK_AFP; } if (env->cregs[0] & CR0_VECTOR) { - *flags |= FLAG_MASK_VECTOR; + flags |= FLAG_MASK_VECTOR; } + *pflags = flags; } static const TCGCPUOps s390_tcg_ops = { diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 02215a7f18..b7100c06c0 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -627,18 +627,16 @@ static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr) void HELPER(per_branch)(CPUS390XState *env, uint64_t from, uint64_t to) { - if ((env->cregs[9] & PER_CR9_EVENT_BRANCH)) { - if (!(env->cregs[9] & PER_CR9_CONTROL_BRANCH_ADDRESS) - || get_per_in_range(env, to)) { - env->per_address = from; - env->per_perc_atmid = PER_CODE_EVENT_BRANCH | get_per_atmid(env); - } + if (!(env->cregs[9] & PER_CR9_CONTROL_BRANCH_ADDRESS) + || get_per_in_range(env, to)) { + env->per_address = from; + env->per_perc_atmid = PER_CODE_EVENT_BRANCH | get_per_atmid(env); } } void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr) { - if ((env->cregs[9] & PER_CR9_EVENT_IFETCH) && get_per_in_range(env, addr)) { + if (get_per_in_range(env, addr)) { env->per_address = addr; env->per_perc_atmid = PER_CODE_EVENT_IFETCH | get_per_atmid(env); @@ -659,12 +657,9 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr) void HELPER(per_store_real)(CPUS390XState *env) { - if ((env->cregs[9] & PER_CR9_EVENT_STORE) && - (env->cregs[9] & PER_CR9_EVENT_STORE_REAL)) { - /* PSW is saved just before calling the helper. */ - env->per_address = env->psw.addr; - env->per_perc_atmid = PER_CODE_EVENT_STORE_REAL | get_per_atmid(env); - } + /* PSW is saved just before calling the helper. */ + env->per_address = env->psw.addr; + env->per_perc_atmid = PER_CODE_EVENT_STORE_REAL | get_per_atmid(env); } #endif diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 2319dcf259..3622c5c883 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -348,7 +348,7 @@ static void per_branch(DisasContext *s, bool to_next) #ifndef CONFIG_USER_ONLY tcg_gen_movi_i64(gbea, s->base.pc_next); - if (s->base.tb->flags & FLAG_MASK_PER) { + if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) { TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; gen_helper_per_branch(tcg_env, gbea, next_pc); } @@ -359,7 +359,7 @@ static void per_branch_cond(DisasContext *s, TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2) { #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) { TCGLabel *lab = gen_new_label(); tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); @@ -658,7 +658,7 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_goto_tb(DisasContext *s, uint64_t dest) { - if (unlikely(s->base.tb->flags & FLAG_MASK_PER)) { + if (unlikely(s->base.tb->flags & FLAG_MASK_PER_BRANCH)) { return false; } return translator_use_goto_tb(&s->base, dest); @@ -4411,7 +4411,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); - if (s->base.tb->flags & FLAG_MASK_PER) { + if (s->base.tb->flags & FLAG_MASK_PER_STORE_REAL) { update_psw_addr(s); gen_helper_per_store_real(tcg_env); } @@ -6325,7 +6325,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (s->base.tb->flags & FLAG_MASK_PER_IFETCH) { TCGv_i64 addr = tcg_constant_i64(s->base.pc_next); gen_helper_per_ifetch(tcg_env, addr); } From patchwork Thu May 2 05:44:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794091 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp77973wrr; Wed, 1 May 2024 22:46:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 05/14] target/s390x: Disable conditional branch-to-next for PER Date: Wed, 1 May 2024 22:44:08 -0700 Message-Id: <20240502054417.234340-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For PER, we require a conditional call to helper_per_branch for the conditional branch. Fold the remaining optimization into a call to helper_goto_direct, which will take care of the remaining gbea adjustment. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3622c5c883..c3c821430d 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1133,13 +1133,13 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (is_imm) { - if (dest == s->pc_tmp) { - /* Branch to next. */ - per_branch(s, true); - ret = DISAS_NEXT; - goto egress; - } - if (c->cond == TCG_COND_ALWAYS) { + /* + * Do not optimize a conditional branch if PER enabled, because we + * still need a conditional call to helper_per_branch. + */ + if (c->cond == TCG_COND_ALWAYS + || (dest == s->pc_tmp && + !(s->base.tb->flags & FLAG_MASK_PER_BRANCH))) { ret = help_goto_direct(s, dest); goto egress; } From patchwork Thu May 2 05:44:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794097 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp78292wrr; Wed, 1 May 2024 22:47:19 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWySpvVldBghMRAPlbtcvn3nxXWQyAX5v2K/36ZD8iGPINt7oXU8Hi1cwRG30yVTl8v9nN7TUIMbs5SwdMRL2k0 X-Google-Smtp-Source: AGHT+IFwOqyFnJfDXyPRjWSjmdgIVDGLd5ZTb9v5Ec1Y1NlBWcYSXN7/1XlMWn5ODKOuU/vzOobd X-Received: by 2002:ac8:5911:0:b0:434:7c49:a94e with SMTP id 17-20020ac85911000000b004347c49a94emr4946262qty.27.1714628839545; Wed, 01 May 2024 22:47:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714628839; cv=none; d=google.com; s=arc-20160816; b=KTHR8GJTTaZRNIZCRKomJeLk3bX4rp8gADRHyOP+6u+GXux4ReOxH2iYiXjHd1grOi 5m8vBKATjfhFb1LkZEPj3O8adSV8FmW5VNf2h7OwWTtQJVoodma33k2dSQnDmXUCRgml i9Xjq7kQzPNe5o4if+FESbIp95ZnNnF4cLeCAs9N4NeXZFPTfq9+8NrLj8C7IhxVgevw arRBLDAAOPe7quL/OBB9hL9PnV9P7YUvSXzCjI4mGtu/iUzTRMKIU4dMIiy69+fbVkNx W3IHzmqAuitUxzvotqfdgk7HWiLYuycDmgfWp/u1q5GPvj4Tle1yLNL06L89ZuPvRsGk 6NZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Fuiq9TfywDbJprPpCqgLClsfOUB0xDNyU+e5J9WUAuU=; fh=9GwfIyeiIL8eNND5+Q7Kf1Ayw7DtlMesgHZ8+LlAA6Q=; b=Gcx+/AX1QArCH35ICIA3DgjMLWjcOmjaqy+Zu0/HLdcgJ1WC85y2u+JbZBQEF5Mi3T iMAKA9FTYzG7Qf3OE7H1k5K4AxyVxxkBW9IenmCSu3FED12vL6S08Kpb1Tg6T9v2FXgT Qp6zzuPa7wUAOU88tv1tWm8+pEHG1SuuCIXeWMoPlVh6OQ8WPlD1iZbnOYS3UU7ID9Yp myWHhY+Qq2hYZMHK1RODAPzS+R2GMy1bKXCy6B/aA8Nu8oSNB/LIi2ofDguhl/dwOrYa EF3IU+YHGFtAhXllWivbGuHYaeLcbG/8CbrPK4YaCcH9Zf4L43zAHrwsiiSkyrODXCO6 L/zA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QJs0DrNn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 06/14] target/s390x: Introduce help_goto_indirect Date: Wed, 1 May 2024 22:44:09 -0700 Message-Id: <20240502054417.234340-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a small helper to handle unconditional indirect jumps. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index c3c821430d..b1a93070cb 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1120,6 +1120,13 @@ static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest) } } +static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) +{ + tcg_gen_mov_i64(psw_addr, dest); + per_branch(s, false); + return DISAS_PC_UPDATED; +} + static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { @@ -1150,9 +1157,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, goto egress; } if (c->cond == TCG_COND_ALWAYS) { - tcg_gen_mov_i64(psw_addr, cdest); - per_branch(s, false); - ret = DISAS_PC_UPDATED; + ret = help_goto_indirect(s, cdest); goto egress; } } @@ -1465,9 +1470,7 @@ static DisasJumpType op_bas(DisasContext *s, DisasOps *o) { pc_to_link_info(o->out, s, s->pc_tmp); if (o->in2) { - tcg_gen_mov_i64(psw_addr, o->in2); - per_branch(s, false); - return DISAS_PC_UPDATED; + return help_goto_indirect(s, o->in2); } else { return DISAS_NEXT; } @@ -1497,9 +1500,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps *o) { save_link_info(s, o); if (o->in2) { - tcg_gen_mov_i64(psw_addr, o->in2); - per_branch(s, false); - return DISAS_PC_UPDATED; + return help_goto_indirect(s, o->in2); } else { return DISAS_NEXT; } From patchwork Thu May 2 05:44:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794096 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp78274wrr; Wed, 1 May 2024 22:47:14 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWE7Etm5TK13iEKaQLPXALnuhT7F74tt8fy66/P7RGFny83C6EC7pO/ZtYIHt1/A9Pq0H+OsBnO/BLwAQTi9NX5 X-Google-Smtp-Source: AGHT+IERW0jnupSvLRhsyuHiCT0i/07A6lCjoSTxi/OtcVitKVI0YeeX8jJT11dsMNhvmvso3Om/ X-Received: by 2002:a05:6214:2385:b0:6a0:b3d5:c21a with SMTP id fw5-20020a056214238500b006a0b3d5c21amr4932814qvb.59.1714628834230; Wed, 01 May 2024 22:47:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714628834; cv=none; d=google.com; s=arc-20160816; b=E0gfKvgA8C3QyaYVv6cYvdbfYU/AnKm6koStLRmR2K9mm4evgXlDVdsa3QZ8K2P7fU 4/hhVksMCboSehbIbcyfqOnbAr0J6EczXZlTCFJkHKLgSvkfT26iZ+7CJlgRlZWqx7IJ Ufk/HxdgMgw2dNcV19fv8s/gAD2ezol1hTuRXhYwaFtAUtMt3UaFePDtef5ZYAAsWlmh cGNVLK29TYZg/DRo3NieO0Rv/nv/9GiwctqZkKWlT2d5pWM/FhatLvokh83YVnIukSQs 4Eu8xDL2L1Ujeqson9KYlRCAv5jk0BVjgGqgl+SygjMc1mfJwRHt7ilLY1ZFdwqiVtJF Wz+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bJ19L6XEqsk3lyVXCAHdcn8K6R6cA/YjCpdra8gDDvU=; fh=vvIHVEExtoxBacLa1w/xvEOdET6IjbTxlMJ0GExg4HQ=; b=tpFq/SFDZcAwKSrKqPL1FbZlqr9uZmGPVUoPecqUgkjXKiNgL6Xfk2GvssA945CbGY KKw/+lGqOftFvTSx99JtaorkRYUIIaON82tvV8n0jf/VT4LwFJohHapNK75HKK8xJpsu WfWEpyjSG3RZ34Wdc14Zk+ozuQR4ircwAMBaSwmV+qqUOsIHNjWgD73xsKQV3CP1tLar xSR7plNf/kbjOG7QXn1lwinFg6WDqltQ6RWzX6TiyVU68LBGVvdzlXBMULj/Fjkd8sIH LeX0OYrWzxERN2MYLJ4MWMRpaMAcDf1GGo4laFO9WflRri+LO2jHFkcZiEl7ffamHPct qJ0g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="dZ/N3j57"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 07/14] target/s390x: Simplify help_branch Date: Wed, 1 May 2024 22:44:10 -0700 Message-Id: <20240502054417.234340-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Always use a tcg branch, instead of movcond. The movcond was not a bad idea before PER was added, but since then we have either 2 or 3 actions to perform on each leg of the branch, and multiple movcond is inefficient. Reorder the taken branch to be fallthrough of the tcg branch. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 164 ++++++++++++----------------------- 1 file changed, 56 insertions(+), 108 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index b1a93070cb..e77660ee50 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -355,25 +355,6 @@ static void per_branch(DisasContext *s, bool to_next) #endif } -static void per_branch_cond(DisasContext *s, TCGCond cond, - TCGv_i64 arg1, TCGv_i64 arg2) -{ -#ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) { - TCGLabel *lab = gen_new_label(); - tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); - - tcg_gen_movi_i64(gbea, s->base.pc_next); - gen_helper_per_branch(tcg_env, gbea, psw_addr); - - gen_set_label(lab); - } else { - TCGv_i64 pc = tcg_constant_i64(s->base.pc_next); - tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); - } -#endif -} - static void per_breaking_event(DisasContext *s) { tcg_gen_movi_i64(gbea, s->base.pc_next); @@ -1130,14 +1111,12 @@ static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { - DisasJumpType ret; uint64_t dest = s->base.pc_next + (int64_t)imm * 2; - TCGLabel *lab; + TCGLabel *lab, *over; /* Take care of the special cases first. */ if (c->cond == TCG_COND_NEVER) { - ret = DISAS_NEXT; - goto egress; + return DISAS_NEXT; } if (is_imm) { /* @@ -1147,104 +1126,73 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, if (c->cond == TCG_COND_ALWAYS || (dest == s->pc_tmp && !(s->base.tb->flags & FLAG_MASK_PER_BRANCH))) { - ret = help_goto_direct(s, dest); - goto egress; + return help_goto_direct(s, dest); } } else { if (!cdest) { /* E.g. bcr %r0 -> no branch. */ - ret = DISAS_NEXT; - goto egress; + return DISAS_NEXT; } if (c->cond == TCG_COND_ALWAYS) { - ret = help_goto_indirect(s, cdest); - goto egress; + return help_goto_indirect(s, cdest); } } - if (use_goto_tb(s, s->pc_tmp)) { - if (is_imm && use_goto_tb(s, dest)) { - /* Both exits can use goto_tb. */ - update_cc_op(s); + update_cc_op(s); - lab = gen_new_label(); - if (c->is_64) { - tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); - } else { - tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); - } - - /* Branch not taken. */ - tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, s->pc_tmp); - tcg_gen_exit_tb(s->base.tb, 0); - - /* Branch taken. */ - gen_set_label(lab); - per_breaking_event(s); - tcg_gen_goto_tb(1); - tcg_gen_movi_i64(psw_addr, dest); - tcg_gen_exit_tb(s->base.tb, 1); - - ret = DISAS_NORETURN; - } else { - /* Fallthru can use goto_tb, but taken branch cannot. */ - /* Store taken branch destination before the brcond. This - avoids having to allocate a new local temp to hold it. - We'll overwrite this in the not taken case anyway. */ - if (!is_imm) { - tcg_gen_mov_i64(psw_addr, cdest); - } - - lab = gen_new_label(); - if (c->is_64) { - tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab); - } else { - tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab); - } - - /* Branch not taken. */ - update_cc_op(s); - tcg_gen_goto_tb(0); - tcg_gen_movi_i64(psw_addr, s->pc_tmp); - tcg_gen_exit_tb(s->base.tb, 0); - - gen_set_label(lab); - if (is_imm) { - tcg_gen_movi_i64(psw_addr, dest); - } - per_breaking_event(s); - ret = DISAS_PC_UPDATED; - } + /* + * Ensure the taken branch is fall-through of the tcg branch. + * This keeps @cdest usage within the extended basic block, + * which avoids an otherwise unnecessary spill to the stack. + */ + lab = gen_new_label(); + if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) { + over = gen_new_label(); } else { - /* Fallthru cannot use goto_tb. This by itself is vanishingly rare. - Most commonly we're single-stepping or some other condition that - disables all use of goto_tb. Just update the PC and exit. */ - - TCGv_i64 next = tcg_constant_i64(s->pc_tmp); - if (is_imm) { - cdest = tcg_constant_i64(dest); - } - - if (c->is_64) { - tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b, - cdest, next); - per_branch_cond(s, c->cond, c->u.s64.a, c->u.s64.b); - } else { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 z = tcg_constant_i64(0); - tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); - tcg_gen_extu_i32_i64(t1, t0); - tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); - per_branch_cond(s, TCG_COND_NE, t1, z); - } - - ret = DISAS_PC_UPDATED; + over = NULL; } - egress: - return ret; + if (c->is_64) { + tcg_gen_brcond_i64(tcg_invert_cond(c->cond), + c->u.s64.a, c->u.s64.b, lab); + } else { + tcg_gen_brcond_i32(tcg_invert_cond(c->cond), + c->u.s32.a, c->u.s32.b, lab); + } + + /* Branch taken. */ + if (is_imm) { + tcg_gen_movi_i64(psw_addr, dest); + } else { + tcg_gen_mov_i64(psw_addr, cdest); + } + per_branch(s, false); + + if (is_imm && use_goto_tb(s, dest)) { + tcg_gen_goto_tb(0); + tcg_gen_exit_tb(s->base.tb, 0); + } else if (over) { + tcg_gen_br(over); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + + gen_set_label(lab); + + /* Branch not taken. */ + tcg_gen_movi_i64(psw_addr, s->pc_tmp); + if (use_goto_tb(s, s->pc_tmp)) { + tcg_gen_goto_tb(1); + tcg_gen_exit_tb(s->base.tb, 1); + } + + if (over) { + gen_set_label(over); + return DISAS_PC_UPDATED; + } + + tcg_gen_lookup_and_goto_ptr(); + return DISAS_NORETURN; } /* ====================================================================== */ From patchwork Thu May 2 05:44:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794101 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp78376wrr; Wed, 1 May 2024 22:47:40 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW5O2sOI0efYNlQyWnUCcQuNR2TbXe4H0HJMvyQpAhWX13Vv1Zyjjino5MbawRKCn6g/eXx0Iy00xQ5luLvXtoF X-Google-Smtp-Source: AGHT+IEWRlI1fBynWK2f/aW74/kenCiRdUjuGF4+JgP9jf1vNmnkqE06qjUyQufxF3JTXKHLNFv9 X-Received: by 2002:ac8:5782:0:b0:43b:1546:f899 with SMTP id v2-20020ac85782000000b0043b1546f899mr4940714qta.12.1714628860103; Wed, 01 May 2024 22:47:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714628860; cv=none; d=google.com; s=arc-20160816; b=nUY72v/QtZ/RZvQBbFPPpbOAafsjbxDsqn30FeKH/ogmXSSEqbpNfXI8Jyu0RbGeEK vJvug6vra9Wt44cvLxkpGx4D2x6H7+ohFrfi62kAa92n2MWugLhV5BfmMDD3uhugTy/h hA/Hwq/rrWokID65qjv6dT2WpeTnrm6b8aL7eg/HOup9YnA0Bt3HMS6cfl1qpvNS+Ga8 RGF6j+ANpJe1V1P6PR6rvFUcvbmD/WnKNP8LI98uCpYIBe+n5frAJlMKOOO7ngRqQphl xueR3jkMPZqeCI2gizEHkMhvaCxFh/K9yZtJCROiqqDXHXIKZyRfwW7VAdKxzvxMbpd7 ynDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Vaaa9XarhFGZUE0t2SjhtfY2cRwW+ttdC8tie4SkVgY=; fh=vvIHVEExtoxBacLa1w/xvEOdET6IjbTxlMJ0GExg4HQ=; b=RirXOdn0dCKZPZEK2uubL4TgadmzUMxLk+QSnEOmvjCKYaf6jHYdxVG1f1JDQLXNyo mr1CZoIMn27AME5Q+ReIB56SNZ3aLTOg1G9pkbplI41N8jnMIdWj4en/L3+7xDdkjnyX KnBG62mebwBTwQ0W5ln4+ruUnQG0r9mYRT1xgGP3Ltca7cxi63vbx90SGB08Zq/mNUdK d4C+abNdQCgpxibaswfXKTU0hzEediNo0Nsfx5CxnFD+xouZvJD5YnwGiiI0VFly+ghI z5Q3c5ow/cyUAlYUfb7XIMi0Ml8RQUZGRq1DxZ/cEIp+g3XOti9Rw/Qyx14wBsgSDUN8 TElg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=C8fpeXoM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 08/14] target/s390x: Split per_breaking_event from per_branch_* Date: Wed, 1 May 2024 22:44:11 -0700 Message-Id: <20240502054417.234340-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The breaking-event-address register is updated regardless of PER being enabled. Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index e77660ee50..a384192d15 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -346,8 +346,6 @@ static void update_psw_addr(DisasContext *s) static void per_branch(DisasContext *s, bool to_next) { #ifndef CONFIG_USER_ONLY - tcg_gen_movi_i64(gbea, s->base.pc_next); - if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) { TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; gen_helper_per_branch(tcg_env, gbea, next_pc); @@ -1083,13 +1081,13 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest) { + per_breaking_event(s); if (dest == s->pc_tmp) { per_branch(s, true); return DISAS_NEXT; } if (use_goto_tb(s, dest)) { update_cc_op(s); - per_breaking_event(s); tcg_gen_goto_tb(0); tcg_gen_movi_i64(psw_addr, dest); tcg_gen_exit_tb(s->base.tb, 0); @@ -1103,6 +1101,7 @@ static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest) static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { + per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); per_branch(s, false); return DISAS_PC_UPDATED; @@ -1161,6 +1160,7 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } /* Branch taken. */ + per_breaking_event(s); if (is_imm) { tcg_gen_movi_i64(psw_addr, dest); } else { From patchwork Thu May 2 05:44:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794087 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp77816wrr; Wed, 1 May 2024 22:45:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVZsI+JRvbtMklKAEdo4xAlj/h2qajMH6t/9kOOoBj63SPxnZUfPd5saKAFSCPAANQaM5KW+jbWYOfGhxhX1SoF X-Google-Smtp-Source: AGHT+IFMuON+lonH1I7OwKvKUHC9wcNp6f0HRH46N2vNn+u0F+sH7knzzmchqJXC1kGT+/GFyumM X-Received: by 2002:a05:622a:1345:b0:43a:7bb9:c3dd with SMTP id w5-20020a05622a134500b0043a7bb9c3ddmr1205265qtk.16.1714628724291; Wed, 01 May 2024 22:45:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714628724; cv=none; d=google.com; s=arc-20160816; b=pTOCh+fqVuBb/mTghVYVjlfByLcStuqSgmqM/Gz8tolULzleQzjz8OhuJqlX7KLGlR CBVhCFRoEFWeLzZbwmaf3XAp++NhZhsK0604irIPCtebn/9rdSg+5TTLKJGYv7dI4cek VPyIx8tunR+QN9QMG0uwQuKBFuxQ0ifHAAODanOPsgwsxQNZS0i/6LU2Hv6fy6WKPYfl rHCK73mq4aHOgBc7Tkta5wQfnbqJlaAY+l1aymq0hkJsgFcI5n1PaTSUw1+V4RZakt0D DzAaftkhDTO7fjzsImkH3jUW0qGVCYAnNKtP26B3iTiuVqVYbLHeJBTcA3LbOhm/3fWC sMgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=V/inWHR1OelJkN3zbarItqFQdu7gu0A59SAvE6t91DA=; fh=vvIHVEExtoxBacLa1w/xvEOdET6IjbTxlMJ0GExg4HQ=; b=No7MZMbpKFTDWp2z/Vb+yrj2s2QeWRIVf5C/eBM31OKMhXD2VIBZzVIEovbLq3P50o qlMxW9hT/9XaC/rdc6KsHD7hoAA3D7hEy4/toZYStgqcyIDSJYeRzhztw+WcwVYedSej yMeb0ZBZRT5qRyDuTykis1KiIuM4ja9v4HdvBYfZ5uT4JyIB/GXs93EmM/XfSmCY4LYj /37XXsb8VJM36R/SmeEcSQhhtzDgxQsZciOWCHEsjnROzFhSrtC4BUJZoRSNrX5qnb+R 9Z8HrjCv1ZJjBpuz1wBE1nBjBEZDW3Fh5cHI+juPZ/rwKawu5meZj50xIQN5Xcyy2byl pmug==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E9pnStMZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 09/14] target/s390x: Raise exception from helper_per_branch Date: Wed, 1 May 2024 22:44:12 -0700 Message-Id: <20240502054417.234340-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Drop from argument, since gbea has always been updated with this address. Add ilen argument for setting int_pgm_ilen. Use update_cc_op before calling per_branch. By raising the exception here, we need not call per_check_exception later, which means we can clean up the normal non-exception branch path. Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/misc_helper.c | 15 +++++++---- target/s390x/tcg/translate.c | 48 ++++++++++++---------------------- 3 files changed, 27 insertions(+), 38 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 96ab71e877..061b379065 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -360,7 +360,7 @@ DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env) DEF_HELPER_3(lra, i64, env, i64, i64) DEF_HELPER_FLAGS_3(per_check_exception, TCG_CALL_NO_WG, void, env, i64, i32) -DEF_HELPER_FLAGS_3(per_branch, TCG_CALL_NO_RWG, void, env, i64, i64) +DEF_HELPER_FLAGS_3(per_branch, TCG_CALL_NO_WG, void, env, i64, i32) DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_RWG, void, env, i64) DEF_HELPER_FLAGS_1(per_store_real, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index b7100c06c0..5b1c512367 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -625,13 +625,18 @@ static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr) } } -void HELPER(per_branch)(CPUS390XState *env, uint64_t from, uint64_t to) +void HELPER(per_branch)(CPUS390XState *env, uint64_t dest, uint32_t ilen) { - if (!(env->cregs[9] & PER_CR9_CONTROL_BRANCH_ADDRESS) - || get_per_in_range(env, to)) { - env->per_address = from; - env->per_perc_atmid = PER_CODE_EVENT_BRANCH | get_per_atmid(env); + if ((env->cregs[9] & PER_CR9_CONTROL_BRANCH_ADDRESS) + && !get_per_in_range(env, dest)) { + return; } + + env->psw.addr = dest; + env->int_pgm_ilen = ilen; + env->per_address = env->gbea; + env->per_perc_atmid = PER_CODE_EVENT_BRANCH | get_per_atmid(env); + per_raise_exception_log(env); } void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a384192d15..4a6ef144b7 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -343,12 +343,11 @@ static void update_psw_addr(DisasContext *s) tcg_gen_movi_i64(psw_addr, s->base.pc_next); } -static void per_branch(DisasContext *s, bool to_next) +static void per_branch(DisasContext *s, TCGv_i64 dest) { #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) { - TCGv_i64 next_pc = to_next ? tcg_constant_i64(s->pc_tmp) : psw_addr; - gen_helper_per_branch(tcg_env, gbea, next_pc); + gen_helper_per_branch(tcg_env, dest, tcg_constant_i32(s->ilen)); } #endif } @@ -637,9 +636,6 @@ static void gen_op_calc_cc(DisasContext *s) static bool use_goto_tb(DisasContext *s, uint64_t dest) { - if (unlikely(s->base.tb->flags & FLAG_MASK_PER_BRANCH)) { - return false; - } return translator_use_goto_tb(&s->base, dest); } @@ -1081,37 +1077,38 @@ struct DisasInsn { static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest) { + update_cc_op(s); per_breaking_event(s); + per_branch(s, tcg_constant_i64(dest)); + if (dest == s->pc_tmp) { - per_branch(s, true); return DISAS_NEXT; } if (use_goto_tb(s, dest)) { - update_cc_op(s); tcg_gen_goto_tb(0); tcg_gen_movi_i64(psw_addr, dest); tcg_gen_exit_tb(s->base.tb, 0); return DISAS_NORETURN; } else { tcg_gen_movi_i64(psw_addr, dest); - per_branch(s, false); - return DISAS_PC_UPDATED; + return DISAS_PC_CC_UPDATED; } } static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest) { + update_cc_op(s); per_breaking_event(s); tcg_gen_mov_i64(psw_addr, dest); - per_branch(s, false); - return DISAS_PC_UPDATED; + per_branch(s, psw_addr); + return DISAS_PC_CC_UPDATED; } static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, bool is_imm, int imm, TCGv_i64 cdest) { uint64_t dest = s->base.pc_next + (int64_t)imm * 2; - TCGLabel *lab, *over; + TCGLabel *lab; /* Take care of the special cases first. */ if (c->cond == TCG_COND_NEVER) { @@ -1145,12 +1142,6 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, * which avoids an otherwise unnecessary spill to the stack. */ lab = gen_new_label(); - if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) { - over = gen_new_label(); - } else { - over = NULL; - } - if (c->is_64) { tcg_gen_brcond_i64(tcg_invert_cond(c->cond), c->u.s64.a, c->u.s64.b, lab); @@ -1166,13 +1157,11 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, } else { tcg_gen_mov_i64(psw_addr, cdest); } - per_branch(s, false); + per_branch(s, psw_addr); if (is_imm && use_goto_tb(s, dest)) { tcg_gen_goto_tb(0); tcg_gen_exit_tb(s->base.tb, 0); - } else if (over) { - tcg_gen_br(over); } else { tcg_gen_lookup_and_goto_ptr(); } @@ -1184,15 +1173,9 @@ static DisasJumpType help_branch(DisasContext *s, DisasCompare *c, if (use_goto_tb(s, s->pc_tmp)) { tcg_gen_goto_tb(1); tcg_gen_exit_tb(s->base.tb, 1); + return DISAS_NORETURN; } - - if (over) { - gen_set_label(over); - return DISAS_PC_UPDATED; - } - - tcg_gen_lookup_and_goto_ptr(); - return DISAS_NORETURN; + return DISAS_PC_CC_UPDATED; } /* ====================================================================== */ @@ -6374,7 +6357,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & FLAG_MASK_PER) { + if (s->base.tb->flags & (FLAG_MASK_PER_STORE_REAL | + FLAG_MASK_PER_IFETCH)) { TCGv_i64 next_pc = psw_addr; if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { @@ -6404,7 +6388,7 @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->cc_op = CC_OP_DYNAMIC; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 10/14] target/s390x: Raise exception from per_store_real Date: Wed, 1 May 2024 22:44:13 -0700 Message-Id: <20240502054417.234340-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org At this point the instruction is complete and there's nothing left to do but raise the exception. With this change we need not make two helper calls for this event. Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/misc_helper.c | 4 +++- target/s390x/tcg/translate.c | 7 ++++--- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 061b379065..5611155ba1 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -362,7 +362,7 @@ DEF_HELPER_3(lra, i64, env, i64, i64) DEF_HELPER_FLAGS_3(per_check_exception, TCG_CALL_NO_WG, void, env, i64, i32) DEF_HELPER_FLAGS_3(per_branch, TCG_CALL_NO_WG, void, env, i64, i32) DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_RWG, void, env, i64) -DEF_HELPER_FLAGS_1(per_store_real, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_2(per_store_real, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) DEF_HELPER_2(xsch, void, env, i64) diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 5b1c512367..5f1efc6a32 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -660,11 +660,13 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr) } } -void HELPER(per_store_real)(CPUS390XState *env) +void HELPER(per_store_real)(CPUS390XState *env, uint32_t ilen) { /* PSW is saved just before calling the helper. */ env->per_address = env->psw.addr; + env->int_pgm_ilen = ilen; env->per_perc_atmid = PER_CODE_EVENT_STORE_REAL | get_per_atmid(env); + per_raise_exception_log(env); } #endif diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 4a6ef144b7..041857e720 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -4344,8 +4344,10 @@ static DisasJumpType op_stura(DisasContext *s, DisasOps *o) tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); if (s->base.tb->flags & FLAG_MASK_PER_STORE_REAL) { + update_cc_op(s); update_psw_addr(s); - gen_helper_per_store_real(tcg_env); + gen_helper_per_store_real(tcg_env, tcg_constant_i32(s->ilen)); + return DISAS_NORETURN; } return DISAS_NEXT; } @@ -6357,8 +6359,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } #ifndef CONFIG_USER_ONLY - if (s->base.tb->flags & (FLAG_MASK_PER_STORE_REAL | - FLAG_MASK_PER_IFETCH)) { + if (s->base.tb->flags & FLAG_MASK_PER_IFETCH) { TCGv_i64 next_pc = psw_addr; if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { From patchwork Thu May 2 05:44:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794095 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp78201wrr; Wed, 1 May 2024 22:46:57 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUbKJgVbBvdzV7jANzLAx7uLCaM3EFkEdX1yvO8xjKi96NIQ/ebIKAeRKIaY0P4dehiBKCBjmQ13o031hoRrllt X-Google-Smtp-Source: AGHT+IH71SJ36fypO1wX06DCh290uyOUAsP5Ur8d9eJGV6GJAryEzo6Flc5LIJ5btaWJB0aqSgEc X-Received: by 2002:a05:6214:2024:b0:69b:5a87:21cc with SMTP id 4-20020a056214202400b0069b5a8721ccmr5934458qvf.13.1714628815342; Wed, 01 May 2024 22:46:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714628815; cv=none; d=google.com; s=arc-20160816; b=sFOrMD2sGaTvrSlyPi+HWJ/mz3+CkzE55Yftr/e83LlvqlizLKzSyqDyi3uRjbtPw7 pqdxZS59wL5xUfEleZWgL7UdOux8RVq5hOXDcGpPlt/H4QqTDUbD4XcVzCJcZYiwV9IR 8J0lfMew0o6bzs+JHf4MDZ4X7OHJtUya75/KS53eRQBLzT95iFIw+rTRBGSDtIB9HMTf wqVx/xJWmvfR4hFtb2hGBEPu2Xc8fi3/qlmT+4f96WKShDXJ0EpjPc2ATdi7QSkojKL6 ZOyYkVZysbRQ/w+uwFqvU7qqf7MTuWMvwE20kCifkoFRpOwYUbL3PhMWGiLfQpNynT3e jvpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=a6kRDMy0sQWoEwNjZBte06pFXGZWoKm5T0LNfV/1PDg=; fh=vvIHVEExtoxBacLa1w/xvEOdET6IjbTxlMJ0GExg4HQ=; b=FQ0XMAFa55M9EUAoxAN49Wpd2bF63jIhKP/wflOjxRyb2mtyIHa/fNZluM38x4Nhp2 pl9fSdhgWz79Yao51rbWa/l+Us0mpC69+ywIeH5eKWPJSAHZtj6gyHMKGVZ29aO+H1AT zwqad938IexIdAPwDOaVhnOJ/GZWZ9X84Tyn58qrMoqYOtk/DtdIFvlAnL5FDV8feUzv +woWdRgRPosV0zmWkbb6lMby9k96tQeyP6utEe2PyeleePRxpbeWPi2DLcFOnaY49qoQ Ov9dM+DlAOPmZefFiWmYV51SullqaXSXaohKTEPq0uGWdKML9ycxV25xy/rGHR4QbMha iLOA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e4+t25D8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fixes: 83bb161299c ("target-s390x: PER instruction-fetch nullification event support") Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- target/s390x/helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 5611155ba1..31bd193322 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -361,7 +361,7 @@ DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env) DEF_HELPER_3(lra, i64, env, i64, i64) DEF_HELPER_FLAGS_3(per_check_exception, TCG_CALL_NO_WG, void, env, i64, i32) DEF_HELPER_FLAGS_3(per_branch, TCG_CALL_NO_WG, void, env, i64, i32) -DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_RWG, void, env, i64) +DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_2(per_store_real, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) From patchwork Thu May 2 05:44:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794092 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp77991wrr; Wed, 1 May 2024 22:46:13 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVf7qyaBXip4OjHyq9zuN9AIbKbh60IgBYkrfXxbMxnYv0V71rRm9d0z3zFouoAlcvrOIqEkKWAj2iQA0n6uxyY X-Google-Smtp-Source: AGHT+IFPnVxoeHE5UKhhhyeShWIhZvRXWXZkPdqdZgW8hcAS2/WxO2oPwhGRityzhypE8jmnUKc4 X-Received: by 2002:ac8:5815:0:b0:43b:36e:6103 with SMTP id g21-20020ac85815000000b0043b036e6103mr3588760qtg.31.1714628773079; Wed, 01 May 2024 22:46:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714628773; cv=none; d=google.com; s=arc-20160816; b=Ms9lhv7KkRrm+iFlPFg6uan7GjvX485kZEt9SQKaf1oMyEHJVwYpAgkUNpC3jOlVYF 3DxfrfES3VFEK6f5r+UiUd/srU4iXXzIJ46lPm55G9ApIh4JLQmtd6tWCzqzKcckKkAY QEumIW2KNzGsyY+ujwgteH23UqCYAX6+K/QXhCXA1cO8st5ZIPFuhC/L42QRfesXwL4l maPRokAbxnZvX6W6MxRk9ZnVQrfSCAyevrPnPyOl6KjdwP0n0chDIknlEW+2bM903sqo LwS+0g3XKbDmS4vxWgZhMbJZg0Ey3H1OY54A8xRzYVnAD1Xnim5q5U8eWTYtHHVHujD7 Re2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RRpV+p3uN0SIcNVCCOcIP9JnG3tMdIXRYZSMJANZEE0=; fh=vvIHVEExtoxBacLa1w/xvEOdET6IjbTxlMJ0GExg4HQ=; b=uZxd++CO7wYxRoU0E8cUNxXg5FaV8a9l9NV8n10RiLiMNuuQon9KWLhPKnndCWUR0/ IjV55GtOiqyZGXxnbdmOFg7Lnzpkid8PpvY/88RCiSbzKWXj6oajjYhXdk2guHxL5CF6 aiiAQcEh3W8Gg25aFLnj5HxlDYLGR5ETaRvMmyF8kJTPrq5Q0iXj1XB3IHmlXxApKwW7 VOjJGs17aKCixbnsGxxzkaEAaPw+gKLMYIH+THY8VCZumFkCqrTJy6Cf1Dk6Y1rbrGGN SxCgi775dFrqh2zJGIj0AymnhFfslLhXelvk1yn8eLDi75uoG5BPqHP5tNPvkT108Wlz qelQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="dyyA/BIu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 12/14] target/s390x: Simplify per_ifetch, per_check_exception Date: Wed, 1 May 2024 22:44:15 -0700 Message-Id: <20240502054417.234340-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Set per_address and ilen in per_ifetch; this is valid for all PER exceptions and will last until the end of the instruction. Therefore we don't need to give the same data to per_check_exception. Signed-off-by: Richard Henderson # Conflicts: # target/s390x/tcg/misc_helper.c --- target/s390x/helper.h | 4 ++-- target/s390x/tcg/misc_helper.c | 23 +++++++++-------------- target/s390x/tcg/translate.c | 20 ++++++++++++-------- 3 files changed, 23 insertions(+), 24 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 31bd193322..1a8a76abb9 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -359,9 +359,9 @@ DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32) DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env) DEF_HELPER_3(lra, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(per_check_exception, TCG_CALL_NO_WG, void, env, i64, i32) +DEF_HELPER_FLAGS_1(per_check_exception, TCG_CALL_NO_WG, void, env) DEF_HELPER_FLAGS_3(per_branch, TCG_CALL_NO_WG, void, env, i64, i32) -DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_WG, void, env, i64) +DEF_HELPER_FLAGS_2(per_ifetch, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_FLAGS_2(per_store_real, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env) diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 5f1efc6a32..f5e674a26e 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -604,12 +604,10 @@ G_NORETURN static void per_raise_exception_log(CPUS390XState *env) per_raise_exception(env); } -void HELPER(per_check_exception)(CPUS390XState *env, uint64_t next_pc, - uint32_t ilen) +void HELPER(per_check_exception)(CPUS390XState *env) { + /* psw_addr, per_address and int_pgm_ilen are already set. */ if (unlikely(env->per_perc_atmid)) { - env->psw.addr = next_pc; - env->int_pgm_ilen = ilen; per_raise_exception_log(env); } } @@ -639,23 +637,20 @@ void HELPER(per_branch)(CPUS390XState *env, uint64_t dest, uint32_t ilen) per_raise_exception_log(env); } -void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr) +void HELPER(per_ifetch)(CPUS390XState *env, uint32_t ilen) { - if (get_per_in_range(env, addr)) { - env->per_address = addr; + if (get_per_in_range(env, env->psw.addr)) { + env->per_address = env->psw.addr; + env->int_pgm_ilen = ilen; env->per_perc_atmid = PER_CODE_EVENT_IFETCH | get_per_atmid(env); /* If the instruction has to be nullified, trigger the exception immediately. */ if (env->cregs[9] & PER_CR9_EVENT_IFETCH_NULLIFICATION) { - CPUState *cs = env_cpu(env); - env->per_perc_atmid |= PER_CODE_EVENT_NULLIFICATION; - env->int_pgm_code = PGM_PER; - env->int_pgm_ilen = get_ilen(cpu_ldub_code(env, addr)); - - cs->exception_index = EXCP_PGM; - cpu_loop_exit(cs); + qemu_log_mask(CPU_LOG_INT, "PER interrupt before %#" PRIx64 "\n", + env->per_address); + per_raise_exception(env); } } } diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 041857e720..7cf2920aec 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6260,8 +6260,8 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER_IFETCH) { - TCGv_i64 addr = tcg_constant_i64(s->base.pc_next); - gen_helper_per_ifetch(tcg_env, addr); + /* With ifetch set, psw_addr and cc_op are always up-to-date. */ + gen_helper_per_ifetch(tcg_env, tcg_constant_i32(s->ilen)); } #endif @@ -6360,14 +6360,18 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER_IFETCH) { - TCGv_i64 next_pc = psw_addr; - - if (ret == DISAS_NEXT || ret == DISAS_TOO_MANY) { - next_pc = tcg_constant_i64(s->pc_tmp); + switch (ret) { + case DISAS_TOO_MANY: + s->base.is_jmp = DISAS_PC_CC_UPDATED; + /* fall through */ + case DISAS_NEXT: + tcg_gen_movi_i64(psw_addr, s->pc_tmp); + break; + default: + break; } update_cc_op(s); - gen_helper_per_check_exception(tcg_env, next_pc, - tcg_constant_i32(s->ilen)); + gen_helper_per_check_exception(tcg_env); } #endif From patchwork Thu May 2 05:44:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794089 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp77856wrr; Wed, 1 May 2024 22:45:34 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUYHC1Lno31++2iZfW660vDqPZoL2RA7nJQ7hwhlhc6THgyf+r2IpbMZgSpbOztfD+jtrCGEpcjieza5J79hjU0 X-Google-Smtp-Source: AGHT+IE2rkA7jXlXuGSh5nK+Dh6dCIbe4FnenxaKxBNyzv34TQ5QifiN6nMGo+f9jH65HANrt1FK X-Received: by 2002:a05:6808:1813:b0:3c9:147c:bd22 with SMTP id bh19-20020a056808181300b003c9147cbd22mr5388794oib.29.1714628734378; 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 13/14] target/s390x: Adjust check of noreturn in translate_one Date: Wed, 1 May 2024 22:44:16 -0700 Message-Id: <20240502054417.234340-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If help_op is not set, ret == DISAS_NEXT. Shift the test up from surrounding help_wout, help_cout to skipping to out, as we do elsewhere in the function. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 7cf2920aec..8e9c0847e3 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6343,14 +6343,15 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) } if (insn->help_op) { ret = insn->help_op(s, &o); + if (ret == DISAS_NORETURN) { + goto out; + } } - if (ret != DISAS_NORETURN) { - if (insn->help_wout) { - insn->help_wout(s, &o); - } - if (insn->help_cout) { - insn->help_cout(s, &o); - } + if (insn->help_wout) { + insn->help_wout(s, &o); + } + if (insn->help_cout) { + insn->help_cout(s, &o); } /* io should be the last instruction in tb when icount is enabled */ From patchwork Thu May 2 05:44:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 794093 Delivered-To: patch@linaro.org Received: by 2002:adf:a153:0:b0:34d:5089:5a9e with SMTP id r19csp78081wrr; Wed, 1 May 2024 22:46:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXmpa7da0S2TbkbVFf/jON2PcRcX7UtRinyZDxTlRAH6pyLR15Qu70Ym1p4JUe1e7OIHT32ubmAXISPHsBJxJ/Z X-Google-Smtp-Source: AGHT+IGaJCz9FKqNA+9mmjvasQGAEJS5JIPmnroOdWQdfA8SYi9SYb6seg2v3A+553D/fV6ZAd4K X-Received: by 2002:a05:620a:4083:b0:790:7346:2a49 with SMTP id f3-20020a05620a408300b0079073462a49mr6147318qko.6.1714628788303; Wed, 01 May 2024 22:46:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1714628788; cv=none; d=google.com; s=arc-20160816; b=QlnKVIkfg/rbenETvr4eF9tBmigyEjizC8HbKIDJ0mXe2Y5F+kOHeqZKA3TdhCIA5s IByjMBVjVy20/48rUp5450CF+wKG57TPblc3lBDal8pT/PHQIeAYpNL/knhZCEuO0gFt PgWIgXswlIfcpz0CT6tiS8NsrIL/g7Zi4eUBPKQSVoone9xoL0ZwsCWEk4auqcQLyll5 VummAoTi9OIyfqUV1+uE7w7072TIUoP80fPwJOLwyfeRNSxFVygpTDb6UYazAXF6Z/5G 5vWqEU9/vLgN8nCDBw2+UmbEIEl5Axhi7g8P0cTOEIJKCzEEhhIggnE1ZQLSmGl7v9tf HHUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Zw9e5BtuMbzLeV49JTlnqFQYfmJ+6A5JAzWr8qjGuDw=; fh=vvIHVEExtoxBacLa1w/xvEOdET6IjbTxlMJ0GExg4HQ=; b=EBYrEbsXIz5dhsrsBlq8M85NV5orykwdTzqpw3tEHLBjFQjd+6lIkmJFvJWlp9Mbqn 0MZ35COGTYA+4vdd9pTH4jOPcR11HARq4GrSoW+AxFogRH195XfTSb3VBavjnlKCWjs2 NF6uP4QY9Mab7GuzWBH6JinS3mjkQOvg1RtOSpJKplQxC5WDqPsdZEOlPXllzeAWZ7k/ KQBFPi3tTd3jc9M64jEcmMHlgn9ia6rezbgMOWbmPEz+vHX1DLVOkOJh+6O+Y5eun4H6 YbsHZIDNDu3Rbbyu93aPwRjaMYG3m0NkHMQamtnmZNSN9HX3Gq7huikqk8REAn8U3/X3 15Xw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jLFQ07Sy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id e18-20020a656492000000b006089cf2cde5sm294401pgv.26.2024.05.01.22.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 22:44:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, iii@linux.ibm.com, david@redhat.com, thuth@redhat.com Subject: [PATCH 14/14] tests/tcg/s390x: Add per.S Date: Wed, 1 May 2024 22:44:17 -0700 Message-Id: <20240502054417.234340-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240502054417.234340-1-richard.henderson@linaro.org> References: <20240502054417.234340-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a small test to avoid regressions. Signed-off-by: Richard Henderson Acked-by: Ilya Leoshkevich Tested-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.softmmu-target | 1 + tests/tcg/s390x/per.S | 82 +++++++++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 tests/tcg/s390x/per.S diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target index 1a1f088b28..80159cccf5 100644 --- a/tests/tcg/s390x/Makefile.softmmu-target +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -25,6 +25,7 @@ ASM_TESTS = \ lpswe-early \ lra \ mc \ + per \ precise-smc-softmmu \ ssm-early \ stosm-early \ diff --git a/tests/tcg/s390x/per.S b/tests/tcg/s390x/per.S new file mode 100644 index 0000000000..79e704a6ff --- /dev/null +++ b/tests/tcg/s390x/per.S @@ -0,0 +1,82 @@ + .org 0x8d +ilc: + .org 0x8e +program_interruption_code: + .org 0x96 +per_code: + .org 0x98 +per_address: + .org 0x150 +program_old_psw: + .org 0x1d0 +program_new_psw: + .quad 0, pgm_handler + + .org 0x200 /* exit lowcore */ + +per_on_psw: + .quad 0x4000000000000000, start_per +per_on_regs: + .quad 0x80000000, 0, -1 /* successful-branching everywhere */ +per_off_regs: + .quad 0, 0 ,0 +success_psw: + .quad 0x2000000000000, 0xfff /* see is_special_wait_psw() */ +failure_psw: + .quad 0x2000000000000, 0 /* disabled wait */ + + .org 0x2000 /* exit lowcore pages */ + + .globl _start +_start: + lpswe per_on_psw +start_per: + lctlg %c9, %c11, per_on_regs + +/* Test unconditional relative branch. */ + larl %r0, j1 + larl %r1, d1 + lhi %r2, 0 +j1: j d1 + lpswe failure_psw +d1: + +/* Test unconditional indirect branch. */ + larl %r0, j2 + larl %r1, d2 +j2: br %r1 + lpswe failure_psw +d2: + +/* Test conditional relative branch. */ + larl %r0, j3 + larl %r1, d3 + clr %r1, %r2 /* d3 != 0 */ +j3: jne d3 + lpswe failure_psw +d3: + +/* Test conditional register branch. */ + larl %r0, j4 + larl %r1, d4 + clr %r1, %r2 /* d4 != 0 */ +j4: bner %r1 + lpswe failure_psw +d4: + +/* Success! */ + nop + lpswe success_psw + +pgm_handler: + chhsi program_interruption_code, 0x80 /* PER event? */ + jne fail + cli per_code, 0x80 /* successful-branching event? */ + jne fail + clg %r0, per_address /* per_address == jump insn? */ + jne fail + clg %r1, program_old_psw+8 /* psw.addr updated to dest? */ + jne fail + lpswe program_old_psw +fail: + lpswe failure_psw