From patchwork Fri May 3 11:14:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Soo X-Patchwork-Id: 794483 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2138.outbound.protection.partner.outlook.cn [139.219.17.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6E0F139CE0; Fri, 3 May 2024 12:48:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.17.138 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714740535; cv=fail; b=oy8thwR2lbiecT5+TnU2rK7Y7VkQncCPScGOQgFPmmfHwEvV/a7zxnoQSTA3LjzhRzILHekJI+jcRHgWUfBKWXSWZ4RrH0LzxpAGrO3OA2HtF67lieeBfvwNk6ClZ1ykmaEcYRg/CICP3D7u2z+kyyJ4UfnZPtL+sDYGQQp5TGE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714740535; c=relaxed/simple; bh=RVvTspYhIcN86g2PKVAdE++YimNgJ1InhEo0JKgf/0s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=glQaTdTYSSl3KjtJ4DOQ7NkRNsWd38ZkRXzYBgDwPnkOzCNQ//sfH9SE8j82SNgQNzB6OInn7tEdodlFG2MgVGrWnQRXf4/Z8oxJp9CY4L2wd5k/VjobyWX0XUjK3TzZw+h+iIOnxRFLWlfztWvr5s7k/qhnBqaYU4sxignHReQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.17.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TaMA5oLHEn8AUhqn6l8zgjHPvL4HEWDbOMh5qKICfKhusMbCxGLFAEBczGXWLkg3GJZw5SF6W/g85m7KBnFHy6ffxF8uvDOw2hRtVACfRqQxnD211GOQuTUSfOjIjuesdOH7XkZCrT16lFRKZMrz3r8tPOOHtuvqBfSfJVIdwNEcl1Li2TiYkfnmJmUJLG1FpT54dUC97UdgI4Q7lkEWiMg2ccx7/xjRmae5I5WuwUXEFmIM1YPxayWmyj2bzuYSDfJFSUp6GuBCyRKUvHoVpNTtityRRCQPOv3+v6YCfZB17Tu5G3DMxODiECbcx1KQesd3FouCghxpTg5F1kb+JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vDdCVsDCb/VueupHtMM8rDUA+vzCW0UtHbAaJOIf6VY=; b=QKS2v848HrJRAXM6Fm4nrfG1lQo6/4ptYCzITUfQMGoDw3+G+x90oti8K9p/K6ezldCI9E4mLQe1cj4sXRXCrdkMTQlAtOuWkWFbGIaMsCU+Ke4ARC+6xdB2/NatxRl6c8+N3NU0J6/uoqtWPx8XDaci5nPSzS5AG7w3DkEffyW+HzpBGiFu8vWcIoerLO+sITjmYn3SwiT29TGNNkXHxPHX4OG3JC+cV3YpSkbAPzKoWVYS/NE4sNKI5fy9jCH8fPTaMyUX3tinFAhxZaMN03AAipf6Y3VhQSgEVX+dbdMlEI0LNgKbKsIMlUaxbLjcbW0w1UOmamrzYBmQaSbNgw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1238.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:14:53 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:14:53 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 2/7] pinctrl: starfive: jh8100: add main driver and sys_east domain sub-driver Date: Fri, 3 May 2024 19:14:31 +0800 Message-Id: <20240503111436.113089-3-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1238:EE_ X-MS-Office365-Filtering-Correlation-Id: aec45f71-2f6e-47c9-e0e7-08dc6b624166 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lgFP9C2Znwsl25f2b7eY18mYHoT5G/TB8r/u8ixqFZpqHEfQ11fAG0W31sL+E6Y22EsctfJmlcCqHIcbWqqjpfMryo/6X/jLsHFD0NzKvNI/Roue5Z307IwjHEvq8C984vWLkN0r3QNgAGZGKmaFgrlWm1YEKZs46cwhibKzR1w/63Ba6dbkpOtBIN1UrlpfHy9awSeQW/kL1iYeDNsq6UCBPo+e+4zXdnnC00Nq5bCH3kUDAvVINEyoOczEU6TRwvtDDeQBpBUZxWw0DSzExpdQ5lnRVnrHaWOkdp854q32ujwQPtJTEYkqQmCDzEy1cMKbVuzR2yq3sH6Psm8fKDOqpBPEJOpTkf1hjdBwEv6UuCd6CCK7sO4pQgWrIovFZo6e/CbYHY6W27scm2YUv5LAot4B+0onbHNUXz4nc+IpM/lv5GBF5uuStLVMLe/hvi5skx93FIPkdF++7lWfLxmub8YFH5MhVfp/6pplXoMHkSf8RCXzfl+WzqESdf1Ngc7SMWeKqLqSsVjSjEz1eP1EvkoOdud6RZIhsqEMvFG6DrRH6lTuVexbEN4n1VhCwCsPLGdlT64ZwCrp/FF3sC173RPM5ByjyJnNlm0Lzg2dIr38khIYHPZbqNpNFGnv+y/dO1sFyFAujc3pEU0MsQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(52116005)(41320700004)(7416005)(366007)(1800799015)(38350700005)(921011); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4S9Zby6l9uw05im4PUnOkZ8iBGN7rY3SaWlQjFJl1BFw6ZpCoLoCKy8XOhoAj+tX3r0youbR+J/ZTz60+m7fbZ/2Mb+M7jDvneLWjxyv9eZRvKZ3fsxv8ncjBn9rmBPb9biUiD44LbHQ9fdWmvNir7YNqPTFTl0TCmYEQgtfb9Xe7FYcsmEdWLI7ZkGfs6ndE5xpKxv1i1+KuBQy3Pl89n5Wg6UAY6e2EGuTG3oJZMXylBKWb/63capXcW85taX2itvWjHT02eysinsLxTqOlTNzjwbiQqcHoOXaw+D+ShqJOz9gMF27Zqms92ZEyt9l3WGcAUiOYQJjfPsjvFUjl+rOFCVppLxgE6ODrpyNvqtJj86CPP4sgQvHHyLpADsWoYhxxV5uLBqt3MEY4+T+OaNEpVb7kg5XfrjAjVTawaAGBWftLWeZ3AhdrNcpTHcNg21ma61nk7wr7MZjUFzwR7aSBpDt88PCvm/OVxUxNciPaCGvdiOXvPLaFlU5TSpQ2K1q0vppE04+6Fze4nCdYYTVKBdPeZGOSip/TFw/RO8iGzDnhch6dWcfhC0TWEryKCYdTXbYrYkZYZM3puTac+QRh7HJhIc8t0QAOKKj1CJ3uIIn8xtaVbXqFq1UanG+w0yUerLRin2LCmbT5qDIj0ApMzMQ/ZxI2/Dy/zoTnjPipaiHQMkA4SXdoIwsNXORh7atduDf8p3M3ePFxSBjFt+xbdIFDx3pNBwgF/yluNRxkaEmNoSjB0Cx1J7CvK7SnT2q4U8el0FI5VbJoRdO4QplCrliuG7mG7C+8eQWcmfsABL0NaJkW0sZ15mPJtdpju17fv/rwUwTWaTo5BApyBmW6BFkg5WaqOoxl7t1MD8GTjpkJ5ZC+MzMJXm8SOOsb/03M+L2YC/CYMcBgM2vDr5/kB1Yhqpk5HW4nNQhVVp8OO1UNc4WHqMszKUEQT2uz6C9178iz5DVJH1u/WC9L2R8OoCsUj7sFa4+2ZTVk/n0gG4Mxn7DY5BzmvoOdCgsiTdoymKwMc5Q34h0oVV5YVWgogyP3sVO6Tzd8IsIgvLDSQ3z8P50giNrD96wiNSWLpFC4ZFcHnDQDyS1lU0+s6r7l8Aq2seZeLSb2dRDQN4+KROH68G99FRAyE6iDoJR/bxLCsqcTEfLjrFfs53HqGFfz17TB018cKARjClNX+nluIa4AwbENiBAAEbVk4hlqPUxWs6uL0M9iMmhoLoh4SQjWCKr5gXePhXLPLe6EcTnPrQbMXhP+5s/XRqVUfNV971WAhMHvnHoOfGQaIq9R2lqihTQcX/3kZBgucwAJmNjEdcrGRHlmldIjpeh/PiuOgh5S48whjuSqTdF6LF+3O+4w532MZOts5CTj36E+k2f63ggF3xRQ4jh280r5ThSZyGJoU9+uLCkOzh5AWKR7vjCh9UhQBVw6CpTi2y1nRGFrQSOfP3DJLiQCYJJ8sHpSh7YyUWKfPY4uVpcNTTcljoddUXqNimioWbmpBKvbBSDjWDpgAVYuHhvKKX9UqyEHRxNIjRpdX7pOznZb7gFqJSlRvYRYEOu8TsOo+nPX6vpzyLZs7uleIajnPPqDcAQwNqQ6KLedUGY8E1oOECIFA== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: aec45f71-2f6e-47c9-e0e7-08dc6b624166 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:14:52.9978 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Sf1WVLkKkXrhic+QPIm0xKjcIrXiN7yZ7Vuwne0FB8F2qfueqAgkTSUbCCAlOGBxDZJHwXi1jq6A5ZSVmBKyaMuENimHPRiRTo+7ra+uOhU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1238 Add Starfive JH8100 SoC pinctrl main driver to provide the common APIs that are used by the sub-drivers of pinctrl domains: - sys_east, - sys_west, - sys_gmac, - aon (always-on) to implement the following tasks: - applies pin multiplexing, function selection, and pin configuration for devices during system initialization or change of pinctrl state due to power management. - read or set pin configuration from user space. Also, add the sys_east domain sub-driver since it requires at least one domain sub-driver to run the probe function in the main driver to enable the basic pinctrl functionalities on the system. Signed-off-by: Alex Soo --- drivers/pinctrl/starfive/Kconfig | 21 + drivers/pinctrl/starfive/Makefile | 3 + .../pinctrl-starfive-jh8100-sys-east.c | 220 ++++ .../starfive/pinctrl-starfive-jh8100.c | 1094 +++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.h | 111 ++ 5 files changed, 1449 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-east.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index 8192ac2087fc..afcbf9d4dc8d 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -49,3 +49,24 @@ config PINCTRL_STARFIVE_JH7110_AON This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH8100 + bool + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIOLIB_IRQCHIP + select OF_GPIO + +config PINCTRL_STARFIVE_JH8100_SYS_EAST + tristate "StarFive JH8100 SoC System IOMUX-East pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support system iomux-east pin control on the StarFive JH8100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index ee0d32d085cb..45698c502b48 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -5,3 +5,6 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o + +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-east.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-east.c new file mode 100644 index 000000000000..45ade4d68d66 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-east.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC sys east controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_SYS_E_GC_BASE 16 + +/* registers */ +#define JH8100_SYS_E_DOEN 0x000 +#define JH8100_SYS_E_DOUT 0x030 +#define JH8100_SYS_E_GPI 0x060 +#define JH8100_SYS_E_GPIOIN 0x0f4 + +#define JH8100_SYS_E_GPIOEN 0x0b8 +#define JH8100_SYS_E_GPIOIS0 0x0bc +#define JH8100_SYS_E_GPIOIS1 0x0c0 +#define JH8100_SYS_E_GPIOIC0 0x0c4 +#define JH8100_SYS_E_GPIOIC1 0x0c8 +#define JH8100_SYS_E_GPIOIBE0 0x0cc +#define JH8100_SYS_E_GPIOIBE1 0x0d0 +#define JH8100_SYS_E_GPIOIEV0 0x0d4 +#define JH8100_SYS_E_GPIOIEV1 0x0d8 +#define JH8100_SYS_E_GPIOIE0 0x0dc +#define JH8100_SYS_E_GPIOIE1 0x0e0 +#define JH8100_SYS_E_GPIORIS0 0x0e4 +#define JH8100_SYS_E_GPIORIS1 0x0e8 +#define JH8100_SYS_E_GPIOMIS0 0x0ec +#define JH8100_SYS_E_GPIOMIS1 0x0f0 + +static const struct pinctrl_pin_desc jh8100_sys_e_pins[] = { + PINCTRL_PIN(0, "SYS_E_GPIO0"), + PINCTRL_PIN(1, "SYS_E_GPIO1"), + PINCTRL_PIN(2, "SYS_E_GPIO2"), + PINCTRL_PIN(3, "SYS_E_GPIO3"), + PINCTRL_PIN(4, "SYS_E_GPIO4"), + PINCTRL_PIN(5, "SYS_E_GPIO5"), + PINCTRL_PIN(6, "SYS_E_GPIO6"), + PINCTRL_PIN(7, "SYS_E_GPIO7"), + PINCTRL_PIN(8, "SYS_E_GPIO8"), + PINCTRL_PIN(9, "SYS_E_GPIO9"), + PINCTRL_PIN(10, "SYS_E_GPIO10"), + PINCTRL_PIN(11, "SYS_E_GPIO11"), + PINCTRL_PIN(12, "SYS_E_GPIO12"), + PINCTRL_PIN(13, "SYS_E_GPIO13"), + PINCTRL_PIN(14, "SYS_E_GPIO14"), + PINCTRL_PIN(15, "SYS_E_GPIO15"), + PINCTRL_PIN(16, "SYS_E_GPIO16"), + PINCTRL_PIN(17, "SYS_E_GPIO17"), + PINCTRL_PIN(18, "SYS_E_GPIO18"), + PINCTRL_PIN(19, "SYS_E_GPIO19"), + PINCTRL_PIN(20, "SYS_E_GPIO20"), + PINCTRL_PIN(21, "SYS_E_GPIO21"), + PINCTRL_PIN(22, "SYS_E_GPIO22"), + PINCTRL_PIN(23, "SYS_E_GPIO23"), + PINCTRL_PIN(24, "SYS_E_GPIO24"), + PINCTRL_PIN(25, "SYS_E_GPIO25"), + PINCTRL_PIN(26, "SYS_E_GPIO26"), + PINCTRL_PIN(27, "SYS_E_GPIO27"), + PINCTRL_PIN(28, "SYS_E_GPIO28"), + PINCTRL_PIN(29, "SYS_E_GPIO29"), + PINCTRL_PIN(30, "SYS_E_GPIO30"), + PINCTRL_PIN(31, "SYS_E_GPIO31"), + PINCTRL_PIN(32, "SYS_E_GPIO32"), + PINCTRL_PIN(33, "SYS_E_GPIO33"), + PINCTRL_PIN(34, "SYS_E_GPIO34"), + PINCTRL_PIN(35, "SYS_E_GPIO35"), + PINCTRL_PIN(36, "SYS_E_GPIO36"), + PINCTRL_PIN(37, "SYS_E_GPIO37"), + PINCTRL_PIN(38, "SYS_E_GPIO38"), + PINCTRL_PIN(39, "SYS_E_GPIO39"), + PINCTRL_PIN(40, "SYS_E_GPIO40"), + PINCTRL_PIN(41, "SYS_E_GPIO41"), + PINCTRL_PIN(42, "SYS_E_GPIO42"), + PINCTRL_PIN(43, "SYS_E_GPIO43"), + PINCTRL_PIN(44, "SYS_E_GPIO44"), + PINCTRL_PIN(45, "SYS_E_GPIO45"), + PINCTRL_PIN(46, "SYS_E_GPIO46"), + PINCTRL_PIN(47, "SYS_E_GPIO47"), +}; + +static const struct jh8100_gpio_func_sel + jh8100_sys_e_func_sel[ARRAY_SIZE(jh8100_sys_e_pins)] = { + [20] = { 0x1d4, 0, 2 }, + [21] = { 0x1d4, 2, 2 }, + [22] = { 0x1d4, 4, 2 }, + [23] = { 0x1d4, 6, 2 }, + [24] = { 0x1d4, 8, 2 }, + [25] = { 0x1d4, 10, 2 }, + [26] = { 0x1d4, 12, 2 }, + [27] = { 0x1d4, 14, 2 }, + [28] = { 0x1d4, 16, 2 }, + [29] = { 0x1d4, 18, 2 }, + [30] = { 0x1d4, 20, 2 }, + [31] = { 0x1d4, 22, 2 }, + [32] = { 0x1d4, 24, 2 }, + [33] = { 0x1d4, 26, 2 }, + [34] = { 0x1d4, 28, 2 }, + [35] = { 0x1d4, 30, 2 }, + + [36] = { 0x1d8, 0, 2 }, + [37] = { 0x1d8, 2, 2 }, + [38] = { 0x1d8, 4, 2 }, + [39] = { 0x1d8, 6, 2 }, + [40] = { 0x1d8, 8, 2 }, + [41] = { 0x1d8, 10, 2 }, + [42] = { 0x1d8, 12, 2 }, + [43] = { 0x1d8, 14, 2 }, + [44] = { 0x1d8, 16, 2 }, + [45] = { 0x1d8, 18, 2 }, + [46] = { 0x1d8, 20, 2 }, + [47] = { 0x1d8, 22, 2 }, +}; + +#ifdef CONFIG_PM_SLEEP +static int jh8100_sys_e_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_sys_east_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_sys_e_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_sys_east_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_sys_e_pinctrl_dev_pm_ops, + jh8100_sys_e_pinctrl_suspend, + jh8100_sys_e_pinctrl_resume); + +static const struct jh8100_gpio_irq_reg jh8100_sys_e_irq_reg = { + .is_reg_base = JH8100_SYS_E_GPIOIS0, + .ic_reg_base = JH8100_SYS_E_GPIOIC0, + .ic1_reg_base = JH8100_SYS_E_GPIOIC1, + .ibe_reg_base = JH8100_SYS_E_GPIOIBE0, + .iev_reg_base = JH8100_SYS_E_GPIOIEV0, + .ie_reg_base = JH8100_SYS_E_GPIOIE0, + .ris_reg_base = JH8100_SYS_E_GPIORIS0, + .mis_reg_base = JH8100_SYS_E_GPIOMIS0, + .mis1_reg_base = JH8100_SYS_E_GPIOMIS1, + .ien_reg_base = JH8100_SYS_E_GPIOEN, +}; + +static const struct jh8100_pinctrl_domain_info jh8100_sys_e_pinctrl_info = { + .pins = jh8100_sys_e_pins, + .npins = ARRAY_SIZE(jh8100_sys_e_pins), + .ngpios = JH8100_SYS_E_NGPIO, + .gc_base = JH8100_SYS_E_GC_BASE, + .name = JH8100_SYS_E_DOMAIN_NAME, + .nregs = JH8100_SYS_E_REG_NUM, + .dout_reg_base = JH8100_SYS_E_DOUT, + .dout_mask = GENMASK(6, 0), + .doen_reg_base = JH8100_SYS_E_DOEN, + .doen_mask = GENMASK(5, 0), + .gpi_reg_base = JH8100_SYS_E_GPI, + .gpi_mask = GENMASK(5, 0), + .gpioin_reg_base = JH8100_SYS_E_GPIOIN, + .func_sel = jh8100_sys_e_func_sel, + .irq_reg = &jh8100_sys_e_irq_reg, + .mis_pin_num = 32, + .mis1_pin_num = 16, +}; + +static const struct of_device_id jh8100_sys_e_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-sys-pinctrl-east", + .data = &jh8100_sys_e_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_sys_e_pinctrl_of_match); + +static struct platform_driver jh8100_sys_e_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-sys-pinctrl-east", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_sys_e_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_sys_e_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_sys_e_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC sys east controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c new file mode 100644 index 000000000000..4b68463ff5a5 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c @@ -0,0 +1,1094 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +/* pad control bits */ +#define JH8100_PADCFG_POS BIT(7) +#define JH8100_PADCFG_SMT BIT(6) +#define JH8100_PADCFG_SLEW BIT(5) +#define JH8100_PADCFG_PD BIT(4) +#define JH8100_PADCFG_PU BIT(3) +#define JH8100_PADCFG_BIAS_MASK (JH8100_PADCFG_PD | JH8100_PADCFG_PU) +#define JH8100_PADCFG_DS_MASK GENMASK(2, 1) +#define JH8100_PADCFG_DS_2MA (0U << 1) +#define JH8100_PADCFG_DS_4MA (1U << 1) +#define JH8100_PADCFG_DS_8MA (2U << 1) +#define JH8100_PADCFG_DS_12MA (3U << 1) +#define JH8100_PADCFG_IE BIT(0) + +/* + * The packed pinmux values from the device tree look like this: + * + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | pin | + */ +static unsigned int jh8100_pinmux_din(u32 v) +{ + return (v & GENMASK(31, 24)) >> 24; +} + +static u32 jh8100_pinmux_dout(u32 v) +{ + return (v & GENMASK(23, 16)) >> 16; +} + +static u32 jh8100_pinmux_doen(u32 v) +{ + return (v & GENMASK(15, 10)) >> 10; +} + +static u32 jh8100_pinmux_function(u32 v) +{ + return (v & GENMASK(9, 8)) >> 8; +} + +static unsigned int jh8100_pinmux_pin(u32 v) +{ + return v & GENMASK(7, 0); +} + +static struct jh8100_pinctrl *jh8100_from_irq_data(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + return container_of(gc, struct jh8100_pinctrl, gc); +} + +struct jh8100_pinctrl *jh8100_from_irq_desc(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + + return container_of(gc, struct jh8100_pinctrl, gc); +} +EXPORT_SYMBOL_GPL(jh8100_from_irq_desc); + +#ifdef CONFIG_DEBUG_FS +static void jh8100_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct jh8100_pinctrl_domain_info *info = sfp->info; + + seq_printf(s, "%s", dev_name(pctldev->dev)); + + if (pin < sfp->gc.ngpio) { + unsigned int offset = 4 * (pin / 4); + unsigned int shift = 8 * (pin % 4); + u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); + u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset); + + dout = (dout >> shift) & info->dout_mask; + doen = (doen >> shift) & info->doen_mask; + gpi = ((gpi >> shift) - 2) & info->gpi_mask; + + seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi); + } +} +#else +#define jh8100_pin_dbg_show NULL +#endif + +static int jh8100_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **maps, + unsigned int *num_maps) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + struct device *dev = sfp->gc.parent; + struct device_node *child; + struct pinctrl_map *map; + const char **pgnames; + const char *grpname; + int ngroups; + int nmaps; + int ret; + + ngroups = 0; + for_each_child_of_node(np, child) + ngroups += 1; + nmaps = 2 * ngroups; + + pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL); + if (!pgnames) + return -ENOMEM; + + map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); + if (!map) + return -ENOMEM; + + nmaps = 0; + ngroups = 0; + mutex_lock(&sfp->mutex); + for_each_child_of_node(np, child) { + int npins = of_property_count_u32_elems(child, "pinmux"); + int *pins; + u32 *pinmux; + int i; + + if (npins < 1) { + dev_err(dev, + "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n", + np, child); + ret = -EINVAL; + goto put_child; + } + + grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child); + if (!grpname) { + ret = -ENOMEM; + goto put_child; + } + + pgnames[ngroups++] = grpname; + + pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) { + ret = -ENOMEM; + goto put_child; + } + + pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL); + if (!pinmux) { + ret = -ENOMEM; + goto put_child; + } + + ret = of_property_read_u32_array(child, "pinmux", pinmux, npins); + if (ret) + goto put_child; + + for (i = 0; i < npins; i++) + pins[i] = jh8100_pinmux_pin(pinmux[i]); + + map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; + map[nmaps].data.mux.function = np->name; + map[nmaps].data.mux.group = grpname; + nmaps += 1; + + ret = pinctrl_generic_add_group(pctldev, grpname, + pins, npins, pinmux); + if (ret < 0) { + dev_err(dev, "error adding group %s: %d\n", grpname, ret); + goto put_child; + } + + ret = pinconf_generic_parse_dt_config(child, pctldev, + &map[nmaps].data.configs.configs, + &map[nmaps].data.configs.num_configs); + if (ret) { + dev_err(dev, "error parsing pin config of group %s: %d\n", + grpname, ret); + goto put_child; + } + + /* don't create a map if there are no pinconf settings */ + if (map[nmaps].data.configs.num_configs == 0) + continue; + + map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; + map[nmaps].data.configs.group_or_pin = grpname; + nmaps += 1; + } + + ret = pinmux_generic_add_function(pctldev, np->name, + pgnames, ngroups, NULL); + if (ret < 0) { + dev_err(dev, "error adding function %s: %d\n", np->name, ret); + goto free_map; + } + mutex_unlock(&sfp->mutex); + + *maps = map; + *num_maps = nmaps; + return 0; + +put_child: + of_node_put(child); +free_map: + pinctrl_utils_free_map(pctldev, map, nmaps); + mutex_unlock(&sfp->mutex); + return ret; +} + +static const struct pinctrl_ops jh8100_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .pin_dbg_show = jh8100_pin_dbg_show, + .dt_node_to_map = jh8100_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +void jh8100_set_gpiomux(struct jh8100_pinctrl *sfp, unsigned int pin, + unsigned int din, u32 dout, u32 doen) +{ + const struct jh8100_pinctrl_domain_info *info = sfp->info; + + unsigned int offset = 4 * (pin / 4); + unsigned int shift = 8 * (pin % 4); + u32 dout_mask = info->dout_mask << shift; + u32 done_mask = info->doen_mask << shift; + u32 ival, imask; + u32 tmp; + void __iomem *reg_dout; + void __iomem *reg_doen; + void __iomem *reg_din; + unsigned long flags; + + reg_dout = sfp->base + info->dout_reg_base + offset; + reg_doen = sfp->base + info->doen_reg_base + offset; + dout <<= shift; + doen <<= shift; + if (din != 255) { + unsigned int ioffset = 4 * (din / 4); + unsigned int ishift = 8 * (din % 4); + + reg_din = sfp->base + info->gpi_reg_base + ioffset; + ival = (pin + 2) << ishift; + imask = info->gpi_mask << ishift; + } else { + reg_din = NULL; + } + + raw_spin_lock_irqsave(&sfp->lock, flags); + dout |= readl_relaxed(reg_dout) & ~dout_mask; + writel_relaxed(dout, reg_dout); + doen |= readl_relaxed(reg_doen) & ~done_mask; + writel_relaxed(doen, reg_doen); + if (reg_din) { + tmp = readl_relaxed(reg_din) & ~imask; + writel_relaxed(tmp, reg_din); + ival |= readl_relaxed(reg_din) & ~imask; + writel_relaxed(ival, reg_din); + } + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh8100_set_function(struct jh8100_pinctrl *sfp, + unsigned int pin, u32 func) +{ + const struct jh8100_gpio_func_sel *fs = &sfp->info->func_sel[pin]; + unsigned long flags; + void __iomem *reg; + u32 mask; + + if (!fs->offset) + return; + + if (func > fs->max) + return; + + reg = sfp->base + fs->offset; + func = func << fs->shift; + mask = 0x3U << fs->shift; + + raw_spin_lock_irqsave(&sfp->lock, flags); + func |= readl_relaxed(reg) & ~mask; + writel_relaxed(func, reg); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh8100_set_one_pin_mux(struct jh8100_pinctrl *sfp, + unsigned int pin, + unsigned int din, u32 dout, + u32 doen, u32 func) +{ + if (pin < sfp->gc.ngpio && func == 0) + jh8100_set_gpiomux(sfp, pin, din, dout, doen); + + if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME) && + pin < sfp->gc.ngpio && func == 1) + jh8100_set_function(sfp, pin, func); + + return 0; +} + +static int jh8100_set_mux(struct pinctrl_dev *pctldev, + unsigned int fsel, unsigned int gsel) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + const u32 *pinmux; + unsigned int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + pinmux = group->data; + + for (i = 0; i < group->grp.npins; i++) { + u32 v = pinmux[i]; + + jh8100_set_one_pin_mux(sfp, + jh8100_pinmux_pin(v), + jh8100_pinmux_din(v), + jh8100_pinmux_dout(v), + jh8100_pinmux_doen(v), + jh8100_pinmux_function(v)); + } + + return 0; +} + +static const struct pinmux_ops jh8100_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = jh8100_set_mux, + .strict = true, +}; + +static const u8 jh8100_drive_strength_mA[4] = { 2, 4, 8, 12 }; + +static u32 jh8100_padcfg_ds_to_mA(u32 padcfg) +{ + return jh8100_drive_strength_mA[(padcfg >> 1) & 3U]; +} + +static u32 jh8100_padcfg_ds_to_uA(u32 padcfg) +{ + return jh8100_drive_strength_mA[(padcfg >> 1) & 3U] * 1000; +} + +static u32 jh8100_padcfg_ds_from_mA(u32 v) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(jh8100_drive_strength_mA); i++) { + if (v <= jh8100_drive_strength_mA[i]) + break; + } + return i << 1; +} + +static u32 jh8100_padcfg_ds_from_uA(u32 v) +{ + /* Convert from uA to mA */ + v /= 1000; + + return jh8100_padcfg_ds_from_mA(v); +} + +static int jh8100_get_padcfg_base(struct jh8100_pinctrl *sfp, + unsigned int pin) +{ + if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME)) { + if (pin < JH8100_SYS_E_NGPIO) + return JH8100_SYS_E_GPO_PDA_00_47_CFG; + } + + return -ENXIO; +} + +static void jh8100_padcfg_rmw(struct jh8100_pinctrl *sfp, + unsigned int pin, u32 mask, u32 value) +{ + void __iomem *reg; + unsigned long flags; + int padcfg_base; + + padcfg_base = jh8100_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return; + + reg = sfp->base + padcfg_base + 4 * pin; + value &= mask; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value |= readl_relaxed(reg) & ~mask; + writel_relaxed(value, reg); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh8100_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + int param = pinconf_to_config_param(*config); + u32 padcfg, arg; + bool enabled; + int padcfg_base; + + padcfg_base = jh8100_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return 0; + + padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + enabled = !(padcfg & JH8100_PADCFG_BIAS_MASK); + arg = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + enabled = padcfg & JH8100_PADCFG_PD; + arg = 1; + break; + case PIN_CONFIG_BIAS_PULL_UP: + enabled = padcfg & JH8100_PADCFG_PU; + arg = 1; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + enabled = true; + arg = jh8100_padcfg_ds_to_mA(padcfg); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + enabled = true; + arg = jh8100_padcfg_ds_to_uA(padcfg); + break; + case PIN_CONFIG_INPUT_ENABLE: + enabled = padcfg & JH8100_PADCFG_IE; + arg = enabled; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + enabled = padcfg & JH8100_PADCFG_SMT; + arg = enabled; + break; + case PIN_CONFIG_SLEW_RATE: + enabled = true; + arg = !!(padcfg & JH8100_PADCFG_SLEW); + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return enabled ? 0 : -EINVAL; +} + +static int jh8100_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int gpio, unsigned long *config, + unsigned int num_configs) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + u32 param; + u32 arg; + u32 value; + u32 mask; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(config[i]); + arg = pinconf_to_config_argument(config[i]); + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask = JH8100_PADCFG_BIAS_MASK; + value = 0; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask = JH8100_PADCFG_BIAS_MASK; + value = JH8100_PADCFG_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask = JH8100_PADCFG_BIAS_MASK; + value = JH8100_PADCFG_PU; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + return 0; + case PIN_CONFIG_INPUT_ENABLE: + mask = JH8100_PADCFG_IE; + value = arg ? JH8100_PADCFG_IE : 0; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask = JH8100_PADCFG_SMT; + value = arg ? JH8100_PADCFG_SMT : 0; + break; + default: + return -ENOTSUPP; + } + + jh8100_padcfg_rmw(sfp, gpio, mask, value); + } + + return 0; +} + +static int jh8100_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *config) +{ + const struct group_desc *group; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + return jh8100_pinconf_get(pctldev, group->grp.pins[0], config); +} + +static int jh8100_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int gsel, + unsigned long *configs, + unsigned int num_configs) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + const struct group_desc *group; + u16 mask, value; + int i; + + group = pinctrl_generic_get_group(pctldev, gsel); + if (!group) + return -EINVAL; + + mask = 0; + value = 0; + for (i = 0; i < num_configs; i++) { + int param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |= JH8100_PADCFG_BIAS_MASK; + value &= ~JH8100_PADCFG_BIAS_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + if (arg == 0) + return -ENOTSUPP; + mask |= JH8100_PADCFG_BIAS_MASK; + value = (value & ~JH8100_PADCFG_BIAS_MASK) | JH8100_PADCFG_PD; + break; + case PIN_CONFIG_BIAS_PULL_UP: + if (arg == 0) + return -ENOTSUPP; + mask |= JH8100_PADCFG_BIAS_MASK; + value = (value & ~JH8100_PADCFG_BIAS_MASK) | JH8100_PADCFG_PU; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + mask |= JH8100_PADCFG_DS_MASK; + value = (value & ~JH8100_PADCFG_DS_MASK) | + jh8100_padcfg_ds_from_mA(arg); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + mask |= JH8100_PADCFG_DS_MASK; + value = (value & ~JH8100_PADCFG_DS_MASK) | + jh8100_padcfg_ds_from_uA(arg); + break; + case PIN_CONFIG_INPUT_ENABLE: + mask |= JH8100_PADCFG_IE; + if (arg) + value |= JH8100_PADCFG_IE; + else + value &= ~JH8100_PADCFG_IE; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + mask |= JH8100_PADCFG_SMT; + if (arg) + value |= JH8100_PADCFG_SMT; + else + value &= ~JH8100_PADCFG_SMT; + break; + case PIN_CONFIG_SLEW_RATE: + mask |= JH8100_PADCFG_SLEW; + if (arg) + value |= JH8100_PADCFG_SLEW; + else + value &= ~JH8100_PADCFG_SLEW; + break; + default: + return -ENOTSUPP; + } + } + + for (i = 0; i < group->grp.npins; i++) + jh8100_padcfg_rmw(sfp, group->grp.pins[i], mask, value); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void jh8100_pinconf_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, unsigned int pin) +{ + struct jh8100_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev); + u32 value; + int padcfg_base; + + padcfg_base = jh8100_get_padcfg_base(sfp, pin); + if (padcfg_base < 0) + return; + + value = readl_relaxed(sfp->base + padcfg_base + 4 * pin); + seq_printf(s, " (0x%02x)", value); +} +#else +#define jh8100_pinconf_dbg_show NULL +#endif + +static const struct pinconf_ops jh8100_pinconf_ops = { + .pin_config_get = jh8100_pinconf_get, + .pin_config_set = jh8100_pinconf_set, + .pin_config_group_get = jh8100_pinconf_group_get, + .pin_config_group_set = jh8100_pinconf_group_set, + .pin_config_dbg_show = jh8100_pinconf_dbg_show, + .is_generic = true, +}; + +static int jh8100_gpio_get_direction(struct gpio_chip *gc, + unsigned int gpio) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + const struct jh8100_pinctrl_domain_info *info = sfp->info; + unsigned int offset = 4 * (gpio / 4); + unsigned int shift = 8 * (gpio % 4); + u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); + + doen = (doen >> shift) & info->doen_mask; + + return doen == 0 ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + +static int jh8100_gpio_direction_input(struct gpio_chip *gc, + unsigned int gpio) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + + /* enable input and schmitt trigger */ + jh8100_padcfg_rmw(sfp, gpio, + JH8100_PADCFG_IE | JH8100_PADCFG_SMT, + JH8100_PADCFG_IE | JH8100_PADCFG_SMT); + + jh8100_set_one_pin_mux(sfp, gpio, 255, 0, 1, 0); + + return 0; +} + +static int jh8100_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + + jh8100_set_one_pin_mux(sfp, gpio, + 255, value ? 1 : 0, + 0, 0); + + /* disable input, schmitt trigger and bias */ + jh8100_padcfg_rmw(sfp, gpio, + JH8100_PADCFG_IE | JH8100_PADCFG_SMT, + 0); + return 0; +} + +static int jh8100_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + const struct jh8100_pinctrl_domain_info *info = sfp->info; + void __iomem *reg = sfp->base + info->gpioin_reg_base + + 4 * (gpio / 32); + + return !!(readl_relaxed(reg) & BIT(gpio % 32)); +} + +static void jh8100_gpio_set(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + const struct jh8100_pinctrl_domain_info *info = sfp->info; + unsigned int offset = 4 * (gpio / 4); + unsigned int shift = 8 * (gpio % 4); + void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset; + u32 dout = (value ? 1 : 0) << shift; + u32 mask = info->dout_mask << shift; + unsigned long flags; + + raw_spin_lock_irqsave(&sfp->lock, flags); + dout |= readl_relaxed(reg_dout) & ~mask; + writel_relaxed(dout, reg_dout); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh8100_irq_ack(struct irq_data *d) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ic = sfp->base + irq_reg->ic_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value, ic); + writel_relaxed(value | mask, ic); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh8100_irq_mask(struct irq_data *d) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) & ~mask; + writel_relaxed(value, ie); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + + gpiochip_disable_irq(&sfp->gc, d->hwirq); +} + +static void jh8100_irq_mask_ack(struct irq_data *d) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + void __iomem *ic = sfp->base + irq_reg->ic_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) & ~mask; + writel_relaxed(value, ie); + + value = readl_relaxed(ic) & ~mask; + writel_relaxed(value, ic); + writel_relaxed(value | mask, ic); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static void jh8100_irq_unmask(struct irq_data *d) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *ie = sfp->base + irq_reg->ie_reg_base + + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + unsigned long flags; + u32 value; + + gpiochip_enable_irq(&sfp->gc, d->hwirq); + + raw_spin_lock_irqsave(&sfp->lock, flags); + value = readl_relaxed(ie) | mask; + writel_relaxed(value, ie); + raw_spin_unlock_irqrestore(&sfp->lock, flags); +} + +static int jh8100_irq_set_type(struct irq_data *d, unsigned int trigger) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + const struct jh8100_gpio_irq_reg *irq_reg = sfp->info->irq_reg; + irq_hw_number_t gpio = irqd_to_hwirq(d); + void __iomem *base = sfp->base + 4 * (gpio / 32); + u32 mask = BIT(gpio % 32); + u32 irq_type, edge_both, polarity; + unsigned long flags; + + switch (trigger) { + case IRQ_TYPE_EDGE_RISING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = mask; /* 1: rising edge */ + break; + case IRQ_TYPE_EDGE_FALLING: + irq_type = mask; /* 1: edge triggered */ + edge_both = 0; /* 0: single edge */ + polarity = 0; /* 0: falling edge */ + break; + case IRQ_TYPE_EDGE_BOTH: + irq_type = mask; /* 1: edge triggered */ + edge_both = mask; /* 1: both edges */ + polarity = 0; /* 0: ignored */ + break; + case IRQ_TYPE_LEVEL_HIGH: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = mask; /* 1: high level */ + break; + case IRQ_TYPE_LEVEL_LOW: + irq_type = 0; /* 0: level triggered */ + edge_both = 0; /* 0: ignored */ + polarity = 0; /* 0: low level */ + break; + default: + return -EINVAL; + } + + if (trigger & IRQ_TYPE_EDGE_BOTH) + irq_set_handler_locked(d, handle_edge_irq); + else + irq_set_handler_locked(d, handle_level_irq); + + raw_spin_lock_irqsave(&sfp->lock, flags); + irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask; + writel_relaxed(irq_type, base + irq_reg->is_reg_base); + + edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask; + writel_relaxed(edge_both, base + irq_reg->ibe_reg_base); + + polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask; + writel_relaxed(polarity, base + irq_reg->iev_reg_base); + raw_spin_unlock_irqrestore(&sfp->lock, flags); + return 0; +} + +static int jh8100_irq_set_wake(struct irq_data *d, unsigned int enable) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + int ret = 0; + + if (enable) + ret = enable_irq_wake(sfp->wakeup_irq); + else + ret = disable_irq_wake(sfp->wakeup_irq); + if (ret) + dev_err(sfp->dev, "failed to %s wake-up interrupt\n", + enable ? "enable" : "disable"); + + return ret; +} + +static void jh8100_irq_print_chip(struct irq_data *d, struct seq_file *p) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_data(d); + + seq_printf(p, sfp->gc.label); +} + +static const struct irq_chip jh8100_irq_chip = { + .irq_ack = jh8100_irq_ack, + .irq_mask = jh8100_irq_mask, + .irq_mask_ack = jh8100_irq_mask_ack, + .irq_unmask = jh8100_irq_unmask, + .irq_set_type = jh8100_irq_set_type, + .irq_set_wake = jh8100_irq_set_wake, + .irq_print_chip = jh8100_irq_print_chip, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_IMMUTABLE | + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | + IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SKIP_SET_WAKE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void jh8100_gpio_irq_handler(struct irq_desc *desc) +{ + struct jh8100_pinctrl *sfp = jh8100_from_irq_desc(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct gpio_irq_chip *girq = &sfp->gc.irq; + unsigned long mis; + unsigned int pin; + + chained_irq_enter(chip, desc); + + mis = readl_relaxed(sfp->base + sfp->info->irq_reg->mis_reg_base); + for_each_set_bit(pin, &mis, sfp->info->mis_pin_num) + generic_handle_domain_irq(girq->domain, pin); + + if (sfp->info->irq_reg->mis1_reg_base) { + mis = readl_relaxed(sfp->base + sfp->info->irq_reg->mis1_reg_base); + for_each_set_bit(pin, &mis, sfp->info->mis1_pin_num) + generic_handle_domain_irq(girq->domain, pin + 32); + } + + chained_irq_exit(chip, desc); +} + +static int jh8100_gpio_init_hw(struct gpio_chip *gc) +{ + struct jh8100_pinctrl *sfp = container_of(gc, + struct jh8100_pinctrl, gc); + + /* mask all GPIO interrupts */ + writel_relaxed(0U, sfp->base + sfp->info->irq_reg->ie_reg_base); + /* clear edge interrupt flags */ + writel_relaxed(0U, sfp->base + sfp->info->irq_reg->ic_reg_base); + writel_relaxed(~0U, sfp->base + sfp->info->irq_reg->ic_reg_base); + if (sfp->info->irq_reg->ic1_reg_base) { + writel_relaxed(0U, sfp->base + sfp->info->irq_reg->ic1_reg_base); + writel_relaxed(~0U, sfp->base + sfp->info->irq_reg->ic1_reg_base); + } + /* enable GPIO interrupts */ + writel_relaxed(1, sfp->base + sfp->info->irq_reg->ien_reg_base); + + return 0; +} + +static void jh8100_disable_clock(void *data) +{ + clk_disable_unprepare(data); +} + +int jh8100_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gpio_irq_chip *girq; + const struct jh8100_pinctrl_domain_info *info; + struct jh8100_pinctrl *sfp; + struct pinctrl_desc *jh8100_pinctrl_desc; + struct reset_control *rst; + struct clk *clk; + int ret; + + info = of_device_get_match_data(&pdev->dev); + if (!info) + return -ENODEV; + + sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL); + if (!sfp) + return -ENOMEM; + + sfp->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sfp->base)) + return PTR_ERR(sfp->base); + + clk = devm_clk_get_optional(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n"); + + rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "could not get reset control\n"); + + ret = clk_prepare_enable(clk); + if (ret) + return dev_err_probe(dev, ret, "could not enable clock\n"); + + ret = devm_add_action_or_reset(dev, jh8100_disable_clock, clk); + if (ret) + return ret; + + /* + * we don't want to assert reset and risk undoing pin muxing for the + * early boot serial console, but let's make sure the reset line is + * deasserted in case someone runs a really minimal bootloader. + */ + ret = reset_control_deassert(rst); + if (ret) + return dev_err_probe(dev, ret, "could not deassert reset\n"); + + jh8100_pinctrl_desc = devm_kzalloc(&pdev->dev, + sizeof(*jh8100_pinctrl_desc), + GFP_KERNEL); + if (!jh8100_pinctrl_desc) + return -ENOMEM; + + jh8100_pinctrl_desc->name = dev_name(dev); + jh8100_pinctrl_desc->pins = info->pins; + jh8100_pinctrl_desc->npins = info->npins; + jh8100_pinctrl_desc->pctlops = &jh8100_pinctrl_ops; + jh8100_pinctrl_desc->pmxops = &jh8100_pinmux_ops; + jh8100_pinctrl_desc->confops = &jh8100_pinconf_ops; + jh8100_pinctrl_desc->owner = THIS_MODULE; + + sfp->info = info; + sfp->dev = dev; + platform_set_drvdata(pdev, sfp); + sfp->gc.parent = dev; + raw_spin_lock_init(&sfp->lock); + mutex_init(&sfp->mutex); + + ret = devm_pinctrl_register_and_init(dev, + jh8100_pinctrl_desc, + sfp, &sfp->pctl); + if (ret) + return dev_err_probe(dev, ret, + "could not register pinctrl driver\n"); + + sfp->gc.label = dev_name(dev); + sfp->gc.owner = THIS_MODULE; + sfp->gc.request = pinctrl_gpio_request; + sfp->gc.free = pinctrl_gpio_free; + sfp->gc.get_direction = jh8100_gpio_get_direction; + sfp->gc.direction_input = jh8100_gpio_direction_input; + sfp->gc.direction_output = jh8100_gpio_direction_output; + sfp->gc.get = jh8100_gpio_get; + sfp->gc.set = jh8100_gpio_set; + sfp->gc.set_config = gpiochip_generic_config; + sfp->gc.base = info->gc_base; + sfp->gc.ngpio = info->ngpios; + + girq = &sfp->gc.irq; + + if (info->irq_reg) { + gpio_irq_chip_set_chip(girq, &jh8100_irq_chip); + girq->parent_handler = jh8100_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, girq->num_parents, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->init_hw = jh8100_gpio_init_hw; + + ret = platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + girq->parents[0] = ret; + } + + ret = pinctrl_enable(sfp->pctl); + if (ret) + return ret; + + if (sfp->gc.ngpio > 0) { + ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp); + if (ret) + return dev_err_probe(dev, ret, "could not register gpiochip\n"); + + dev_info(dev, "StarFive JH8100 GPIO chip registered %d GPIOs\n", sfp->gc.ngpio); + } + + return 0; +} +EXPORT_SYMBOL_GPL(jh8100_pinctrl_probe); + +MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH8100 SoC"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h new file mode 100644 index 000000000000..6eb4f1896a90 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#ifndef __PINCTRL_STARFIVE_JH8100_H__ +#define __PINCTRL_STARFIVE_JH8100_H__ + +#include "../core.h" + +#define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" + +#define JH8100_SYS_E_NGPIO 48 + +#define JH8100_SYS_E_REG_NUM 116 + +#define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 + +struct jh8100_pinctrl { + struct device *dev; + struct gpio_chip gc; + struct pinctrl_gpio_range gpios; + raw_spinlock_t lock; + void __iomem *base; + struct pinctrl_dev *pctl; + /* register read/write mutex */ + struct mutex mutex; + const struct jh8100_pinctrl_domain_info *info; + unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; + /* wakeup */ + struct irq_domain *irq_domain; + struct gpio_desc *wakeup_gpio; + int wakeup_irq; +}; + +struct jh8100_gpio_func_sel { + unsigned short offset; + unsigned char shift; + unsigned char max; +}; + +struct jh8100_gpio_irq_reg { + unsigned int is_reg_base; + unsigned int ic_reg_base; + unsigned int ic1_reg_base; + unsigned int ibe_reg_base; + unsigned int iev_reg_base; + unsigned int ie_reg_base; + unsigned int ris_reg_base; + unsigned int mis_reg_base; + unsigned int mis1_reg_base; + unsigned int ien_reg_base; +}; + +struct jh8100_pinctrl_domain_info { + const struct pinctrl_pin_desc *pins; + unsigned int npins; + unsigned int ngpios; + unsigned int gc_base; + + const char *name; + unsigned int nregs; + + /* gpio dout/doen/din/gpioinput register */ + unsigned int dout_reg_base; + unsigned int dout_mask; + unsigned int doen_reg_base; + unsigned int doen_mask; + unsigned int gpi_reg_base; + unsigned int gpi_mask; + unsigned int gpioin_reg_base; + + const struct jh8100_gpio_func_sel *func_sel; + const struct jh8100_gpio_irq_reg *irq_reg; + + /* gpio chip */ + unsigned int mis_pin_num; + unsigned int mis1_pin_num; +}; + +int jh8100_pinctrl_probe(struct platform_device *pdev); +void jh8100_set_gpiomux(struct jh8100_pinctrl *sfp, unsigned int pin, + unsigned int din, u32 dout, u32 doen); +struct jh8100_pinctrl *jh8100_from_irq_desc(struct irq_desc *desc); +void pinctrl_utils_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int num_maps); +int pinmux_generic_get_function_count(struct pinctrl_dev *pctldev); +const char *pinmux_generic_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector); +int pinmux_generic_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups); +int pinmux_generic_add_function(struct pinctrl_dev *pctldev, + const char *name, + const char * const *groups, + unsigned int const num_groups, + void *data); + +#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF) +int pinconf_generic_parse_dt_config(struct device_node *np, + struct pinctrl_dev *pctldev, + unsigned long **configs, + unsigned int *nconfigs); +#endif + +#endif /* __PINCTRL_STARFIVE_JH8100_H__ */ From patchwork Fri May 3 11:14:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Soo X-Patchwork-Id: 794482 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2126.outbound.protection.partner.outlook.cn [139.219.17.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16B1A1534E7; Fri, 3 May 2024 12:49:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.17.126 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714740571; cv=fail; b=sOkYj1bQyRGBV30Ly2Azd6S8ZG2fgylOWh+/WBPBJdsuKdz+Fr3xuLO3odGSry4aT+Jo6x3XumHKNnzFp7+pEz6NIn9fwxQAOAqeywKU6a3wMau7BxVHUj38yqn42dRdhYr24YnlSlVReqBLkNh0hF9lm/f0HdGU3QpcgWFSjKI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714740571; c=relaxed/simple; bh=b0+Y/H4T61Q/T2VkWr6mLoegIZnSoJJuLeH9xqrU4V0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=l41TMMJxOJR2+tslVtH+rISWdUs4MvMBf7mhOGDuufNh8vUT0Zgw2eiM0XNTqPThv5lSqr06IUGx0rxMGDmEx+GKfeXgMAs8UvwSV4CzTJ7fjpUgBdiQEsZpZIQRhhQJmS7mUP5awRY27FTZGs57LkcCUo6WBavJFqXfaKu7XTw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.17.126 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Yc6emfCmmDOaSNi28/XZ36qJiEN5xlMtx7/4sBurXVbKkGtA3bFXuU9lzuLB056zPlcEtIodUikXz+S3XcJk3tWN1capU0umaZQRMt3V5Z6jTRj5S57zS3lRw4rQIrc1dY82q9JxUp56tSr/uAxayB3HAuMCYjzhzZHpYfKZpt1Hcya7Pe2mLCLWgptMpmh7/7tQZNJ0vzO2AZI4XacuZeVkHgAtkNYd4uSrk+fJUIGaHjq7x9sX0ciWytYPMPlUtrT6cUZ+4T7GiK4tjtR+oVKpxtRRRuAs3RxX4bvU6LVGI61LVQ5XhhW/pTUQ9P9CGfORjfE85zzDoVtpBEot7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=A4jb7iFCnA3QDskpBV8VGbbtzV1NunIi753ciHo9LA8=; b=PBpisGU65Dt0urmk38HKq1cOhgFwgIAjGhsPAhQWQ17Dc/ApwHlXSuSeK7jPPOWkEq30ipyUR979Ib7pBfewcme1UxrjG8SLBwR42sZSNRQaWcHjQH5eiE6lv2cYXdpRzc9ThnoNNnW/mtt+qCNtp1ugHxt+A54ydfmKf4psqx9OyzTPi9dcf5G3X/7rDWYIqqqunZh30aq+g/So79OPejhWnVpdtWr8CeezvUftkq0oNn1naGqwfRRCF8CxHTCAe86e/gss9of1nxj0ngvIvu/sZbbiFo6FVPe3WIDyoRwwBZmsbneWgUalfguRYEwLf3A155k6CB+MfrnkOAJGfQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1238.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:14:56 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:14:56 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 3/7] pinctrl: starfive: jh8100: add sys_west domain sub-driver Date: Fri, 3 May 2024 19:14:32 +0800 Message-Id: <20240503111436.113089-4-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1238:EE_ X-MS-Office365-Filtering-Correlation-Id: d12fe879-e9cc-4afe-dda7-08dc6b62434b X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U51KBppsyaMNg4IC/g5pQ90fRSAsK09+VMlb7wgqPrUbA0we6UjC66YazeXvxFGDHq3CZ2hTIWz7Jr3xG7qouQ1tcNdJhgTPuWberl5PiTdeKajc0yfWzJc55DdfIynBOql/Wi68Rq4iCjXgR1MCoK5Beu8U2ryb7X+lhIvNgbtnpbnjlNexC0oEFZMandGll61BAn/84D2z+gOTRz5a1KqkaV2YqiFiKwwo+d8lay39tzssnyHjnozz/qnT0HxugIuu4VhjYt/F9903X2GjKMYHloFlu5kh8GDljSpyFU/dqtnk9AxpWlUqVMS7fR5aSkYVsyfEdwzttFm//DzfKtDBVzhos8m3SZB0iFgLXGAD2PDq2rnX68w9pQsKcPB6461ET44Lh5h+p9hlTDEylvx91L2a4ush5brBsyGUxawdNmqgCmSy2v+adwjk+gOXEzeOfpPj6J+FSL7utUIJ8wohyXWANENC4z+myq4A/b//fyGNup9iq/KJt1BEcg1rPHSDgKGvZLH6wnwUDUHShaMyEqM7Qh42Eeu5gQn/GOVh39E231BYCPidBYcgj+n2nGjSPZaIx4CxPWDqlFOfZwhsd0aZ2DLx06RvSskkHz+4Z8lkNeJuoHRmGVF2bexw4b+5myLW4u+9tXvJPMiZ7g== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(52116005)(41320700004)(7416005)(366007)(1800799015)(38350700005)(921011); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xw0xFhWEZzb3s9qqQ9Qj8DWMV/5Nev6px5oGNZTna1FQcp3sGVNG8VQ0TgnYx0+yKyi8/COoKKNMKJoXgmKq331eUpEBqXqCYToCFT0aWvvkj2hjxb37linxfMjKZ0xGnIMDDP9MV7x4Sfu5Lq25s/GREACNucEg9DxulkW7haSrypkdAu8c3omiXBVUPMRFKcMwiMtKxMZ2j7KytfkVsBvvEg/bNbllVY/v7pN2tnqMy/yLo3Qi9xGbBQorOflXPSAg5s2DripEyOGl9pEU+MZMKU3CrIJq94BmnDQlP3IsYpZEGQL0BfJjGjdJBTzXYQbwP83dsz+brI30ibI5qke8VdmYgVJ7AjOizM55KY/zOFxfKaFznsJauK2PjvA00699CIMJf1HTy47BY0lTFnEnXQGvdCo5lYKJiK3bAiGuuQq/1R6dCfh0dPj5EltL+lMSTB0VyiJg5BhZI/ndRE2n5NZrMHvEXKNlFJUU7riMTvU07GZzO73rgUm7UL/mx5pECBRabU88jZkcDolRuxm8RlKfm1a8yV5X+hHWPjR1ezQev1e6cZeFfBNWZwAwgizAKuruwPkRl0INeH80FbGtjOzUyfvxpm0B25VPzIcR1WIgPe1pFHzIuwxF1/4r2Ik+icWAX1vmkMM6Ycia2Yv59evcqt+KixIASWpVZmVs/EiNxKIP5+Yea4PXr10ayt7feRuRkeUt5OWqZyt+mfw89NxsdqR7xbRzWcAvivr/nPKGRBEdKoPo9ifEMcYjWJOEw7Rx3k6SiXj1kOOqTwNCXELxvW9m+rfZPecOydFlbgyHuz5WJ9dc89mgFQducMGDrT7/2o3jjpEdSspuzFAl9vQpLPjU6JB302GRoJbQectorBvNcHNIkSljV7kVRblvZ5BsFZ67q9yNmbJ8L4EIQhyUfzncZN70DZRjb3Q3PFMymf7218PBFQVD/recdka4M/HJRURXj1rO/rFRSB365J/ytJipaRNwWuDbCDrgymymYKYLTTufzKlA6PJSRbu2apwR9e2VLMqGqFOOvs0a0jtSfcyn+XnRX0+DU1mqsBK9FbUQKUjvsVu8xOA8HinFGxOjbDowEbb4Xm4CC53e3f2eI/vAcxqC8cGKMMQxx5p3VNPK+TOHST97yLPHdx9V9BeagiX4QdfP5+Caf/66jFowOzb6qHkF2/p16osgftQ3CzFXr5LsGUqAz817X2q4SdN+427m9tr91IjxDp+0a/1uCPMs1w6iSVfQS6VA60wCLv5walnPpmxCkmNfuGQgQAJJV885fzUTA57fQRPJjB8deRVB6OapQM7jBMkpDPv+QmIdXWRnnnaZpK9xuXRaUMDdIRowAssFcjxORmA4YuRTuT2YtwwZMnQ3obYEg6b1XTuFTxVsnYGeGPliDzF4y0J+IsgxbOjZowhv66XsWZg+6SZLgypLNcDVW2yxpKAx4BsPqemDDlpAx0IBsMqsynwvlexspGGmIA6VSqs9CNLZV84/h8GATz9dfWtg8FDPGKlShgVYOeZvdaWuPwAqQOd15cgVOpmgFzrb/lWdNnc5/yK6OnvqQs/8HFH/McaJfrqjTgNauTcqOI6N3icCbD9ATb1bkcjsLNMVGw== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: d12fe879-e9cc-4afe-dda7-08dc6b62434b X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:14:56.0756 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: uXFjiYlC6YSZd5Xk7hS+bK4jGc6fY/Zpdc27ERRDV9PKQxWEk4Js4js+IfaaoiVk6QjRZGhFd0anXwImHASt0vjOFkwOMo76teJMdxseruY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1238 Add sys_west domain sub-driver. Signed-off-by: Alex Soo --- drivers/pinctrl/starfive/Kconfig | 12 ++ drivers/pinctrl/starfive/Makefile | 1 + .../pinctrl-starfive-jh8100-sys-west.c | 164 ++++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.c | 6 + .../starfive/pinctrl-starfive-jh8100.h | 5 + 5 files changed, 188 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index afcbf9d4dc8d..d78f161a636c 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -70,3 +70,15 @@ config PINCTRL_STARFIVE_JH8100_SYS_EAST This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH8100_SYS_WEST + tristate "StarFive JH8100 SoC System IOMUX-West pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support system iomux-west pin control on the StarFive JH8100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 45698c502b48..784465157ae2 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_WEST) += pinctrl-starfive-jh8100-sys-west.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c new file mode 100644 index 000000000000..b97d89777aa3 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-west.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC sys west controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_SYS_W_GC_BASE 0 + +/* registers */ +#define JH8100_SYS_W_DOEN 0x000 +#define JH8100_SYS_W_DOUT 0x010 +#define JH8100_SYS_W_GPI 0x020 +#define JH8100_SYS_W_GPIOIN 0x068 + +#define JH8100_SYS_W_GPIOEN 0x048 +#define JH8100_SYS_W_GPIOIS0 0x04c +#define JH8100_SYS_W_GPIOIC0 0x050 +#define JH8100_SYS_W_GPIOIBE0 0x054 +#define JH8100_SYS_W_GPIOIEV0 0x058 +#define JH8100_SYS_W_GPIOIE0 0x05c +#define JH8100_SYS_W_GPIORIS0 0x060 +#define JH8100_SYS_W_GPIOMIS0 0x064 + +static const struct pinctrl_pin_desc jh8100_sys_w_pins[] = { + PINCTRL_PIN(0, "SYS_W_GPIO0"), + PINCTRL_PIN(1, "SYS_W_GPIO1"), + PINCTRL_PIN(2, "SYS_W_GPIO2"), + PINCTRL_PIN(3, "SYS_W_GPIO3"), + PINCTRL_PIN(4, "SYS_W_GPIO4"), + PINCTRL_PIN(5, "SYS_W_GPIO5"), + PINCTRL_PIN(6, "SYS_W_GPIO6"), + PINCTRL_PIN(7, "SYS_W_GPIO7"), + PINCTRL_PIN(8, "SYS_W_GPIO8"), + PINCTRL_PIN(9, "SYS_W_GPIO9"), + PINCTRL_PIN(10, "SYS_W_GPIO10"), + PINCTRL_PIN(11, "SYS_W_GPIO11"), + PINCTRL_PIN(12, "SYS_W_GPIO12"), + PINCTRL_PIN(13, "SYS_W_GPIO13"), + PINCTRL_PIN(14, "SYS_W_GPIO14"), + PINCTRL_PIN(15, "SYS_W_GPIO15"), +}; + +static const struct jh8100_gpio_func_sel + jh8100_sys_w_func_sel[ARRAY_SIZE(jh8100_sys_w_pins)] = { + [0] = { 0xb4, 0, 2 }, + [1] = { 0xb4, 12, 2 }, + [2] = { 0xb4, 14, 2 }, + [3] = { 0xb4, 16, 2 }, + [4] = { 0xb4, 18, 2 }, + [5] = { 0xb4, 20, 2 }, + [6] = { 0xb4, 22, 2 }, + [7] = { 0xb4, 24, 2 }, + [8] = { 0xb4, 26, 2 }, + [9] = { 0xb4, 28, 2 }, + [10] = { 0xb4, 2, 2 }, + [11] = { 0xb4, 4, 2 }, + [12] = { 0xb4, 6, 2 }, + [13] = { 0xb4, 8, 2 }, + [14] = { 0xb4, 10, 2 }, +}; + +#ifdef CONFIG_PM_SLEEP +static int jh8100_sys_w_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_sys_west_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_sys_w_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_sys_west_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_sys_w_pinctrl_dev_pm_ops, + jh8100_sys_w_pinctrl_suspend, + jh8100_sys_w_pinctrl_resume); + +static const struct jh8100_gpio_irq_reg jh8100_sys_w_irq_reg = { + .is_reg_base = JH8100_SYS_W_GPIOIS0, + .ic_reg_base = JH8100_SYS_W_GPIOIC0, + .ibe_reg_base = JH8100_SYS_W_GPIOIBE0, + .iev_reg_base = JH8100_SYS_W_GPIOIEV0, + .ie_reg_base = JH8100_SYS_W_GPIOIE0, + .ris_reg_base = JH8100_SYS_W_GPIORIS0, + .mis_reg_base = JH8100_SYS_W_GPIOMIS0, + .ien_reg_base = JH8100_SYS_W_GPIOEN, +}; + +static const struct jh8100_pinctrl_domain_info jh8100_sys_w_pinctrl_info = { + .pins = jh8100_sys_w_pins, + .npins = ARRAY_SIZE(jh8100_sys_w_pins), + .ngpios = JH8100_SYS_W_NGPIO, + .gc_base = JH8100_SYS_W_GC_BASE, + .name = JH8100_SYS_W_DOMAIN_NAME, + .nregs = JH8100_SYS_W_REG_NUM, + .dout_reg_base = JH8100_SYS_W_DOUT, + .dout_mask = GENMASK(5, 0), + .doen_reg_base = JH8100_SYS_W_DOEN, + .doen_mask = GENMASK(4, 0), + .gpi_reg_base = JH8100_SYS_W_GPI, + .gpi_mask = GENMASK(4, 0), + .gpioin_reg_base = JH8100_SYS_W_GPIOIN, + .func_sel = jh8100_sys_w_func_sel, + .irq_reg = &jh8100_sys_w_irq_reg, + .mis_pin_num = JH8100_SYS_W_NGPIO, +}; + +static const struct of_device_id jh8100_sys_w_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-sys-pinctrl-west", + .data = &jh8100_sys_w_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_sys_w_pinctrl_of_match); + +static struct platform_driver jh8100_sys_w_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-sys-pinctrl-west", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_sys_w_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_sys_w_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_sys_w_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC sys west controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c index 4b68463ff5a5..8c3e4a90d68d 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.c @@ -333,6 +333,9 @@ static int jh8100_set_one_pin_mux(struct jh8100_pinctrl *sfp, if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME) && pin < sfp->gc.ngpio && func == 1) jh8100_set_function(sfp, pin, func); + else if (!strcmp(sfp->info->name, JH8100_SYS_W_DOMAIN_NAME) && + pin < sfp->gc.ngpio - 1 && func == 2) + jh8100_set_function(sfp, pin, func); return 0; } @@ -410,6 +413,9 @@ static int jh8100_get_padcfg_base(struct jh8100_pinctrl *sfp, if (!strcmp(sfp->info->name, JH8100_SYS_E_DOMAIN_NAME)) { if (pin < JH8100_SYS_E_NGPIO) return JH8100_SYS_E_GPO_PDA_00_47_CFG; + } else if (!strcmp(sfp->info->name, JH8100_SYS_W_DOMAIN_NAME)) { + if (pin < JH8100_SYS_W_NGPIO) + return JH8100_SYS_W_GPO_PDA_00_15_CFG; } return -ENXIO; diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h index 6eb4f1896a90..7c7a05c1c828 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -12,12 +12,16 @@ #include "../core.h" +#define JH8100_SYS_W_DOMAIN_NAME "jh8100-sys-west" #define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" +#define JH8100_SYS_W_NGPIO 16 #define JH8100_SYS_E_NGPIO 48 +#define JH8100_SYS_W_REG_NUM 44 #define JH8100_SYS_E_REG_NUM 116 +#define JH8100_SYS_W_GPO_PDA_00_15_CFG 0x074 #define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 struct jh8100_pinctrl { @@ -30,6 +34,7 @@ struct jh8100_pinctrl { /* register read/write mutex */ struct mutex mutex; const struct jh8100_pinctrl_domain_info *info; + unsigned int jh8100_sys_west_regs[JH8100_SYS_W_REG_NUM]; unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; /* wakeup */ struct irq_domain *irq_domain; From patchwork Fri May 3 11:14:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Soo X-Patchwork-Id: 794484 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2115.outbound.protection.partner.outlook.cn [139.219.146.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9D6F2D047; Fri, 3 May 2024 11:48:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.115 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714736889; cv=fail; b=u3XCqypjJzvJIhUSVvFWIWCczajmD+Ox8MymQLXTHfbbsIZtimkfbfPYxIlvFXbyn2gXUt3/NrJTX7swPQee0aEGeEem+X+AciLT0qjLSzG9Ng6XaDck4GkqFr58pssZS7Y1IgqHfjAY1JR/qJKGdch/P8hlb5RqGNpHCvEgrRI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714736889; c=relaxed/simple; bh=o/Wod2U8hAhdsu3bhCQzkZbU9R6FXaQhXn2SqtUa5Wc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=PLtDLfzdPl8FHQyYodvXKk6jh/mPHYRlvhAeIRDLbGfTNSlEdwBlVN0KKWkK0NRize/aAQprgafCMiVGBz4aPxYqTilSn9pfL/5DESplM972DhgxUpg/UtT+FJAV8ZlL/vOTBBSiAp2YMAHHUi9V+/F3u1jdw624JeYRMSvRDg4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.146.115 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Bq6pobkJ+VnTrnfwfi0GzZXMl4YH5b+tdGSe5vqIwhQSn4OUiLd9slAhmdYn9pWEiYisPww+NX1E02zkDqxu1LlCPP3rpCdQbi8MzBgBXMzi4JUELbD+/SQV76SkjzvridqDSGwkkfDmtDYIhpnQy4aMGodX3zSN+dTjS961LW1/6EghCq8TnNFzaq6cTQjFj7U619e9cHIV869RQfNsDFOfWiyp5f14qQmeSZaciRqUdx7bdHhb8vfDxWdCugNSVYntDCPjfA9VJN7vlb2U3V09rvGadEVOU3pmISvloGtkiB2u9JHixPRo5V1uXxrD/7wzvUXlIyM7e8VbcM/elA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=g+kPXEwFOk6Vk6fj8TZBhGJ/JG1x9D8pU73iMkL4xfE=; b=lhsdWqIodwjDnN1Q+onQwgd16Ty4n2OGOE11kTafBFo4Bgd45YR92OnfByao2nHBl0W/ZdpCWIOH0Cxb4/xsr3FNfIhbTj63Sb1x0ZdpeGNS4DfgQVtXvUBK/ral5PGGyLERMPgWc8Rh6TAKGHMPHz2z9e3GQMMrPCG9xGvh0QwbfhzDZMY4vwf9d/sog5zuqUiqCWWlvUo8q02EiK/sxTAzId9ZEjQ0wGEHzQ68cxDtImXEVPEXI3a1SBf9FBbtk/SE6NRmqtsBwYh6lce910uuRzUy9gjaecos0KbAOCmZJOrVTDt6BQkUE7PNKiOywnJDTuCVM0lMs0mcGvCmwg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1238.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:14:59 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:14:59 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 4/7] pinctrl: starfive: jh8100: add sys_gmac domain sub-driver Date: Fri, 3 May 2024 19:14:33 +0800 Message-Id: <20240503111436.113089-5-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1238:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d7faab7-cbef-46ae-ceca-08dc6b624517 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LZxcT0xyLFmYe0ZJJTvXCd09ilen3M5IsP1qhP6c0ayaEhycrIoO/7YnSI0kfUq5j1iwCEsaB1nJvD5B7lRZfA/0rWGeKedsEQhMaG5MNldKCR00R2R4JwvwuJ62VdvXFeElNvsCl6sxeqNcCmWcoQpW8K2xqbDSb0Hjs8TIjGGWe6fgteeIg1WXaz9ZgEA01df/YoPsmpNQ6IpddSHizn4eHn+7nTk0mU4LFZ0ZX3+J3loB+R5qaHPJ8XQAC3Zlh6j0Xmrx1yveKyzH5n4YLhAWz+RknB6FAW2tqr+LMzf3gfS6aE2c6uz2P7hMqsLx9YL7OJGvmaJxJXJA7ujfqY5OnxCOP3VhIXdYk4RhqxJqc5ismJPtkZQAAA+KYvUtXCd0Ql742YP3Ia7+mSlg9K9ZXm+mOZZErMKcJv7ceOo538GV4YV3d9ONs3mezgcun5V2UMpOyvIjmFgcxwDbZTXiKdKkRvnaQvHGud/IjfmzPLn6meTFie3jKahiKjzkIX48zKGfAf011unlKAaJ2uu0vtQZm1xvOdaQVDRDu+zDIDbJdeQ3GthNumMiotv48BZTLoKGk+D7K73IW4nTgbLnvLGmxHBDaIgJxkekl6BxoSCKJiulAAG+qoq1W3ADF6FRmikDy0yJOoXzZdEDfw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(52116005)(41320700004)(7416005)(366007)(1800799015)(38350700005)(921011); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tnQ7ZEx9FEyHPY+iw38HlOwBhTmLy0IhnlzhEyAy0yETKuljK/HLtMC5TLzz+7SwSwkhRc9bBrNAjkClsbsVODm4mNsZTSAwUWRdXHwn3DQKvIV45LB2Wrx3f3LyeHUgRTvbho+mttjZLnC6tzACZTW3Wcn1G3ue/x8Sczi/NwXEsSR1vIM14rXkfRjgfnB0uMB0yTs+Up5iCm/fLUf/g1tjVOh/FzEOJ2vgmQMQDxKsrTZ+IwNk8yzu+J2U9YiLyuRp1/4/b1rVUme1aQU3yZWxbx7ioRAwlHZmBXAAur7dNNyu/GnFrU84sWaTHvNk1GwsaZ+xylceo/UAcqK2g/8LWR3GuZTJ2L1+R5veM62Yi+VLypN8jZ1iTcO1fLmYleK104wAIqjTpelCPnRDV2CwUI4ZW7ueJVr7u+tdUAs6TuT4BqJt1DvQ9ap4Fa68SBM15DZga6cqEAXGomfA9uN49SRKa16cyabQ0vqC7A3lQ5Osk1PcOM8WffPtarWhKVU5kP5IqOe8lWftuCosiAFfuAq62VO6Yb5wTz3l88NAPsSjEZkkz3pmpcIQwWUR0DkiOJOynnR6Fj4uMn1pWGrlPLvYz56+Tcm4OD5oOYqz2IYrZmXkBlrYG8k8Ax8pYjkAk7AqbrAletnUBjrlFgu1LIa1jN5/wFH3MgNf//MuUjgMjcj+xn4OKGpM+UmWgDYyNFTO0S5I5PBj5akEhj2k4Fdqmzat/uJ6tj/eaoq1fiJ81po6zbLzLev1tc+4JUxm36Ce9nqpSIcG+s58PJKD/tKEUqbz922yCFtQIlA+k1BBVO0QAmaltnYUzZrzKxnadAuTUckav4K5J6baagAes5bDLrK6vWZVx4QOn7lCfQoCBEuv0IROJmjZOy842aUDtZ/elYyzeRpDFDu8PtKI9iJxo0n6yknbuxUyD4Q322YSbA1zEbUWvG59pF35KM+jNQqliZ+RqsqekaaCkHTuu702wv4G91T+bHbMUYPyT4cCTdJmp9qH//wOKOIFiJK4JNiGNZAZRcwtJaUWh9ZuVgij8LzrUwu2X9q6+ELqq2409Uu76Rc4EydHvMdBClf58c05iPLuhdJnBqVPc6m/67hTxSSccFE4BwNvLU/KtCTRcbJcfPpjbcLueakN3SJb09OpYAZA8wxh4sAW/ETbA+1mtxcdiwo+GMJ2gi6igA31X1Hfb9BoUIWgS2a0eCf45t4hFki6wQpOsNJKa43AysU9q1+AEftziwgWoFpe2LTFwTcFiScQQPENYWtrrLy99SxF85gsIl4vD0/WRBSep/pFHzmpjTVfmbpE/hM56OuE/xoHSVe1cTb6wBFu81nERCE9O3yEnx/qljdTFkMXjT0e/+vFYw53IQ3sFtwaJr3lm1d2imh6P/iC8Fi1YPq1ARjf2WnWDfAnh3u8ZWp/N7tLM7J5tndBVQ3E7bf4u2UUjdjVMNhi8qerk599ukUgMVaGVw490RoSS5CRgBzzMNIrOgE2GRbIZ5tVvRQMUnNZFTqFmnHFBxdc+F5X/W95ghFyb3TPIGOp4L+M8/nGsa8EsApEgU4gsYtBqSWfJntQDdQaJMJWjhrANHrLXix1JSN1F5nPPh6TOVY1dg== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0d7faab7-cbef-46ae-ceca-08dc6b624517 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:14:59.0925 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Tws8oIYOsK8q+1inhguB+BWXqv4bNPNo1LCyghpl8xMY3CnQ848v7stb16QyfOpMfqaf3WbvutAOpp3LAlE82oYQCkb4gip4BZ1v4jOqhiw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1238 Add sys_gmac domain sub-driver. Signed-off-by: Alex Soo --- drivers/pinctrl/starfive/Kconfig | 12 +++ drivers/pinctrl/starfive/Makefile | 1 + .../pinctrl-starfive-jh8100-sys-gmac.c | 89 +++++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.h | 4 + 4 files changed, 106 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-gmac.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index d78f161a636c..bc123c0bf35e 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -82,3 +82,15 @@ config PINCTRL_STARFIVE_JH8100_SYS_WEST This also provides an interface to the GPIO pins not used by other peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. + +config PINCTRL_STARFIVE_JH8100_SYS_GMAC + tristate "StarFive JH8100 SoC System IOMUX-GMAC pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support system iomux-gmac pin control on the StarFive JH8100 SoC. + This provides syscon registers to indicate voltage level on SDIO1/GMAC1, to indicate + GMAC1 pads voltage level under different GMAC interface modes, and to configure + GMAC1 interface slew rate. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 784465157ae2..236a693a8aef 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_WEST) += pinctrl-starfive-jh8100-sys-west.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_GMAC) += pinctrl-starfive-jh8100-sys-gmac.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-gmac.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-gmac.c new file mode 100644 index 000000000000..3758280e3660 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-sys-gmac.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC sys gmac controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_SYS_G_GC_BASE -1 +#define JH8100_SYS_G_DOMAIN_NAME "jh8100-sys-gmac" + +#ifdef CONFIG_PM_SLEEP +static int jh8100_sys_gmac_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_sys_gmac_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_sys_gmac_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_sys_gmac_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_sys_gmac_pinctrl_dev_pm_ops, + jh8100_sys_gmac_pinctrl_suspend, + jh8100_sys_gmac_pinctrl_resume); + +static const struct jh8100_pinctrl_domain_info jh8100_sys_gmac_pinctrl_info = { + .ngpios = JH8100_SYS_G_NGPIO, + .gc_base = JH8100_SYS_G_GC_BASE, + .name = JH8100_SYS_G_DOMAIN_NAME, + .nregs = JH8100_SYS_G_REG_NUM, +}; + +static const struct of_device_id jh8100_sys_gmac_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-sys-pinctrl-gmac", + .data = &jh8100_sys_gmac_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_sys_gmac_pinctrl_of_match); + +static struct platform_driver jh8100_sys_gmac_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-sys-pinctrl-gmac", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_sys_gmac_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_sys_gmac_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_sys_gmac_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC sys gmac controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h index 7c7a05c1c828..90eef6417dd7 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -14,12 +14,15 @@ #define JH8100_SYS_W_DOMAIN_NAME "jh8100-sys-west" #define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" +#define JH8100_SYS_G_DOMAIN_NAME "jh8100-sys-gmac" #define JH8100_SYS_W_NGPIO 16 #define JH8100_SYS_E_NGPIO 48 +#define JH8100_SYS_G_NGPIO 0 #define JH8100_SYS_W_REG_NUM 44 #define JH8100_SYS_E_REG_NUM 116 +#define JH8100_SYS_G_REG_NUM 19 #define JH8100_SYS_W_GPO_PDA_00_15_CFG 0x074 #define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 @@ -36,6 +39,7 @@ struct jh8100_pinctrl { const struct jh8100_pinctrl_domain_info *info; unsigned int jh8100_sys_west_regs[JH8100_SYS_W_REG_NUM]; unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; + unsigned int jh8100_sys_gmac_regs[JH8100_SYS_G_REG_NUM]; /* wakeup */ struct irq_domain *irq_domain; struct gpio_desc *wakeup_gpio; From patchwork Fri May 3 11:14:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Soo X-Patchwork-Id: 794485 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2139.outbound.protection.partner.outlook.cn [139.219.17.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31D6D152193; Fri, 3 May 2024 11:15:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.17.139 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714734915; cv=fail; b=CQ2Bre6SWG4jA1IosmbnEofyIGNum9UorgSkeIJJxWhZvjuoL2NweNS4fUYlTp77LdJzHDajyUsiBM/FD5fE25b93DqgV4+cE75gG+H/KV2KXwxsHAuFyqVbHa7yIO97TUQ+nJndz0VRYIbv+Aci2Q2FDXvB+uYXgrjUBoR+tXo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714734915; c=relaxed/simple; bh=3qOIH8Lv+VG0PbhRMvTuEHuVFClRqRVgFLVFmh74las=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=Ny+XRLpwqXrd7i3WBm6GdKj8RVFU/onqsM3pDIL3+fTuP/23haGcD/2IegMEZWhSd317HsCu3oky9VpYX68IAszg+Wj99FuSpKRDFvQdg3sXuFZXTXTKBX6fijtIy8C78cwKJbVwPpS+BnHp2NA2pGbluKW+uYyM5tTwPUv4Vu8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com; spf=pass smtp.mailfrom=starfivetech.com; arc=fail smtp.client-ip=139.219.17.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jlvKIViyg9sKWJP0+CRNaCxzGcvSOOhH8NtoTjv+vOl926zjllICY+B/RzKC+fkGMU+d26CgHXG6yyD88yaSOpPBMPzv7C8Jx5zqXBB8K6YXyb/cWB95txm2GdNOP/jbFCLuJr80eiBWVlv25/Co5jClE04hmmtg9hBgS+vWBPcBjbbAYe770DcEJgly77Rt2EEeS/02Q9DGlgHjICxZaOzS6NCbdJ16tl0A68vu+erAR7jHdH/hobmHv3yP/J+3UVFrWwATZppwUdgW9rg9XT84e4OEEvNjGZH2V22OOlCkscyfq12nINB39QHT5k+SaTO6vhBasjbdBSeWYKXnwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dAqNpNO+pzoUOb1ovcRYsgkdv6JzCxdG9bEgFv6/p0Q=; b=bkKIM/sjjQRILtyCzWH/GJsjqaDWCrSlwzP4lpcBGxN6pzaK0wlsTBki9OTKHXjsz0OQ92ba39eT/oJrbaIFbg9JPMkx30ALRMujsb0rZyaxMJPPefJ5Rq38Fc2z9FW2on26XkT/7nfASNrlmoOEfbS58fSWgnoGbd+belxqJZV7CONEiqBDyujWjb3St0KRgFCCha2fmftZwdchqtisBujKJ7PUMj6H3PntCuP2mTZM7YkD7yxOQhtmS5OtYXVMmhwd0GEZyYwTxQaxs99rS++m1/ri52dEUCN/C/FctIpLypGF+enI6oJ28VNmYGJebqLESUTF1MFfFyrm/EiJAA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) by ZQ0PR01MB1112.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.44; Fri, 3 May 2024 11:15:05 +0000 Received: from ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4]) by ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn ([fe80::feb4:a4b4:1132:58f4%5]) with mapi id 15.20.7472.044; Fri, 3 May 2024 11:15:05 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v3 6/7] gpiolib: enable GPIO interrupt to wake up a system from sleep Date: Fri, 3 May 2024 19:14:35 +0800 Message-Id: <20240503111436.113089-7-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240503111436.113089-1-yuklin.soo@starfivetech.com> References: <20240503111436.113089-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0011.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::20) To ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:19::9) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1176:EE_|ZQ0PR01MB1112:EE_ X-MS-Office365-Filtering-Correlation-Id: ebce3d29-f0be-4031-fc78-08dc6b6248d4 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NwHDAIU/Y9PYmIoVj46oSiFQgBksWJK4YZtdts3CQ10zkRJD3XTKUbVcLlC6G4cfouyTMFgiOrZ1Vjq2m40MPjFpjJNg4Xj1cOZsD8yMmvrPcEtpe/pbFq9RbREUf62RuiZgjV/7bcqTm8AylumF1H9Hxt+4PlLZxudMyRfte2UgHSLxUwAVEdpOBtGKS10UTLWJuvHP5v/80JQpfOdEsy5C2/nDImWD9Cqm9PPds9yIO4zFkkxmoxDw7nOze8vf5vi0KBjrIcKr4MgAve/eVsio6FNnsO64yrMnLzFO2LMv9YsSCPWfA4/Bil83J3Db6MLBH3jyortkiKQOg+6MUztqX9Xfnuc2uVwqzpYdhfcrgG+L49hszZP/7klJe4VeN31gPi/QpYZ6p8uIEAwYhJgOoAUrqxxAulIdtBHTDEbkovN7d7D6iJAvtS12+vsP1oqrqhqQGdHqx1+tDo/xpI7pWkTe4fJ3Vv/+h+aoE6m7jPBkYw5nNMSXJekQf7zWlvRzALHpYSZLeotF5oTutMUBMXWL2+ANhvCzFXFn3IR3PjbJf/S0apkjJhRxqwTU3xR1b8a227U9bnBTqHdhORVMHmPs+yxXtIwcg0aPsKFBlqRhWVG9IAufMu6oQ7rUnC9dwRz5uswwArTu7UjUKA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn; PTR:; CAT:NONE; SFS:(13230031)(41320700004)(7416005)(1800799015)(52116005)(366007)(38350700005)(921011); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wUFH8X3wJl+3Y78oXno3rgnp0IZbQUjiD5Es4WWqSM7fr6XYhKh8BTnubT0jIsq/NofV54V6B+ti1CTB+q1yzd7LdcGtHVBkk+vqXLPhwpqF/f65WEqmF6n2cM5deJXLuPjSPYk+CFNR8Cams0vjLsemmYP6C6Mcr4kc0ZyynPDnnOxCLPfv5CVhhzxuNOBNv35Y1fo1RYLJxzgKf0x5QtLDyFwotunYvWDeJHgDDloZEo08ZJeCd+JlTc+KCuHOUrhuQJG3r+wGqvkisWEV7yHW5lLfJUPcJFWz05NArIhlp/AbvDaYRNlrT6vvL4GakCWC3k1jKtxbHRaSbaYnQdVRFwj8gbZDbNu1fzVYRDOP7tAEjVlv5KRMmtCPIKPTxng9a91pRaClEndcez01tpenugAUJFFQAaTcmP+53xlaBXAfvPuAlsmDeHv08YArhB9Ms7qSLI8GNZrvv6pzClkmxge79fSzWGsBMHDhKHlO5HkrH6ZGD5hdENR4uzV7MNpvZmb5/VFmH1vCVx4LGN3hyfKv2BPobKterJcun8/1vmyhuLabfp92YNIGvJSAgVwbCdtEFUmQMLmSl2B860luVF8FqlMaMTVSonXD9n/+nfC+xSJvDcY8Rqg5vE23RNsuGJ2Cf6BjqzfHGDJ/uXA7ptwzYgvfqIoHZnqbDP1iCl84CB8GEikN1OBWouUa8B2UjcUqYsMJkR8xgGBtCf4T49t+rgVALqI98SaqXVRsI7j04JTi6OxCc8Z7GgQAZ6S3L5h3SRnWEt7hiwU6TY/nxmdp7DZmEMwXj56AyKu5yhBm1TxDE1U3mmeDP+wiLSxvenFjfzOwzHkAbIlaDhqJKiVn8m74gH0lAkPc+EC/PNQJClUE8tIS1NjDr7Y+H3quea8p3g9Q+TDE0mc8T/VIjUFaqrH0G5zW3ILyKHeOHZsJc62O6gN2ZaGJ44YN2Zk+DI8ehYZCkzuLTrkvEulaVzBzINY8sOkCChOp2O7OCC98GD+rzrczj9/WP9agKYqFvOqCbdk8wHTLyAQsBzOvHI55xwkfdHr22b6Armh7bcgspo1YFVQpNfiy7c9jQthkPLptrfBLn/z9RluiEO4UPgKkwwK3PjZQ3QF9zEi+mh2kglcltf6GxT0qtczgmt5iayJGqj/TjeOK/whmmkTY88KmCPhIdB7obMJ+2rPKxp1W0C1jKB25bcbzHWQExbizRiUgtH5BuZ8U9o3SDjKNGMdE/w23P7U8HQpI9z5hTzhxA8XjRJatEm0nfh12mJtbcymJUwCIR7JQRd4Wx/U/VQMTrFywJHDFct+JKU1O+YWknnUJf0dmOjoMr5Du++pO2E7jBMBAlfPjU+7hXecv5YSIBqvxViUNynii4bQltLzEsULIQpB4UNKKf8oSg4+bX1JE47H5PB2xh1FfryToNzW1lTQepGKtGE4lXLj7ldIWFUGTwBXdBJwSLUCkJtkeytSQUN9SojG7dJb8/HLVoFeqOYWqAupfn6aIeHfnkTiYxccTrAEDFIqeFBNPGU79FmYVSCmt3beV5eBEsMbOfBLxcZ0Gf7rM5JOd/0C0t2TU+x7u8S1rbA1CQOM7Fti4k1zQh/7vnLZxBYmwYw== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: ebce3d29-f0be-4031-fc78-08dc6b6248d4 X-MS-Exchange-CrossTenant-AuthSource: ZQ0PR01MB1176.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2024 11:15:05.3566 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: uwz7IU8b1Bb22q5T70iUIpLHoGS8688VTJYSP68RbPJHTsoLKTHScN3l/mZf5lEGTZyMsPk1Cbmlu4cQlvjdC1Tkrq9sEZtT5t72H+ZOB6U= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQ0PR01MB1112 Add function gpiochip_wakeup_irq_setup() to configure and enable a GPIO pin with interrupt wakeup capability according to user-defined wakeup-gpios property in the device tree. Interrupt generated by toggling the logic level (rising/falling edge) on the specified GPIO pin can wake up a system from sleep mode. Signed-off-by: Alex Soo --- drivers/gpio/gpiolib.c | 87 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 94903fc1c145..92cfbc34abb0 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -96,6 +97,7 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gc); static int gpiochip_irqchip_init_hw(struct gpio_chip *gc); static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gc); static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gc); +static int gpiochip_wakeup_irq_setup(struct gpio_chip *gc); static bool gpiolib_initialized; @@ -1045,8 +1047,15 @@ int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, if (ret) goto err_remove_irqchip; } + + ret = gpiochip_wakeup_irq_setup(gc); + if (ret) + goto err_remove_device; + return 0; +err_remove_device: + gcdev_unregister(gdev); err_remove_irqchip: gpiochip_irqchip_remove(gc); err_remove_irqchip_mask: @@ -1874,6 +1883,84 @@ static int gpiochip_irqchip_add_allocated_domain(struct gpio_chip *gc, return 0; } +static irqreturn_t gpio_wake_irq_handler(int irq, void *data) +{ + struct irq_data *irq_data = data; + + if (!irq_data || irq != irq_data->irq) + return IRQ_NONE; + + return IRQ_HANDLED; +} + +static int gpiochip_wakeup_irq_setup(struct gpio_chip *gc) +{ + struct device *dev = gc->parent; + struct gpio_irq_chip *girq = &gc->irq; + struct gpio_desc *wakeup_gpiod; + struct irq_desc *wakeup_irqd; + struct irq_domain *irq_domain; + struct irq_data *irq_data; + unsigned int offset; + int wakeup_irq; + int ret; + + if (!(device_property_read_bool(dev, "wakeup-source"))) + return 0; + + irq_domain = girq->domain; + + if (!irq_domain) { + dev_err(dev, "Couldn't allocate IRQ domain\n"); + return -ENXIO; + } + + wakeup_gpiod = devm_gpiod_get_optional(dev, "wakeup", GPIOD_IN); + + if (IS_ERR(wakeup_gpiod)) { + dev_err(dev, "invalid wakeup gpio: %lu\n", PTR_ERR(wakeup_gpiod)); + return PTR_ERR(wakeup_gpiod); + } + if (!wakeup_gpiod) { + dev_dbg(dev, "property wakeup-gpios is not defined\n"); + return 0; + } + + offset = gpio_chip_hwgpio(wakeup_gpiod); + wakeup_irq = gpiod_to_irq(wakeup_gpiod); + if (wakeup_irq < 0) { + dev_err(dev, "failed to convert wakeup GPIO to IRQ\n"); + return wakeup_irq; + } + irq_domain->ops->map(irq_domain, wakeup_irq, offset); + wakeup_irqd = irq_to_desc(wakeup_irq); + irq_data = irq_get_irq_data(wakeup_irq); + girq->handler = handle_edge_irq; + + if (!(wakeup_irqd->status_use_accessors & IRQ_NOREQUEST)) { + device_init_wakeup(dev, 1); + ret = devm_request_threaded_irq(dev, wakeup_irq, NULL, + gpio_wake_irq_handler, + IRQF_TRIGGER_FALLING | + IRQF_TRIGGER_RISING | + IRQF_ONESHOT | + IRQF_SHARED, + "pm-wakeup-gpio", irq_data); + if (ret) { + dev_err(dev, "unable to request wakeup IRQ: %d\n", ret); + return ret; + } + } + + ret = dev_pm_set_wake_irq(dev, wakeup_irq); + if (ret) { + dev_err(dev, "failed to enable gpio irq wake\n"); + return ret; + } + + return 0; +} + /** * gpiochip_add_irqchip() - adds an IRQ chip to a GPIO chip * @gc: the GPIO chip to add the IRQ chip to