From patchwork Tue May 7 15:54:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 795392 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19362168B18 for ; Tue, 7 May 2024 15:55:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097316; cv=none; b=QQd/Mbzym5DiGHPKVT2K8bhd7AbIpLpcU6AVZvlGtS7gdTAZkMH3Lvmf2GhVMdYbSou4z+e9r83VFPUHol8pWP5VJMjyTFRuHZf2vE32I++wJlD56SDxQXknZtUrukPrBkCwwSMqhBVMhVGesHSiWl77eAjAU70pnfWSwX7Xb0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097316; c=relaxed/simple; bh=3Z54om05C99PgUXag4ah6Qh00jU2HZ3rMA6Ed26Bqes=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=a1gMUaXn+mVwmI2+U0tB3wujMiplFdsXBzymT0GUQP0xDzlghbbIY7ZqL8DdUCW2P3s76UwnovdtlsHFXMaCHjmXxPjYcwvELMCojEHgJXNvAODS63h7f//iMUV62mXOY72DicyxVv2tHrbm7uTOfETTJLYPFGcTQa0yIrjW9uM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=cYvNlere; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="cYvNlere" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-61bb09d8fecso60047707b3.0 for ; Tue, 07 May 2024 08:55:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1715097312; x=1715702112; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=9idoWjT7C/CpOygYJseK27lqfFE7kXdK2UIJxaXf2Rg=; b=cYvNlerei1YdwHyv9KaQRxyA3GDlqVOK6QuJ3wa7KTIVcu8Z1+PDOoWQPtgX0iRBoV tUpaFl78ffc5MJmMwbO4AyXKcE5h5WpdRQpgp5lEFRkcBxqcNHXQccwGDWaibbtrRYLy G3uIJRahUZvaX9AGWKgGq19O9nhjh14eqsRLEtArSpmPg4Zflb0c8EUebXaSO8VRXINE oe6QTLiGU05rr+IYGBncRrhODa2VGrEd/rmwZXFYdHJ1qypTkGInM2D+6AomOWCR9SoL K2hwztghOKM5hHU0+dZ4VxXwRgOC+8Whye0mB88r8itX0AQ8PAdvbAU0dSOEcWNvdDzm bPkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715097312; x=1715702112; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=9idoWjT7C/CpOygYJseK27lqfFE7kXdK2UIJxaXf2Rg=; b=gomK0kp2pR1fBaAM7QpJ+hkHZcCzUnKkqeAQ41nWsELnlR61ItU6U4DJQQThdkQ8jD sVav2yn9ltV4SgbpRRMK50y2cDqVljlfoQyNKql30AXbYfTXPuO+bhw2bAZtOOC9+8XO R56q3J/I2nXNUGFXOskdvbRknpbLIftCAGHNX5k5igzZ6o0Av5ns7oLt4K3OSRgfjlOp /J2huH+2J3ql7xxEbfR/1iyLp6pTk3XGAfkcY4UmFbjzZAqZtNttYLPWYdScSRyKeSti XqPehPDkHyoHE2CdlZi0IAosCB0rxX66eV+/EkwKmArWyXlj5cucX7OkeUev3yv67h6Y 0eaw== X-Forwarded-Encrypted: i=1; AJvYcCWpqtwJQffTN90KSYCF7Q3k6nnCFcqVNBkLVQP13+eynnxT+9I/lAOT1IjzaCrIBsm78D1YKasvw7/AF6RCnQ01KzfUNmtBSGib7B4= X-Gm-Message-State: AOJu0YwFbrbLYIwg4UHfY/Uf3F0j+2s37Lugl++WcDE1CXWHpRSRQXmP 03pG2nOcl7rosCUCYsOG5bBlzJ/CpzZQ5vBjLqtpgvs8lOMXcgRC49Ags0U7QlZmCY+F1stGysY I4qKwag3Cuw== X-Google-Smtp-Source: AGHT+IFtnnsoc7TgcbxAb5JpRmGG6brCL/7XuJ1NU6l9qw8hRKBezRDZo+ZRQo0Du/RWa75TCU5gdIU8n7+bdA== X-Received: from szatan.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:2d83]) (user=panikiel job=sendgmr) by 2002:a0d:d204:0:b0:61b:4d3:2dd6 with SMTP id 00721157ae682-62085b0bec6mr376237b3.6.1715097311959; Tue, 07 May 2024 08:55:11 -0700 (PDT) Date: Tue, 7 May 2024 15:54:04 +0000 In-Reply-To: <20240507155413.266057-1-panikiel@google.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240507155413.266057-1-panikiel@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240507155413.266057-2-panikiel@google.com> Subject: [PATCH v3 01/10] media: Add Chameleon v3 video interface driver From: " =?utf-8?q?Pawe=C5=82_Anikiel?= " To: airlied@gmail.com, akpm@linux-foundation.org, conor+dt@kernel.org, daniel@ffwll.ch, dinguyen@kernel.org, hverkuil-cisco@xs4all.nl, krzysztof.kozlowski+dt@linaro.org, maarten.lankhorst@linux.intel.com, mchehab@kernel.org, mripard@kernel.org, robh+dt@kernel.org, tzimmermann@suse.de Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, chromeos-krk-upstreaming@google.com, " =?utf-8?q?Pawe=C5=82_Anikiel?= " Add v4l2 driver for the video interface present on the Google Chameleon v3. The Chameleon v3 uses the video interface to capture a single video source from a given HDMI or DP connector and write the resulting frames to memory. Signed-off-by: Paweł Anikiel --- drivers/media/platform/Kconfig | 1 + drivers/media/platform/Makefile | 1 + drivers/media/platform/google/Kconfig | 13 + drivers/media/platform/google/Makefile | 3 + drivers/media/platform/google/chv3-video.c | 891 +++++++++++++++++++++ 5 files changed, 909 insertions(+) create mode 100644 drivers/media/platform/google/Kconfig create mode 100644 drivers/media/platform/google/Makefile create mode 100644 drivers/media/platform/google/chv3-video.c diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 91e54215de3a..b82f7b142b85 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -69,6 +69,7 @@ source "drivers/media/platform/aspeed/Kconfig" source "drivers/media/platform/atmel/Kconfig" source "drivers/media/platform/cadence/Kconfig" source "drivers/media/platform/chips-media/Kconfig" +source "drivers/media/platform/google/Kconfig" source "drivers/media/platform/intel/Kconfig" source "drivers/media/platform/marvell/Kconfig" source "drivers/media/platform/mediatek/Kconfig" diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 3296ec1ebe16..f7067eb05f76 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -12,6 +12,7 @@ obj-y += aspeed/ obj-y += atmel/ obj-y += cadence/ obj-y += chips-media/ +obj-y += google/ obj-y += intel/ obj-y += marvell/ obj-y += mediatek/ diff --git a/drivers/media/platform/google/Kconfig b/drivers/media/platform/google/Kconfig new file mode 100644 index 000000000000..9674a4c12e2d --- /dev/null +++ b/drivers/media/platform/google/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config VIDEO_CHAMELEONV3 + tristate "Google Chameleon v3 video driver" + depends on V4L_PLATFORM_DRIVERS + depends on VIDEO_DEV + select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE + help + v4l2 driver for the video interface present on the Google + Chameleon v3. The Chameleon v3 uses the video interface to + capture a single video source from a given HDMI or DP connector + and write the resulting frames to memory. diff --git a/drivers/media/platform/google/Makefile b/drivers/media/platform/google/Makefile new file mode 100644 index 000000000000..cff06486244c --- /dev/null +++ b/drivers/media/platform/google/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_VIDEO_CHAMELEONV3) += chv3-video.o diff --git a/drivers/media/platform/google/chv3-video.c b/drivers/media/platform/google/chv3-video.c new file mode 100644 index 000000000000..6e782484abaf --- /dev/null +++ b/drivers/media/platform/google/chv3-video.c @@ -0,0 +1,891 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2023-2024 Google LLC. + * Author: Paweł Anikiel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEVICE_NAME "chv3-video" + +#define VIDEO_EN 0x00 +#define VIDEO_EN_BIT BIT(0) +#define VIDEO_HEIGHT 0x04 +#define VIDEO_WIDTH 0x08 +#define VIDEO_BUFFERA 0x0c +#define VIDEO_BUFFERB 0x10 +#define VIDEO_BUFFERSIZE 0x14 +#define VIDEO_RESET 0x18 +#define VIDEO_RESET_BIT BIT(0) +#define VIDEO_ERRORSTATUS 0x1c +#define VIDEO_IOCOLOR 0x20 +#define VIDEO_DATARATE 0x24 +#define VIDEO_DATARATE_SINGLE 0x0 +#define VIDEO_DATARATE_DOUBLE 0x1 +#define VIDEO_PIXELMODE 0x28 +#define VIDEO_PIXELMODE_SINGLE 0x0 +#define VIDEO_PIXELMODE_DOUBLE 0x1 +#define VIDEO_SYNCPOLARITY 0x2c +#define VIDEO_DMAFORMAT 0x30 +#define VIDEO_DMAFORMAT_8BPC 0x0 +#define VIDEO_DMAFORMAT_10BPC_UPPER 0x1 +#define VIDEO_DMAFORMAT_10BPC_LOWER 0x2 +#define VIDEO_DMAFORMAT_12BPC_UPPER 0x3 +#define VIDEO_DMAFORMAT_12BPC_LOWER 0x4 +#define VIDEO_DMAFORMAT_16BPC 0x5 +#define VIDEO_DMAFORMAT_RAW 0x6 +#define VIDEO_DMAFORMAT_8BPC_PAD 0x7 +#define VIDEO_VERSION 0x34 +#define VIDEO_VERSION_CURRENT 0xc0fb0001 + +#define VIDEO_IRQ_MASK 0x8 +#define VIDEO_IRQ_CLR 0xc +#define VIDEO_IRQ_ALL 0xf +#define VIDEO_IRQ_BUFF0 BIT(0) +#define VIDEO_IRQ_BUFF1 BIT(1) +#define VIDEO_IRQ_RESOLUTION BIT(2) +#define VIDEO_IRQ_ERROR BIT(3) + +struct chv3_video { + struct device *dev; + void __iomem *iobase; + void __iomem *iobase_irq; + + struct v4l2_device v4l2_dev; + struct vb2_queue queue; + struct video_device vdev; + struct v4l2_pix_format pix_fmt; + struct v4l2_dv_timings timings; + u32 bytes_per_pixel; + + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_async_notifier notifier; + struct v4l2_subdev *subdev; + int subdev_source_pad; + + u32 sequence; + bool writing_to_a; + + struct list_head bufs; + spinlock_t bufs_lock; + + struct mutex video_lock; +}; + +struct chv3_video_buffer { + struct vb2_v4l2_buffer vb; + struct list_head link; +}; + +struct chv3_video_config { + u32 pixelformat; + u32 bytes_per_pixel; + u32 dmaformat; +}; + +static void chv3_video_set_format_resolution(struct chv3_video *video, u32 width, u32 height) +{ + video->pix_fmt.width = width; + video->pix_fmt.height = height; + video->pix_fmt.bytesperline = width * video->bytes_per_pixel; + video->pix_fmt.sizeimage = video->pix_fmt.bytesperline * height; +} + +/* + * The video interface has hardware counters which expose the width and + * height of the current video stream. It can't reliably detect if the stream + * is present or not, so this is only used as a fallback in the case where + * we don't have access to the receiver hardware. + */ +static int chv3_video_query_dv_timings_fallback(struct chv3_video *video, + struct v4l2_dv_timings *timings) +{ + u32 width, height; + + width = readl(video->iobase + VIDEO_WIDTH); + height = readl(video->iobase + VIDEO_HEIGHT); + if (width == 0 || height == 0) + return -ENOLINK; + + memset(timings, 0, sizeof(*timings)); + timings->type = V4L2_DV_BT_656_1120; + timings->bt.width = width; + timings->bt.height = height; + timings->bt.pixelclock = width * height * 24; + + return 0; +} + +static int chv3_video_query_dv_timings(struct chv3_video *video, struct v4l2_dv_timings *timings) +{ + if (video->subdev) { + return v4l2_subdev_call(video->subdev, pad, query_dv_timings, + video->subdev_source_pad, timings); + } else { + return chv3_video_query_dv_timings_fallback(video, timings); + } +} + +static const struct v4l2_dv_timings_cap chv3_video_fallback_dv_timings_cap = { + .type = V4L2_DV_BT_656_1120, + .bt = { + .min_width = 640, + .max_width = 7680, + .min_height = 480, + .max_height = 4320, + .min_pixelclock = 25000000, + .max_pixelclock = 1080000000, + .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | + V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF, + .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE | + V4L2_DV_BT_CAP_REDUCED_BLANKING | + V4L2_DV_BT_CAP_CUSTOM, + }, +}; + +static int chv3_video_enum_dv_timings_fallback(struct chv3_video *video, + struct v4l2_enum_dv_timings *timings) +{ + return v4l2_enum_dv_timings_cap(timings, &chv3_video_fallback_dv_timings_cap, + NULL, NULL); +} + +static int chv3_video_dv_timings_cap_fallback(struct chv3_video *video, + struct v4l2_dv_timings_cap *cap) +{ + *cap = chv3_video_fallback_dv_timings_cap; + + return 0; +} + +static void chv3_video_apply_dv_timings(struct chv3_video *video) +{ + struct v4l2_dv_timings timings; + int res; + + res = chv3_video_query_dv_timings(video, &timings); + if (res) + return; + + video->timings = timings; + chv3_video_set_format_resolution(video, timings.bt.width, timings.bt.height); +} + +static int chv3_video_querycap(struct file *file, void *fh, struct v4l2_capability *cap) +{ + strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver)); + strscpy(cap->card, "Chameleon v3 video", sizeof(cap->card)); + + return 0; +} + +static int chv3_video_g_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *fmt) +{ + struct chv3_video *video = video_drvdata(file); + + fmt->fmt.pix = video->pix_fmt; + + return 0; +} + +static int chv3_video_enum_fmt_vid_cap(struct file *file, void *fh, struct v4l2_fmtdesc *fmt) +{ + struct chv3_video *video = video_drvdata(file); + + if (fmt->index != 0) + return -EINVAL; + + fmt->flags = 0; + fmt->pixelformat = video->pix_fmt.pixelformat; + + return 0; +} + +static int chv3_video_g_input(struct file *file, void *fh, unsigned int *index) +{ + *index = 0; + + return 0; +} + +static int chv3_video_s_input(struct file *file, void *fh, unsigned int index) +{ + if (index != 0) + return -EINVAL; + + return 0; +} + +static int chv3_video_enum_input(struct file *file, void *fh, struct v4l2_input *input) +{ + if (input->index != 0) + return -EINVAL; + + strscpy(input->name, "input0", sizeof(input->name)); + input->type = V4L2_INPUT_TYPE_CAMERA; + input->capabilities = V4L2_IN_CAP_DV_TIMINGS; + + return 0; +} + +static int chv3_video_g_edid(struct file *file, void *fh, struct v4l2_edid *edid) +{ + struct chv3_video *video = video_drvdata(file); + int res; + + if (!video->subdev) + return -ENOTTY; + + if (edid->pad != 0) + return -EINVAL; + + edid->pad = video->subdev_source_pad; + res = v4l2_subdev_call(video->subdev, pad, get_edid, edid); + edid->pad = 0; + + return res; +} + +static int chv3_video_s_edid(struct file *file, void *fh, struct v4l2_edid *edid) +{ + struct chv3_video *video = video_drvdata(file); + int res; + + if (!video->subdev) + return -ENOTTY; + + if (edid->pad != 0) + return -EINVAL; + + edid->pad = video->subdev_source_pad; + res = v4l2_subdev_call(video->subdev, pad, set_edid, edid); + edid->pad = 0; + + return res; +} + +static int chv3_video_s_dv_timings(struct file *file, void *fh, struct v4l2_dv_timings *timings) +{ + struct chv3_video *video = video_drvdata(file); + + if (v4l2_match_dv_timings(&video->timings, timings, 0, false)) + return 0; + + if (vb2_is_busy(&video->queue)) + return -EBUSY; + + if (!v4l2_valid_dv_timings(timings, &chv3_video_fallback_dv_timings_cap, NULL, NULL)) + return -ERANGE; + + video->timings = *timings; + chv3_video_set_format_resolution(video, timings->bt.width, timings->bt.height); + + return 0; +} + +static int chv3_video_g_dv_timings(struct file *file, void *fh, struct v4l2_dv_timings *timings) +{ + struct chv3_video *video = video_drvdata(file); + + *timings = video->timings; + return 0; +} + +static int chv3_video_vidioc_query_dv_timings(struct file *file, void *fh, + struct v4l2_dv_timings *timings) +{ + struct chv3_video *video = video_drvdata(file); + + return chv3_video_query_dv_timings(video, timings); +} + +static int chv3_video_enum_dv_timings(struct file *file, void *fh, + struct v4l2_enum_dv_timings *timings) +{ + struct chv3_video *video = video_drvdata(file); + int res; + + if (timings->pad != 0) + return -EINVAL; + + if (video->subdev) { + timings->pad = video->subdev_source_pad; + res = v4l2_subdev_call(video->subdev, pad, enum_dv_timings, timings); + timings->pad = 0; + return res; + } else { + return chv3_video_enum_dv_timings_fallback(video, timings); + } +} + +static int chv3_video_dv_timings_cap(struct file *file, void *fh, struct v4l2_dv_timings_cap *cap) +{ + struct chv3_video *video = video_drvdata(file); + int res; + + if (cap->pad != 0) + return -EINVAL; + + if (video->subdev) { + cap->pad = video->subdev_source_pad; + res = v4l2_subdev_call(video->subdev, pad, dv_timings_cap, cap); + cap->pad = 0; + return res; + } else { + return chv3_video_dv_timings_cap_fallback(video, cap); + } +} + +static int chv3_video_subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_SOURCE_CHANGE: + return v4l2_src_change_event_subscribe(fh, sub); + } + + return v4l2_ctrl_subscribe_event(fh, sub); +} + +static const struct v4l2_ioctl_ops chv3_video_v4l2_ioctl_ops = { + .vidioc_querycap = chv3_video_querycap, + + .vidioc_enum_fmt_vid_cap = chv3_video_enum_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = chv3_video_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = chv3_video_g_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = chv3_video_g_fmt_vid_cap, + + .vidioc_enum_input = chv3_video_enum_input, + .vidioc_g_input = chv3_video_g_input, + .vidioc_s_input = chv3_video_s_input, + .vidioc_g_edid = chv3_video_g_edid, + .vidioc_s_edid = chv3_video_s_edid, + + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, + + .vidioc_s_dv_timings = chv3_video_s_dv_timings, + .vidioc_g_dv_timings = chv3_video_g_dv_timings, + .vidioc_query_dv_timings = chv3_video_vidioc_query_dv_timings, + .vidioc_enum_dv_timings = chv3_video_enum_dv_timings, + .vidioc_dv_timings_cap = chv3_video_dv_timings_cap, + + .vidioc_subscribe_event = chv3_video_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static int chv3_video_queue_setup(struct vb2_queue *q, + unsigned int *nbuffers, unsigned int *nplanes, + unsigned int sizes[], struct device *alloc_devs[]) +{ + struct chv3_video *video = vb2_get_drv_priv(q); + + if (*nplanes) { + if (sizes[0] < video->pix_fmt.sizeimage) + return -EINVAL; + return 0; + } + *nplanes = 1; + sizes[0] = video->pix_fmt.sizeimage; + + return 0; +} + +/* + * There are two address registers: BUFFERA and BUFFERB. The device + * alternates writing between them (i.e. even frames go to BUFFERA, odd + * ones to BUFFERB). + * + * (buffer queue) > QUEUED ---> QUEUED ---> QUEUED ---> ... + * BUFFERA BUFFERB + * (hw writing to this) ^ + * (and then to this) ^ + * + * The buffer swapping happens at irq time. When an irq comes, the next + * frame is already assigned an address in the buffer queue. This gives + * the irq handler a whole frame's worth of time to update the buffer + * address register. + */ + +static dma_addr_t chv3_video_buffer_dma_addr(struct chv3_video_buffer *buf) +{ + return vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); +} + +static void chv3_video_start_frame(struct chv3_video *video, struct chv3_video_buffer *buf) +{ + video->writing_to_a = 1; + writel(chv3_video_buffer_dma_addr(buf), video->iobase + VIDEO_BUFFERA); + writel(VIDEO_EN_BIT, video->iobase + VIDEO_EN); +} + +static void chv3_video_next_frame(struct chv3_video *video, struct chv3_video_buffer *buf) +{ + u32 reg = video->writing_to_a ? VIDEO_BUFFERB : VIDEO_BUFFERA; + + writel(chv3_video_buffer_dma_addr(buf), video->iobase + reg); +} + +static int chv3_video_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct chv3_video *video = vb2_get_drv_priv(q); + struct chv3_video_buffer *buf; + unsigned long flags; + + video->sequence = 0; + writel(video->pix_fmt.sizeimage, video->iobase + VIDEO_BUFFERSIZE); + + spin_lock_irqsave(&video->bufs_lock, flags); + buf = list_first_entry_or_null(&video->bufs, struct chv3_video_buffer, link); + if (buf) { + chv3_video_start_frame(video, buf); + if (!list_is_last(&buf->link, &video->bufs)) + chv3_video_next_frame(video, list_next_entry(buf, link)); + } + spin_unlock_irqrestore(&video->bufs_lock, flags); + + return 0; +} + +static void chv3_video_stop_streaming(struct vb2_queue *q) +{ + struct chv3_video *video = vb2_get_drv_priv(q); + struct chv3_video_buffer *buf; + unsigned long flags; + + writel(0, video->iobase + VIDEO_EN); + + spin_lock_irqsave(&video->bufs_lock, flags); + list_for_each_entry(buf, &video->bufs, link) + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + INIT_LIST_HEAD(&video->bufs); + spin_unlock_irqrestore(&video->bufs_lock, flags); +} + +static void chv3_video_buf_queue(struct vb2_buffer *vb) +{ + struct chv3_video *video = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *v4l2_buf = to_vb2_v4l2_buffer(vb); + struct chv3_video_buffer *buf = container_of(v4l2_buf, struct chv3_video_buffer, vb); + bool first, second; + unsigned long flags; + + spin_lock_irqsave(&video->bufs_lock, flags); + first = list_empty(&video->bufs); + second = list_is_singular(&video->bufs); + list_add_tail(&buf->link, &video->bufs); + if (vb2_is_streaming(vb->vb2_queue)) { + if (first) + chv3_video_start_frame(video, buf); + else if (second) + chv3_video_next_frame(video, buf); + } + spin_unlock_irqrestore(&video->bufs_lock, flags); +} + +static const struct vb2_ops chv3_video_vb2_ops = { + .queue_setup = chv3_video_queue_setup, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .start_streaming = chv3_video_start_streaming, + .stop_streaming = chv3_video_stop_streaming, + .buf_queue = chv3_video_buf_queue, +}; + +static int chv3_video_open(struct file *file) +{ + struct chv3_video *video = video_drvdata(file); + int res; + + mutex_lock(&video->video_lock); + res = v4l2_fh_open(file); + if (!res) { + if (v4l2_fh_is_singular_file(file)) + chv3_video_apply_dv_timings(video); + } + mutex_unlock(&video->video_lock); + + return res; +} + +static const struct v4l2_file_operations chv3_video_v4l2_fops = { + .owner = THIS_MODULE, + .open = chv3_video_open, + .release = vb2_fop_release, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, + .poll = vb2_fop_poll, +}; + +static void chv3_video_frame_irq(struct chv3_video *video) +{ + struct chv3_video_buffer *buf; + + spin_lock(&video->bufs_lock); + + buf = list_first_entry_or_null(&video->bufs, struct chv3_video_buffer, link); + if (!buf) + goto empty; + list_del(&buf->link); + + vb2_set_plane_payload(&buf->vb.vb2_buf, 0, video->pix_fmt.sizeimage); + buf->vb.vb2_buf.timestamp = ktime_get_ns(); + buf->vb.sequence = video->sequence++; + buf->vb.field = V4L2_FIELD_NONE; + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + buf = list_first_entry_or_null(&video->bufs, struct chv3_video_buffer, link); + if (buf) { + video->writing_to_a = !video->writing_to_a; + if (!list_is_last(&buf->link, &video->bufs)) + chv3_video_next_frame(video, list_next_entry(buf, link)); + } else { + writel(0, video->iobase + VIDEO_EN); + } +empty: + spin_unlock(&video->bufs_lock); +} + +static void chv3_video_error_irq(struct chv3_video *video) +{ + if (vb2_is_streaming(&video->queue)) + vb2_queue_error(&video->queue); +} + +static void chv3_video_resolution_irq(struct chv3_video *video) +{ + static const struct v4l2_event event = { + .type = V4L2_EVENT_SOURCE_CHANGE, + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, + }; + + v4l2_event_queue(&video->vdev, &event); + chv3_video_error_irq(video); +} + +static irqreturn_t chv3_video_isr(int irq, void *data) +{ + struct chv3_video *video = data; + unsigned int reg; + + reg = readl(video->iobase_irq + VIDEO_IRQ_CLR); + if (!reg) + return IRQ_NONE; + + if (reg & VIDEO_IRQ_BUFF0) + chv3_video_frame_irq(video); + if (reg & VIDEO_IRQ_BUFF1) + chv3_video_frame_irq(video); + if (reg & VIDEO_IRQ_RESOLUTION) + chv3_video_resolution_irq(video); + if (reg & VIDEO_IRQ_ERROR) { + dev_warn(video->dev, "error: 0x%x\n", + readl(video->iobase + VIDEO_ERRORSTATUS)); + chv3_video_error_irq(video); + } + + writel(reg, video->iobase_irq + VIDEO_IRQ_CLR); + + return IRQ_HANDLED; +} + +static int chv3_video_check_version(struct chv3_video *video) +{ + u32 version; + + version = readl(video->iobase + VIDEO_VERSION); + if (version != VIDEO_VERSION_CURRENT) { + dev_err(video->dev, + "wrong hw version: expected %x, got %x\n", + VIDEO_VERSION_CURRENT, version); + return -ENODEV; + } + return 0; +} + +static void chv3_video_init_timings_and_format(struct chv3_video *video, + const struct chv3_video_config *config) +{ + struct v4l2_pix_format *pix = &video->pix_fmt; + struct v4l2_dv_timings timings = V4L2_DV_BT_CEA_1920X1080P60; + + video->timings = timings; + video->bytes_per_pixel = config->bytes_per_pixel; + + pix->pixelformat = config->pixelformat; + pix->field = V4L2_FIELD_NONE; + pix->colorspace = V4L2_COLORSPACE_SRGB; + chv3_video_set_format_resolution(video, timings.bt.width, timings.bt.height); +} + +#define notifier_to_video(nf) container_of(nf, struct chv3_video, notifier) + +static int chv3_video_async_notify_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_connection *asc) +{ + struct chv3_video *video = notifier_to_video(notifier); + int pad; + + pad = media_entity_get_fwnode_pad(&subdev->entity, asc->match.fwnode, + MEDIA_PAD_FL_SOURCE); + if (pad < 0) + return pad; + + video->subdev = subdev; + video->subdev_source_pad = pad; + + video->v4l2_dev.ctrl_handler = subdev->ctrl_handler; + + return 0; +} + +static void chv3_video_async_notify_unbind(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_connection *asc) +{ + struct chv3_video *video = notifier_to_video(notifier); + + vb2_video_unregister_device(&video->vdev); +} + +static int chv3_video_async_notify_complete(struct v4l2_async_notifier *notifier) +{ + struct chv3_video *video = notifier_to_video(notifier); + + return video_register_device(&video->vdev, VFL_TYPE_VIDEO, -1); +} + +static const struct v4l2_async_notifier_operations chv3_video_async_notify_ops = { + .bound = chv3_video_async_notify_bound, + .unbind = chv3_video_async_notify_unbind, + .complete = chv3_video_async_notify_complete, +}; + +static int chv3_video_fallback_init(struct chv3_video *video) +{ + int res; + + video->subdev = NULL; + video->subdev_source_pad = 0; + + v4l2_ctrl_handler_init(&video->ctrl_handler, 1); + v4l2_ctrl_new_std(&video->ctrl_handler, NULL, + V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0); + res = video->ctrl_handler.error; + if (res) + goto handler_free; + + video->v4l2_dev.ctrl_handler = &video->ctrl_handler; + + res = video_register_device(&video->vdev, VFL_TYPE_VIDEO, -1); + if (res) + goto handler_free; + + return 0; + +handler_free: + v4l2_ctrl_handler_free(&video->ctrl_handler); + + return res; +} + +static int chv3_video_fwnode_init(struct chv3_video *video) +{ + struct v4l2_async_connection *asc; + struct fwnode_handle *endpoint; + int res; + + endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(video->dev), NULL); + if (!endpoint) + return -EINVAL; + + v4l2_async_nf_init(&video->notifier, &video->v4l2_dev); + + asc = v4l2_async_nf_add_fwnode_remote(&video->notifier, endpoint, + struct v4l2_async_connection); + fwnode_handle_put(endpoint); + + if (IS_ERR(asc)) + return PTR_ERR(asc); + + video->notifier.ops = &chv3_video_async_notify_ops; + res = v4l2_async_nf_register(&video->notifier); + if (res) { + v4l2_async_nf_cleanup(&video->notifier); + return res; + } + + return 0; +} + +static int chv3_video_probe(struct platform_device *pdev) +{ + struct chv3_video *video; + const struct chv3_video_config *config; + int res; + int irq; + + video = devm_kzalloc(&pdev->dev, sizeof(*video), GFP_KERNEL); + if (!video) + return -ENOMEM; + video->dev = &pdev->dev; + platform_set_drvdata(pdev, video); + + config = device_get_match_data(video->dev); + + /* map register space */ + video->iobase = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(video->iobase)) + return PTR_ERR(video->iobase); + + video->iobase_irq = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(video->iobase_irq)) + return PTR_ERR(video->iobase_irq); + + /* check hw version */ + res = chv3_video_check_version(video); + if (res) + return res; + + /* setup interrupts */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return -ENXIO; + res = devm_request_irq(&pdev->dev, irq, chv3_video_isr, 0, DEVICE_NAME, video); + if (res) + return res; + + /* initialize v4l2_device */ + res = v4l2_device_register(&pdev->dev, &video->v4l2_dev); + if (res) + return res; + + /* initialize vb2 queue */ + video->queue.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + video->queue.io_modes = VB2_MMAP | VB2_DMABUF; + video->queue.dev = &pdev->dev; + video->queue.lock = &video->video_lock; + video->queue.ops = &chv3_video_vb2_ops; + video->queue.mem_ops = &vb2_dma_contig_memops; + video->queue.drv_priv = video; + video->queue.buf_struct_size = sizeof(struct chv3_video_buffer); + video->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + res = vb2_queue_init(&video->queue); + if (res) + goto error; + + /* initialize video_device */ + strscpy(video->vdev.name, DEVICE_NAME, sizeof(video->vdev.name)); + video->vdev.fops = &chv3_video_v4l2_fops; + video->vdev.ioctl_ops = &chv3_video_v4l2_ioctl_ops; + video->vdev.lock = &video->video_lock; + video->vdev.release = video_device_release_empty; + video->vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + video->vdev.v4l2_dev = &video->v4l2_dev; + video->vdev.queue = &video->queue; + video_set_drvdata(&video->vdev, video); + + if (device_get_named_child_node(&pdev->dev, "port")) + res = chv3_video_fwnode_init(video); + else + res = chv3_video_fallback_init(video); + if (res) + goto error; + + /* initialize rest of driver struct */ + INIT_LIST_HEAD(&video->bufs); + spin_lock_init(&video->bufs_lock); + mutex_init(&video->video_lock); + + chv3_video_init_timings_and_format(video, config); + + /* initialize hw */ + writel(VIDEO_RESET_BIT, video->iobase + VIDEO_RESET); + writel(VIDEO_DATARATE_DOUBLE, video->iobase + VIDEO_DATARATE); + writel(VIDEO_PIXELMODE_DOUBLE, video->iobase + VIDEO_PIXELMODE); + writel(config->dmaformat, video->iobase + VIDEO_DMAFORMAT); + + writel(VIDEO_IRQ_ALL, video->iobase_irq + VIDEO_IRQ_MASK); + + return 0; + +error: + v4l2_device_unregister(&video->v4l2_dev); + + return res; +} + +static void chv3_video_remove(struct platform_device *pdev) +{ + struct chv3_video *video = platform_get_drvdata(pdev); + + /* disable interrupts */ + writel(0, video->iobase_irq + VIDEO_IRQ_MASK); + + if (video->subdev) { + /* notifier is initialized only in non-fallback mode */ + v4l2_async_nf_unregister(&video->notifier); + v4l2_async_nf_cleanup(&video->notifier); + } else { + /* ctrl handler is initialized only in fallback mode */ + v4l2_ctrl_handler_free(&video->ctrl_handler); + } + + v4l2_device_unregister(&video->v4l2_dev); +} + +static const struct chv3_video_config chv3_video_it = { + .pixelformat = V4L2_PIX_FMT_BGRX32, + .bytes_per_pixel = 4, + .dmaformat = VIDEO_DMAFORMAT_8BPC_PAD, +}; + +static const struct chv3_video_config chv3_video_dp = { + .pixelformat = V4L2_PIX_FMT_RGB24, + .bytes_per_pixel = 3, + .dmaformat = VIDEO_DMAFORMAT_8BPC, +}; + +static const struct of_device_id chv3_video_match_table[] = { + { .compatible = "google,chv3-video-it-1.0", .data = &chv3_video_it }, + { .compatible = "google,chv3-video-dp-1.0", .data = &chv3_video_dp }, + { }, +}; + +static struct platform_driver chv3_video_platform_driver = { + .probe = chv3_video_probe, + .remove_new = chv3_video_remove, + .driver = { + .name = DEVICE_NAME, + .of_match_table = chv3_video_match_table, + }, +}; + +module_platform_driver(chv3_video_platform_driver); + +MODULE_AUTHOR("Paweł Anikiel "); +MODULE_DESCRIPTION("Google Chameleon v3 video interface driver"); +MODULE_LICENSE("GPL"); From patchwork Tue May 7 15:54:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 795391 Received: from mail-wm1-f73.google.com (mail-wm1-f73.google.com [209.85.128.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E542D16C687 for ; Tue, 7 May 2024 15:55:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097319; cv=none; b=KRmFoerTiYjz8GtiNX+jvJ2nEiAgqLX5i+A5W2Prhy7JlDkNA5ELlHM/IDTxFLqGI0iBuvXIYk51rDe+sqakpwqr2RlWba3Y9rc8ZgWFfPKaV4aGvHd0WIykfsGu6gMVpua/0CKjT7hNW3UYUI2amnEBS2dc7AqP80ADQYQVkTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097319; c=relaxed/simple; bh=5ugYS7mcYB39rdTwhNSLO9uUY7hLn18BmFVRM+d5dFc=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=AmATzR5jqlAg/AfdaQWhdymUpl6UiNLrXBS0PuX8OjChydQh20KXXl5okuYis0XgdX3xguaUFpTeQqHk2qz//c1Sn9+907oCC3r4IzwLhoRSS7lCvkfBy+A4go1Gn48ISZ6Do+lzhLHgivhDHPij1ksciGdzbevD+BPVXDI3fNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=2Yuhlqfs; arc=none smtp.client-ip=209.85.128.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="2Yuhlqfs" Received: by mail-wm1-f73.google.com with SMTP id 5b1f17b1804b1-41ab7cdccd2so13233615e9.1 for ; Tue, 07 May 2024 08:55:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1715097316; x=1715702116; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=40+Pm6zyt5X6n4Ns9MlN83kz/gWPVXV1Uvz0YKR00AQ=; b=2YuhlqfsDw2MJeM9cUsDKsTqNkdeLCMbJKGOzQqO7zRI1VrEpqsADBesrbZjUqMZyq +3mX8CUiqcUYcOBa0osOcovdjze2tFLEj1NELBjAbhE1Q9nFks5F4M3vBAPS0dgFc4wR /qUcvPcBO1Dlng9ACh4k3AqU+3dTl80uC0FzgqkU6a1GqrSNgNag+c01SRCb1HaF5xM5 6qPRKxxKCspjHUbz0KqT8d6prijFyZl7EvxsMFcMPRbtFUZ1RvcqjA+On5EbUWK0M+9+ APKkVDDsAbNHfIp7CwWWqLCg+eX3MX7KR8fO7/+xFEOX9t55vh8rUnFlOZd4heSZCqJl EATA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715097316; x=1715702116; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=40+Pm6zyt5X6n4Ns9MlN83kz/gWPVXV1Uvz0YKR00AQ=; b=mP3xuqOPTxSq/9uIptqukNCUYhEcTd1UJpd3Z8+1kLsfIRayz9X/9qZ2NSDY0KKwu/ YEpdkeqfkrq2QFqMkPFDaA/71Z6T3AZvADzwDDr4oIaEbXrNF0A+L8UXZ9u9UlxNvmHr w0g+Va9izPaJ24R45BcBgoT2fFPDuVwU+AMU3rM6mBDMg1WI7U1OFsJ5Ov8r7NhhNMoQ TqX24JdDaSZyMwqYr9nnnpcBKES/P+59yZV9ZhAC+xs2DP/DrWWsqmkg2jN6Wg3z3hp8 nEdklrJBkrJzLYXx0HtOUGkVqtmFZh9Dxk3W3EIwuoXfwSrEuZ4AUH2/XK5IWM8Y05n9 tiaA== X-Forwarded-Encrypted: i=1; AJvYcCVhz22cbcvXUAAa+BeGmbhbXvQizScN8yF35V9ivfKBpGGl3eUy0T0YAREhuzqmT9NGQXS1VFdzdEzDq5xPJhQkOoV2dUi22TDtUpw= X-Gm-Message-State: AOJu0Yxu9Cds5DPsvvfU7Oh4o7y6W7GhuSrypYyZGkrNpaVQ7b3413jD q5/vS/2s7wmdwsskQ3rx1Hns9K8cKf8/BWRZNlp3X3h2JDYJiaBuiVF7rVFakthCb3icrr5eagx dfUJvdpGrPQ== X-Google-Smtp-Source: AGHT+IF/5zSOo21MvZ154VSfD/SVvXl6RXiUdoc/sdkw9vF99qGVCLv+fog+PM7u+XdwnhS55cvGs0/dve3sQg== X-Received: from szatan.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:2d83]) (user=panikiel job=sendgmr) by 2002:a05:600c:2108:b0:41c:97e:20fc with SMTP id 5b1f17b1804b1-41f723a0969mr4115e9.3.1715097316211; Tue, 07 May 2024 08:55:16 -0700 (PDT) Date: Tue, 7 May 2024 15:54:06 +0000 In-Reply-To: <20240507155413.266057-1-panikiel@google.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240507155413.266057-1-panikiel@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240507155413.266057-4-panikiel@google.com> Subject: [PATCH v3 03/10] lib: Move DisplayPort CRC functions to common lib From: " =?utf-8?q?Pawe=C5=82_Anikiel?= " To: airlied@gmail.com, akpm@linux-foundation.org, conor+dt@kernel.org, daniel@ffwll.ch, dinguyen@kernel.org, hverkuil-cisco@xs4all.nl, krzysztof.kozlowski+dt@linaro.org, maarten.lankhorst@linux.intel.com, mchehab@kernel.org, mripard@kernel.org, robh+dt@kernel.org, tzimmermann@suse.de Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, chromeos-krk-upstreaming@google.com, " =?utf-8?q?Pawe=C5=82_Anikiel?= " The CRC functions found in drivers/gpu/drm/display/drm_dp_mst_topology.c may be useful for other non-DRM code that deals with DisplayPort, e.g. v4l2 drivers for DP receivers. Move these functions to /lib. Signed-off-by: Paweł Anikiel --- drivers/gpu/drm/display/Kconfig | 1 + drivers/gpu/drm/display/drm_dp_mst_topology.c | 76 ++---------------- include/linux/crc-dp.h | 10 +++ lib/Kconfig | 8 ++ lib/Makefile | 1 + lib/crc-dp.c | 78 +++++++++++++++++++ 6 files changed, 103 insertions(+), 71 deletions(-) create mode 100644 include/linux/crc-dp.h create mode 100644 lib/crc-dp.c diff --git a/drivers/gpu/drm/display/Kconfig b/drivers/gpu/drm/display/Kconfig index c0f56888c328..eda19645201d 100644 --- a/drivers/gpu/drm/display/Kconfig +++ b/drivers/gpu/drm/display/Kconfig @@ -14,6 +14,7 @@ config DRM_DISPLAY_HELPER config DRM_DISPLAY_DP_HELPER bool depends on DRM_DISPLAY_HELPER + select CRC_DP help DRM display helpers for DisplayPort. diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 03d528209426..54ba98d3bc6f 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -195,73 +196,6 @@ drm_dp_mst_rad_to_str(const u8 rad[8], u8 lct, char *out, size_t len) } /* sideband msg handling */ -static u8 drm_dp_msg_header_crc4(const uint8_t *data, size_t num_nibbles) -{ - u8 bitmask = 0x80; - u8 bitshift = 7; - u8 array_index = 0; - int number_of_bits = num_nibbles * 4; - u8 remainder = 0; - - while (number_of_bits != 0) { - number_of_bits--; - remainder <<= 1; - remainder |= (data[array_index] & bitmask) >> bitshift; - bitmask >>= 1; - bitshift--; - if (bitmask == 0) { - bitmask = 0x80; - bitshift = 7; - array_index++; - } - if ((remainder & 0x10) == 0x10) - remainder ^= 0x13; - } - - number_of_bits = 4; - while (number_of_bits != 0) { - number_of_bits--; - remainder <<= 1; - if ((remainder & 0x10) != 0) - remainder ^= 0x13; - } - - return remainder; -} - -static u8 drm_dp_msg_data_crc4(const uint8_t *data, u8 number_of_bytes) -{ - u8 bitmask = 0x80; - u8 bitshift = 7; - u8 array_index = 0; - int number_of_bits = number_of_bytes * 8; - u16 remainder = 0; - - while (number_of_bits != 0) { - number_of_bits--; - remainder <<= 1; - remainder |= (data[array_index] & bitmask) >> bitshift; - bitmask >>= 1; - bitshift--; - if (bitmask == 0) { - bitmask = 0x80; - bitshift = 7; - array_index++; - } - if ((remainder & 0x100) == 0x100) - remainder ^= 0xd5; - } - - number_of_bits = 8; - while (number_of_bits != 0) { - number_of_bits--; - remainder <<= 1; - if ((remainder & 0x100) != 0) - remainder ^= 0xd5; - } - - return remainder & 0xff; -} static inline u8 drm_dp_calc_sb_hdr_size(struct drm_dp_sideband_msg_hdr *hdr) { u8 size = 3; @@ -284,7 +218,7 @@ static void drm_dp_encode_sideband_msg_hdr(struct drm_dp_sideband_msg_hdr *hdr, (hdr->msg_len & 0x3f); buf[idx++] = (hdr->somt << 7) | (hdr->eomt << 6) | (hdr->seqno << 4); - crc4 = drm_dp_msg_header_crc4(buf, (idx * 2) - 1); + crc4 = crc_dp_msg_header(buf, (idx * 2) - 1); buf[idx - 1] |= (crc4 & 0xf); *len = idx; @@ -305,7 +239,7 @@ static bool drm_dp_decode_sideband_msg_hdr(const struct drm_dp_mst_topology_mgr len += ((buf[0] & 0xf0) >> 4) / 2; if (len > buflen) return false; - crc4 = drm_dp_msg_header_crc4(buf, (len * 2) - 1); + crc4 = crc_dp_msg_header(buf, (len * 2) - 1); if ((crc4 & 0xf) != (buf[len - 1] & 0xf)) { drm_dbg_kms(mgr->dev, "crc4 mismatch 0x%x 0x%x\n", crc4, buf[len - 1]); @@ -725,7 +659,7 @@ static void drm_dp_crc_sideband_chunk_req(u8 *msg, u8 len) { u8 crc4; - crc4 = drm_dp_msg_data_crc4(msg, len); + crc4 = crc_dp_msg_data(msg, len); msg[len] = crc4; } @@ -782,7 +716,7 @@ static bool drm_dp_sideband_append_payload(struct drm_dp_sideband_msg_rx *msg, if (msg->curchunk_idx >= msg->curchunk_len) { /* do CRC */ - crc4 = drm_dp_msg_data_crc4(msg->chunk, msg->curchunk_len - 1); + crc4 = crc_dp_msg_data(msg->chunk, msg->curchunk_len - 1); if (crc4 != msg->chunk[msg->curchunk_len - 1]) print_hex_dump(KERN_DEBUG, "wrong crc", DUMP_PREFIX_NONE, 16, 1, diff --git a/include/linux/crc-dp.h b/include/linux/crc-dp.h new file mode 100644 index 000000000000..b63435c82b96 --- /dev/null +++ b/include/linux/crc-dp.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_CRC_DP_H +#define _LINUX_CRC_DP_H + +#include + +u8 crc_dp_msg_header(const uint8_t *data, size_t num_nibbles); +u8 crc_dp_msg_data(const uint8_t *data, u8 number_of_bytes); + +#endif /* _LINUX_CRC_DP_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 4557bb8a5256..d2836dacf10d 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -168,6 +168,14 @@ config CRC_ITU_T the kernel tree does. Such modules that use library CRC ITU-T V.41 functions require M here. +config CRC_DP + tristate "CRC DisplayPort MST functions" + help + This option is provided for the case where no in-kernel-tree + modules require CRC DisplayPort MST functions, but a module built outside + the kernel tree does. Such modules that use library CRC DisplayPort MST + functions require M here. + config CRC32 tristate "CRC32/CRC32c functions" default y diff --git a/lib/Makefile b/lib/Makefile index ffc6b2341b45..82edf655036b 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -186,6 +186,7 @@ obj-$(CONFIG_CRC7) += crc7.o obj-$(CONFIG_LIBCRC32C) += libcrc32c.o obj-$(CONFIG_CRC8) += crc8.o obj-$(CONFIG_CRC64_ROCKSOFT) += crc64-rocksoft.o +obj-$(CONFIG_CRC_DP) += crc-dp.o obj-$(CONFIG_XXHASH) += xxhash.o obj-$(CONFIG_GENERIC_ALLOCATOR) += genalloc.o diff --git a/lib/crc-dp.c b/lib/crc-dp.c new file mode 100644 index 000000000000..95b58bc436d4 --- /dev/null +++ b/lib/crc-dp.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +/* + * Sideband MSG Header CRC + * Defined in DisplayPort 1.2 spec, section 2.11.3.1.9 + */ +u8 crc_dp_msg_header(const uint8_t *data, size_t num_nibbles) +{ + u8 bitmask = 0x80; + u8 bitshift = 7; + u8 array_index = 0; + int number_of_bits = num_nibbles * 4; + u8 remainder = 0; + + while (number_of_bits != 0) { + number_of_bits--; + remainder <<= 1; + remainder |= (data[array_index] & bitmask) >> bitshift; + bitmask >>= 1; + bitshift--; + if (bitmask == 0) { + bitmask = 0x80; + bitshift = 7; + array_index++; + } + if ((remainder & 0x10) == 0x10) + remainder ^= 0x13; + } + + number_of_bits = 4; + while (number_of_bits != 0) { + number_of_bits--; + remainder <<= 1; + if ((remainder & 0x10) != 0) + remainder ^= 0x13; + } + + return remainder; +} + +/* + * Sideband MSG Data CRC + * Defined in DisplayPort 1.2 spec, section 2.11.3.2.2 + */ +u8 crc_dp_msg_data(const uint8_t *data, u8 number_of_bytes) +{ + u8 bitmask = 0x80; + u8 bitshift = 7; + u8 array_index = 0; + int number_of_bits = number_of_bytes * 8; + u16 remainder = 0; + + while (number_of_bits != 0) { + number_of_bits--; + remainder <<= 1; + remainder |= (data[array_index] & bitmask) >> bitshift; + bitmask >>= 1; + bitshift--; + if (bitmask == 0) { + bitmask = 0x80; + bitshift = 7; + array_index++; + } + if ((remainder & 0x100) == 0x100) + remainder ^= 0xd5; + } + + number_of_bits = 8; + while (number_of_bits != 0) { + number_of_bits--; + remainder <<= 1; + if ((remainder & 0x100) != 0) + remainder ^= 0xd5; + } + + return remainder & 0xff; +} From patchwork Tue May 7 15:54:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 795390 Received: from mail-wr1-f74.google.com (mail-wr1-f74.google.com [209.85.221.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 478ED168B19 for ; Tue, 7 May 2024 15:55:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097323; cv=none; b=PAU/78/slW69dUE0L2pW1e6jI68m1ZuJpM02Ba0ymz6/aqsdZNuU7PUx6OyTBEgmPmDwcbOqM/yFg7NpxUdiZN27+MK/tEGaHvrdbJup1rhQXg2a4NqDPy6mi1jwBWCen77Dwo5D1wWEbfbv9RP19ECwCCSOyqNqjVnTi0c6dpM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097323; c=relaxed/simple; bh=qIz58J9D08HEDbRnnXnEvA94us7AQDo0d2kZB+Mdj40=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=KmCpIaV219Mf5Y1OpgPcEskfONkHzkEaJqY8EjRuCo1Gcald1aBlAe9mn0h4P7qxLoMGbJkjY6pJJ8Z/Bo5kLFmY/hqSbzF13uJTze6ltKPkvWpLz5zauMMwTtIKqNoHh0QzMaVCGHmI2/60lCjqD+C6pBJ3DcnkyDgn1Jt1b14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=N9cyq3CQ; arc=none smtp.client-ip=209.85.221.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="N9cyq3CQ" Received: by mail-wr1-f74.google.com with SMTP id ffacd0b85a97d-34dd570f48cso2037915f8f.3 for ; Tue, 07 May 2024 08:55:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1715097321; x=1715702121; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=ENm7dGdRCegViXpKOlFOwQirdvQpMHKuwbsV2GUz3rE=; b=N9cyq3CQJy3fi/exqKi9OitPCwx9QKdlWuqzjZdXQ3R6OmMC64JoXHbvXpg4mqA9MK +1ihrfxoV7T2HK6tfA2aUeCqoQPkRR2WLVI9Pgm7HirT7sgPm8IvLTtdc0E0xAi25Bop 19jGbiMK9JB3jTY5ncUhFzW6CE+h/lFp6iKyDLzFPBbZ8E8LY2tmT7Mg2GWZwssJB/vQ clAKgcmGCw8L9Uat8/C52EEyecbu1kX+DGFzC93SFo3Ev3kZ4Nw1gGiMYlOUtoiZogqK FyuDr4696/htDJxEMQ9btgZwdtvlNkEcNqYNtwO/wWOOvot0DG7w4ltRQbz8YlEOZ/s/ r6Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715097321; x=1715702121; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=ENm7dGdRCegViXpKOlFOwQirdvQpMHKuwbsV2GUz3rE=; b=Yry//yAp5MdRmUb8RNPCYYLJNmVDCtnl4zi/NzZb+qbiIvbOJoeue+BVMC/wNalrVW hIslu9WXAIqRzOV2Ws6021FFKquppZbL/ZpzYD7MEhgj6LeNmbXZSS+/KP1UGwV1il/q +OtRh2506t1bD1qncy6VSl/00oFJEbdqx48WQQVuBmWwZlRb9IWdOKo4f9ZMuzNuwMBK 2xOTr+DcJ/KwIkcWX2hnBreeYOrPA9HXslexsw0rToR9sfPTPuNm3KqvgihX7XPYgNh9 rbPJ83FO9VD+9sc/7/ZzhHWWRfCOVQEgNEp/+zmS5rKYHTxpm7pAoPi9F8Qhop5pgGM7 pCkw== X-Forwarded-Encrypted: i=1; AJvYcCVPlths+s+AfAPWA/zgNiNofkjHx9CwHIivrkcIKfo7XopW/GVjYrjLffkddh+pme288S5Q15jwamsTqIpjbaL7dtcOJSOCbrnLG1g= X-Gm-Message-State: AOJu0YybEGX4aDCxiVTdTPA2sBHwwCsaNflf/Lg+2OWE4M58Rthm4FC7 oNODSmH00kgcOISuYykDL9j3fCsjkeb2LT/EXtSbL2NMcpO2K33yFAQarLG8Oc/ER93Nq9M+5B0 mWeP9BpY+nA== X-Google-Smtp-Source: AGHT+IHGZ0yavujoh3USa9TPTOqVQ47cF03iCo0u4JgWlc3kP8zUzp3F+JtX/FYOC3mCEQ6JEWGwA5+DbsxNUw== X-Received: from szatan.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:2d83]) (user=panikiel job=sendgmr) by 2002:adf:ed83:0:b0:34c:d3c5:b12d with SMTP id ffacd0b85a97d-34fcb3aaef5mr233f8f.14.1715097320472; Tue, 07 May 2024 08:55:20 -0700 (PDT) Date: Tue, 7 May 2024 15:54:08 +0000 In-Reply-To: <20240507155413.266057-1-panikiel@google.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240507155413.266057-1-panikiel@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240507155413.266057-6-panikiel@google.com> Subject: [PATCH v3 05/10] media: dt-bindings: video-interfaces: Support DisplayPort MST From: " =?utf-8?q?Pawe=C5=82_Anikiel?= " To: airlied@gmail.com, akpm@linux-foundation.org, conor+dt@kernel.org, daniel@ffwll.ch, dinguyen@kernel.org, hverkuil-cisco@xs4all.nl, krzysztof.kozlowski+dt@linaro.org, maarten.lankhorst@linux.intel.com, mchehab@kernel.org, mripard@kernel.org, robh+dt@kernel.org, tzimmermann@suse.de Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, chromeos-krk-upstreaming@google.com, " =?utf-8?q?Pawe=C5=82_Anikiel?= " Add a DisplayPort bus type and a multi-stream-support property indicating whether the interface supports MST. Signed-off-by: Paweł Anikiel Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/media/video-interfaces.yaml | 7 +++++++ include/dt-bindings/media/video-interfaces.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/media/video-interfaces.yaml b/Documentation/devicetree/bindings/media/video-interfaces.yaml index 26e3e7d7c67b..7bf3a2c09a5b 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.yaml +++ b/Documentation/devicetree/bindings/media/video-interfaces.yaml @@ -94,6 +94,7 @@ properties: - 5 # Parallel - 6 # BT.656 - 7 # DPI + - 8 # DisplayPort description: Data bus type. @@ -217,4 +218,10 @@ properties: Whether the clock signal is used as clock (0) or strobe (1). Used with CCP2, for instance. + multi-stream-support: + type: boolean + description: + Support transport of multiple independent streams. Used for + DisplayPort MST-capable interfaces. + additionalProperties: true diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h index 68ac4e05e37f..b236806f4482 100644 --- a/include/dt-bindings/media/video-interfaces.h +++ b/include/dt-bindings/media/video-interfaces.h @@ -12,5 +12,7 @@ #define MEDIA_BUS_TYPE_CSI2_DPHY 4 #define MEDIA_BUS_TYPE_PARALLEL 5 #define MEDIA_BUS_TYPE_BT656 6 +#define MEDIA_BUS_TYPE_DPI 7 +#define MEDIA_BUS_TYPE_DISPLAYPORT 8 #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ From patchwork Tue May 7 15:54:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 795389 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3987E16D4F2 for ; Tue, 7 May 2024 15:55:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097329; cv=none; b=OnPlwEgPmbUn0DdSrzPqQ8JsRcJ/vkLF9UEFL4+0Rh9VtX9SP3JZJZS9L3dcFu907ON/poNlnrg9HiBHcircSmCWEYU+vUUD99pjVogHUxcsVQDzY/fMhgHeVkqEYFIHdpDu42it0wiRS6NBOmbs2p0ool8lT52/IxC6PiAjdp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097329; c=relaxed/simple; bh=lj3Uuvfbi3ogaJj1SEB5/Jfxuor2q0oFT4UvFLlqcuQ=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=pVsnUYAaurz1SLsMLB5QiH5D59Fe+1P+kG0qdmZ1RHcx58Hz8DlacsZsP9XLoe0FGLL+oKyEl+uEMxEHURCG3fdq+OHzwXGjtduXZLNtZqIVHoxbimqYr4xMy39LiF9iH5FdkxxprMs7AYhHKdt5brNNjIEvB76OI11OVecH0bQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=HpAA+kgj; arc=none smtp.client-ip=209.85.219.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="HpAA+kgj" Received: by mail-yb1-f201.google.com with SMTP id 3f1490d57ef6-de60cd96bf3so7438639276.0 for ; Tue, 07 May 2024 08:55:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1715097327; x=1715702127; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=YyhwXzsTi3iuS9VxYlKBJB4yY1r1RWRn/sVpGYW4xm0=; b=HpAA+kgjZ28e5uUu9/K1CjDZVmc2jF5NaQ7Y/BiRUjr6OWPoXCSxwpNQdJB0afPWrc 73htNL+ZsVu/w/IhRbO1eepjbLPqpDohGCTibcx8leKmq3aQ6qyzA9C2T9nx0GK2exEv K+3kEM5F91hIXE72uck2+opIpsawARNrfiv1X0rzPSGE7fd1QyDnbQgwBXbIw52BjlFk oV0enIFyjztTfWollok5QQjbpBXqRGbpoAsUBQhalC0JPpPSoCI7aNhu8mXWZ+u+h0Ec xxkrKo5vWpJ/O71OBiYRbqGA/R7V74r/CqcouytB0CCNlr78btHqg1Zi3hgkEImO4ots kOfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715097327; x=1715702127; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=YyhwXzsTi3iuS9VxYlKBJB4yY1r1RWRn/sVpGYW4xm0=; b=CbjqqxGdHi7wTfSUD37aZf4MA4OGs0PbMP/ovVDYF6XOtdJqDDCwZkmzP2/lcyGuSy wXvpuiY0FCx5j8petIUjAaXPMYP87TzTBaR2W1k598R6BM8WSAQ/F6wLJe+dhttcihTB mPnpjngJTwNpcn/gEYhGZgc7qmHGmcClk15LELfgmV12pmaZNA7cuYA8YCFQ2yKRLGbp gIotVfQQiCX2uwo6IPZawiK1K3eqNLlnOJsfhH8AxPrzgfbhUaduT+H0FkT3fjh3TxrS k3+IFK9nHDI90EyRoqcMNz/vE2JoJjzRfJllUPnQsDjP9ZLw6YHrK7vrcVGMFoP22zdS FIGg== X-Forwarded-Encrypted: i=1; AJvYcCUOIVFU4/BBO1LLRlwQ0e8Wtp+UDOq8LoR6DWEMFfcxf+h4tldlL0ZsnKcBV8Wy6M/hbeq2kLrzmBzhmB4VlzJROTkZuLhh1HBdoFo= X-Gm-Message-State: AOJu0YzmMyI6oc18x8YyG63z49dwjWDZQ3Tz5SxsVh7deR6+xkB4CBbA /2Hmj4HlnCGSxZo/N1hvSdFhXKN8TsKrQvWF4nlgiipxSbS41w8CLNUzKRv605/Pf1bPFzqL+Sy wfiacfdN0zA== X-Google-Smtp-Source: AGHT+IFXr71F6VzIV2IWcHBSYr3WsXCqqHZWMEiC5DuDYmkkVHWrNMTCKBa7KJNHIvxEbrt1NsffE8mdi7jzMQ== X-Received: from szatan.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:2d83]) (user=panikiel job=sendgmr) by 2002:a25:ed0d:0:b0:de5:a77e:f9bd with SMTP id 3f1490d57ef6-deba36c73bamr692217276.6.1715097327282; Tue, 07 May 2024 08:55:27 -0700 (PDT) Date: Tue, 7 May 2024 15:54:11 +0000 In-Reply-To: <20240507155413.266057-1-panikiel@google.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240507155413.266057-1-panikiel@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240507155413.266057-9-panikiel@google.com> Subject: [PATCH v3 08/10] media: dt-bindings: Add Chameleon v3 video interface From: " =?utf-8?q?Pawe=C5=82_Anikiel?= " To: airlied@gmail.com, akpm@linux-foundation.org, conor+dt@kernel.org, daniel@ffwll.ch, dinguyen@kernel.org, hverkuil-cisco@xs4all.nl, krzysztof.kozlowski+dt@linaro.org, maarten.lankhorst@linux.intel.com, mchehab@kernel.org, mripard@kernel.org, robh+dt@kernel.org, tzimmermann@suse.de Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, chromeos-krk-upstreaming@google.com, " =?utf-8?q?Pawe=C5=82_Anikiel?= " Add dt binding for the video interface present on the Google Chameleon v3. The Chameleon v3 uses the video interface to capture a single video source from a given HDMI or DP connector and write the resulting frames to memory. Signed-off-by: Paweł Anikiel Reviewed-by: Rob Herring (Arm) --- .../bindings/media/google,chv3-video.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/google,chv3-video.yaml diff --git a/Documentation/devicetree/bindings/media/google,chv3-video.yaml b/Documentation/devicetree/bindings/media/google,chv3-video.yaml new file mode 100644 index 000000000000..b8380021cd23 --- /dev/null +++ b/Documentation/devicetree/bindings/media/google,chv3-video.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/google,chv3-video.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Chameleon v3 video interface + +maintainers: + - Paweł Anikiel + +properties: + compatible: + enum: + - google,chv3-video-it-1.0 + - google,chv3-video-dp-1.0 + + reg: + items: + - description: core registers + - description: irq registers + + interrupts: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Connection to the video receiver - optional. If this isn't present, + the video interface still works on its own, but EDID control is + unavailable and DV timing information only reports the active + video width/height. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + video@c0060500 { + compatible = "google,chv3-video-it-1.0"; + reg = <0xc0060500 0x100>, + <0xc0060f20 0x10>; + interrupts = ; + }; + + - | + video@c0060600 { + compatible = "google,chv3-video-dp-1.0"; + reg = <0xc0060600 0x100>, + <0xc0060f30 0x10>; + interrupts = ; + + port { + video_mst0_0: endpoint { + remote-endpoint = <&dprx_mst_0>; + }; + }; + }; From patchwork Tue May 7 15:54:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Pawe=C5=82_Anikiel?= X-Patchwork-Id: 795388 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8966116D9BA for ; Tue, 7 May 2024 15:55:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097332; cv=none; b=jf7hhiR7MD2Roe85p6Y4DaWYqrz/FJJ+kC3OJoS/JJ37Oq/h0Ijy77iDDoi7/EixilFkCFfdpeTx0s6AE8Xg3dfQaqWLE5z5FukwWU3om8flrmBllPk5KKi7UoOGi05Mv3Q67E5pJBPfhrksJlvHNJtd18Db3GIB8QYEhdV0gPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715097332; c=relaxed/simple; bh=5GcCSNxUB2nNT9lCSh3AsMpAmCe/+f8zkisiEdAT35g=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Y4m//IT6JmH43YI7ng5ZN4KPCPM2DgQBYdxT1LrbTiYHkTCnD7ySNlLboYGFBS+0Dws1KqlgNcxsVWGmu+iXS5bp7PuS4B9tV1v32G3KM8Hx07i207TLtSPnRFSxXsvuF42u16Lz2+9Gf/GQOv5ovL0h/gybep9vxPx9BheFIO8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=mjs29lxO; arc=none smtp.client-ip=209.85.219.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--panikiel.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="mjs29lxO" Received: by mail-yb1-f202.google.com with SMTP id 3f1490d57ef6-dbf618042daso6367274276.0 for ; Tue, 07 May 2024 08:55:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1715097329; x=1715702129; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=4Zg5aDDMOyqW00delol8Ca3GL2MBNFcyQ9gNrBCTWcU=; b=mjs29lxOy2t5vtKl2r+ttbjlF8d2YaZQlsbA9ycYxuedbA34Tkw8Ji2Yit0HLCi+fe j4Tep37l0fnA5FVVY1JMY8ha5gL+6uRd4yoQ1dHJEjZ2kPXml0wA/Q8O0x2pSN47rh0C dpTqnVe+q+8AMGSegaI/d5Sww9rZ/51a/A4+bpVEjce4xZ094ArH1elyDB+CyYlR1ZlN EAkLYqSCBRX53oyd4jjnmXd5QRJaEDp7kALM9SRzNS2pWqkw/eBu1TW2O5KScbapE3hp Y+0m+NcjdqvO5EjNIqCyjZjpJ64y0tFfu1NLDep+EF9pc6lgjIHlyN4T5B96Uv9xDdoa g5TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715097329; x=1715702129; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=4Zg5aDDMOyqW00delol8Ca3GL2MBNFcyQ9gNrBCTWcU=; b=owTWVPi4r7lmWWyRlPRQ+4+k47agi/ZugmxyEZdG/nfZRQTl5pboxQruAZHnGFKGx0 VCSgzxDzisiuNdFXVGmT1IYh/KM6YFZVLUmIPsNpk90c+/oXhNOxOfSSmgDtxesyB4re MrfjyECajyojoOpXvox29a+E+k42RuKVjiq+Tw8SGOHt3MO+breJuS8xg31pMAAqCDqm +Q68PnkqSxErEsNWA4gyX2V8/lgFA3t/50d0CxCNHHGlP4Uhsu67TCKPAHYMsHwrKj0P bHVXSf8zURJoLarNpeZGrUgOqS8Jv1u0oGghk+lBFGqnNZalHzvGISibzidpoESMWHo9 y+UQ== X-Forwarded-Encrypted: i=1; AJvYcCWuWuyn1VzsgaVcILq4z3yVdvJijDg0+3EsnYMSUOmULLzjE1bHswyz2N9bT0XiMIhW0M69HUhk6fI6Togn6T+a/A2BqXpcF2pQM8w= X-Gm-Message-State: AOJu0YxyiOCnYenzLJ9UO3w4hhCNhNhLbBaw32JVdf6jOqSesUuxY9hc Ll4WWrDQ3SLP+IGfCq3b0H8oSSus9WTbi1UE/f2coFGJDUpZiufXN653tEz4kRFDBDW/J5D5hPj kbXya9bJnBA== X-Google-Smtp-Source: AGHT+IFl69D5om/H+B54ETJ2PMG3nixPpLSKdXlaMOhDwBY7IXqpN0xGnNqZTl237/xQEoI2pJqnIU8A60Nk+w== X-Received: from szatan.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:2d83]) (user=panikiel job=sendgmr) by 2002:a05:6902:1007:b0:dd1:38ec:905d with SMTP id 3f1490d57ef6-debb9e0bdeemr176276.11.1715097329468; Tue, 07 May 2024 08:55:29 -0700 (PDT) Date: Tue, 7 May 2024 15:54:12 +0000 In-Reply-To: <20240507155413.266057-1-panikiel@google.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240507155413.266057-1-panikiel@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240507155413.266057-10-panikiel@google.com> Subject: [PATCH v3 09/10] media: dt-bindings: Add Intel Displayport RX IP From: " =?utf-8?q?Pawe=C5=82_Anikiel?= " To: airlied@gmail.com, akpm@linux-foundation.org, conor+dt@kernel.org, daniel@ffwll.ch, dinguyen@kernel.org, hverkuil-cisco@xs4all.nl, krzysztof.kozlowski+dt@linaro.org, maarten.lankhorst@linux.intel.com, mchehab@kernel.org, mripard@kernel.org, robh+dt@kernel.org, tzimmermann@suse.de Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, chromeos-krk-upstreaming@google.com, " =?utf-8?q?Pawe=C5=82_Anikiel?= " Add dt binding for the Intel Displayport receiver FPGA IP. It is a part of the DisplayPort Intel FPGA IP Core, and supports DisplayPort 1.4, HBR3 video capture and Multi-Stream Transport. The user guide can be found here: https://www.intel.com/programmable/technical-pdfs/683273.pdf Signed-off-by: Paweł Anikiel --- .../devicetree/bindings/media/intel,dprx.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/intel,dprx.yaml diff --git a/Documentation/devicetree/bindings/media/intel,dprx.yaml b/Documentation/devicetree/bindings/media/intel,dprx.yaml new file mode 100644 index 000000000000..01bed858f746 --- /dev/null +++ b/Documentation/devicetree/bindings/media/intel,dprx.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/intel,dprx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel DisplayPort RX IP + +maintainers: + - Paweł Anikiel + +description: | + The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP + Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video + capture and Multi-Stream Transport. + + The IP features a large number of configuration parameters, found at: + https://www.intel.com/content/www/us/en/docs/programmable/683273/23-3-20-0-1/sink-parameters.html + + The following parameters have to be enabled: + - Support DisplayPort sink + - Enable GPU control + The following parameters have to be set in the devicetree: + - RX maximum link rate (using link-frequencies) + - Maximum lane count (using data-lanes) + - Support MST (using multi-stream-support) + - Max stream count (inferred from the number of ports) + +properties: + compatible: + const: intel,dprx-20.0.1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: MST virtual channel 0 or SST main link + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + + properties: + link-frequencies: true + + data-lanes: + minItems: 1 + maxItems: 4 + + multi-stream-support: true + + required: + - data-lanes + - link-frequencies + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 0 or SST main link + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 1 + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 2 + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 3 + + +required: + - compatible + - reg + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include + + dp-receiver@c0062000 { + compatible = "intel,dprx-20.0.1"; + reg = <0xc0062000 0x800>; + interrupt-parent = <&dprx_mst_irq>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dprx_mst_in: endpoint { + remote-endpoint = <&dp_input_mst_0>; + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 + 5400000000 8100000000>; + multi-stream-support; + }; + }; + + port@1 { + reg = <1>; + dprx_mst_0: endpoint { + remote-endpoint = <&video_mst0_0>; + }; + }; + + port@2 { + reg = <2>; + dprx_mst_1: endpoint { + remote-endpoint = <&video_mst1_0>; + }; + }; + + port@3 { + reg = <3>; + dprx_mst_2: endpoint { + remote-endpoint = <&video_mst2_0>; + }; + }; + + port@4 { + reg = <4>; + dprx_mst_3: endpoint { + remote-endpoint = <&video_mst3_0>; + }; + }; + }; + }; + + - | + dp-receiver@c0064000 { + compatible = "intel,dprx-20.0.1"; + reg = <0xc0064000 0x800>; + interrupt-parent = <&dprx_sst_irq>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dprx_sst_in: endpoint { + remote-endpoint = <&dp_input_sst_0>; + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 + 5400000000 8100000000>; + }; + }; + + port@1 { + reg = <1>; + dprx_sst_0: endpoint { + remote-endpoint = <&video_sst_0>; + }; + }; + }; + };