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Sat, 11 May 2024 15:04:10 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d878fsm1123875e87.206.2024.05.11.15.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 May 2024 15:04:09 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:07 +0300 Subject: [PATCH v4 1/9] dt-bindings: clk: qcom,dispcc-sm8x50: describe additional DP clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240512-typec-fix-sm8250-v4-1-ad153c747a97@linaro.org> References: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> In-Reply-To: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2305; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Pl/YNaCowSJwtvM5CLxzriI2N0LVr+hVT798TnH3gks=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmP+tXp0Q5GwpORS+iXqTB5ajH8osXG5Ezc0mES IOnbKfLsZSJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj/rVwAKCRCLPIo+Aiko 1RZbB/9jfNSvkrAiw3FfSqlT7aAyrEiQRJI/7aZT73ThY08D9L8FFb8NDFAcOcZ3/+053LXmFG+ 7Q442pF4cmedrD8wYwP3gFja36hQ9tkKQM6yGvG0Hv5fZm9l1rhA2TPWYZZEeGv+1K5mKmY/L96 e2YRvo1w4VJYmnKtThuFlqakeBXsRjIc3xGq928b+yjpsl6yR1hmMsP6yuYJU2b19mzlaHbMqfQ SmM3zfh1gDpOF69ODUM/GRk3Nj2Vs5eXlQ/9o6Sf/WPLsZfTovepUjeKXwDTzUzOvHT6tJP/VmG vjvVve7M2ka3tZg4hBSZ/drWzqx4onBz/mCErRXDBej7DjMt X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A On the affected Qualcomm platforms the display clock controller has additional DP input clocks, describe them in DT schema. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 59cc88a52f6b..5831579b572e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -27,6 +27,7 @@ properties: - qcom,sm8350-dispcc clocks: + minItems: 7 items: - description: Board XO source - description: Byte clock from DSI PHY0 @@ -35,8 +36,15 @@ properties: - description: Pixel clock from DSI PHY1 - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY + - description: Link clock from eDP PHY + - description: VCO DIV clock from eDP PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Link clock from DP2 PHY + - description: VCO DIV clock from DP2 PHY clock-names: + minItems: 7 items: - const: bi_tcxo - const: dsi0_phy_pll_out_byteclk @@ -45,6 +53,12 @@ properties: - const: dsi1_phy_pll_out_dsiclk - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk + - const: edp_phy_pll_link_clk + - const: edp_phy_pll_vco_div_clk + - const: dptx1_phy_pll_link_clk + - const: dptx1_phy_pll_vco_div_clk + - const: dptx2_phy_pll_link_clk + - const: dptx2_phy_pll_vco_div_clk '#clock-cells': const: 1 @@ -68,6 +82,20 @@ properties: A phandle to an OPP node describing required MMCX performance point. maxItems: 1 +allOf: + - if: + not: + properties: + compatible: + contains: + const: qcom,sc8180x-dispcc + then: + properties: + clocks: + maxItems: 7 + clock-names: + maxItems: 7 + required: - compatible - reg From patchwork Sat May 11 22:04:08 2024 Content-Type: text/plain; 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Sat, 11 May 2024 15:04:10 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d878fsm1123875e87.206.2024.05.11.15.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 May 2024 15:04:10 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:08 +0300 Subject: [PATCH v4 2/9] arm64: dts: qcom: sc8180x: correct dispcc clocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240512-typec-fix-sm8250-v4-2-ad153c747a97@linaro.org> References: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> In-Reply-To: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1954; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Jwd9rhQ0JDu40ZBPuVk2gO1cB7XlxbXe5F6OjmzPxEg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmP+tX6+qiXkBU0JXiWCdi7IxJlyO8ZsvLk4cU1 HGuVvpquWeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj/rVwAKCRCLPIo+Aiko 1Uz9B/wN/QlD9xubscmi2AT7q1HuAaHjNh11kLWGTwSK9za8pxSJW0O6M+LGibWZ37HQMFMto3h 9EbExutNm0oiYMmk7FhIu95e9Wg17c/GQN+/CwYKy8SNKIISCf2Cpq4/n+FgQd5B2RJ7NolqmAy hmjR2TEElD7KGmPQdtt+1rgSM+OHFxqeSIRPvqTSnPaTrum/rWZAF1rN0kwJffueb2kdNFtvbY5 tDnns93Xq8XMFmnmSNQyuYLtdhPeOj/XEttodJMQ/UOthp96zS35fUWP4h0ueNcdCa4r0tCm3hq uUcKaZ4QHByxKdwcVI04akyLjRIQx0DlEQpFftIvsu/UaGhj X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Correct the clocks being used by the display clock controller on the SC8180X platform (to match the schema): - Drop the sleep clock - Add DSI clocks - Reorder eDP / DP clocks This changes the order of clocks, however it should be noted that the clock list was neither correct nor followed the schema beforehand. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 067712310560..b92b6fb73057 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3308,21 +3308,27 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sc8180x-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>, - <&usb_sec_dpphy 0>, - <&usb_sec_dpphy 1>, <&edp_phy 0>, - <&edp_phy 1>; + <&edp_phy 1>, + <&usb_sec_dpphy 0>, + <&usb_sec_dpphy 1>; clock-names = "bi_tcxo", - "sleep_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", - "dptx1_phy_pll_link_clk", - "dptx1_phy_pll_vco_div_clk", "edp_phy_pll_link_clk", - "edp_phy_pll_vco_div_clk"; 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There is no 'role switch' signal between Type-C connector and the DWC3 USB controller. Rename endpoints to mention USB HS signal instead (this follows the example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and all PMIC GLINK platforms). Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index cd0db4f31d4a..44239d1e57e9 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1356,8 +1356,8 @@ &usb_1_dwc3 { usb-role-switch; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &usb_1_hsphy { @@ -1465,8 +1465,8 @@ ports { port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 41f117474872..3596dd328c31 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -659,8 +659,8 @@ ports { port@0 { reg = <0>; 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Sat, 11 May 2024 15:04:12 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d878fsm1123875e87.206.2024.05.11.15.04.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 May 2024 15:04:12 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:10 +0300 Subject: [PATCH v4 4/9] arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240512-typec-fix-sm8250-v4-4-ad153c747a97@linaro.org> References: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> In-Reply-To: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Add corresponding OF graph link. Reported-by: Luca Weiss Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 0ec473ceb3d2..d6c8c6c2eced 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3947,6 +3947,10 @@ port@0 { port@1 { reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss_out>; + }; }; port@2 { @@ -4225,8 +4229,24 @@ usb_1_dwc3: usb@a600000 { phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_1_dwc3_hs_out: endpoint {}; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; }; }; }; From patchwork Sat May 11 22:04:11 2024 Content-Type: text/plain; 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a=openpgp-sha256; l=7378; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=hVvfvlT0rTVoTQnAQO6OY0YYd59DO6aFyNFsg5mz/Js=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmP+tYNmwzw3jfHOdsMUIbalRCLS7pJ5F99GTaV v9KW7Uum7CJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj/rWAAKCRCLPIo+Aiko 1SN/B/4nObihuFgyMeA5OlhDW9VVXj1c0dyViz+Hll1bnheQURwcWj/MSCHBmrokPSwRgR96vMS SLzYAu0TZs1dvkw9ZjiNDqrXVEbQ25A2RnPf4kcRaxOYowGqxvM2R9narvuki8R6pllda6t6yuS 76Dhgf7yW5o+uNqRrO4lQrt6UoOVzV7W4mcp0jPJwPMQENgD1NwUORUzN6Av8pgntwbi2TVqAMF wrc+iS0nLq+ZU+fdQoseYnsmGn4y8q79AmeEAfS5MQXvVJlnhuhKOUAkxH11822yGGg0UD/LtpE 0QRhvCxJdC1WQSQG5J/l4w0ft67fwwoUOxsaT/smvBEjqsiF X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A To follow other Qualcomm platforms, update QMP USB+DP PHYs to use newer bindings rather than old bindings which had PHYs as subdevices. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 122 ++++++++++++---------------------- 1 file changed, 41 insertions(+), 81 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index b92b6fb73057..897c0f51a612 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -2511,28 +2512,25 @@ usb_sec_hsphy: phy@88e3000 { status = "disabled"; }; - usb_prim_qmpphy: phy@88e9000 { + usb_prim_qmpphy: phy@88e8000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x38>, - <0 0x088ea000 0 0x40>; - reg-names = "reg-base", "dp_com"; + reg = <0 0x088e8000 0 0x3000>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", - "ref_clk_src", "ref", - "com_aux"; + "com_aux", + "usb3_pipe"; + resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #phy-cells = <1>; status = "disabled"; @@ -2546,59 +2544,38 @@ port@0 { usb_prim_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_prim_qmpphy_usb_ss_in: endpoint {}; + }; + port@2 { reg = <2>; usb_prim_qmpphy_dp_in: endpoint {}; }; }; - - usb_prim_ssphy: usb3-phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_prim_phy_pipe_clk_src"; - }; - - usb_prim_dpphy: dp-phy@88ea200 { - reg = <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eaa00 0 0x200>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - }; }; usb_sec_qmpphy: phy@88ee000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; - reg = <0 0x088ee000 0 0x18c>, - <0 0x088ed000 0 0x10>, - <0 0x088ef000 0 0x40>; - reg-names = "reg-base", "dp_com"; + reg = <0 0x088ed000 0 0x3000>; + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", - "ref_clk_src", "ref", - "com_aux"; + "com_aux", + "usb3_pipe"; resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, <&gcc GCC_USB3_PHY_SEC_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #phy-cells = <1>; status = "disabled"; @@ -2612,37 +2589,18 @@ port@0 { usb_sec_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_sec_qmpphy_usb_ss_in: endpoint {}; + }; + port@2 { reg = <2>; usb_sec_qmpphy_dp_in: endpoint {}; }; }; - - usb_sec_ssphy: usb3-phy@88e9200 { - reg = <0 0x088ee200 0 0x200>, - <0 0x088ee400 0 0x200>, - <0 0x088eec00 0 0x218>, - <0 0x088ee600 0 0x200>, - <0 0x088ee800 0 0x200>, - <0 0x088eea00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_sec_phy_pipe_clk_src"; - }; - - usb_sec_dpphy: dp-phy@88ef200 { - reg = <0 0x088ef200 0 0x200>, - <0 0x088ef400 0 0x200>, - <0 0x088efa00 0 0x200>, - <0 0x088ef600 0 0x200>, - <0 0x088ef800 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - clock-output-names = "qmp_dptx1_phy_pll_link_clk", - "qmp_dptx1_phy_pll_vco_div_clk"; - }; }; system-cache-controller@9200000 { @@ -2711,7 +2669,7 @@ usb_prim_dwc3: usb@a600000 { iommus = <&apps_smmu 0x140 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; + phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; port { @@ -2768,7 +2726,7 @@ usb_sec_dwc3: usb@a800000 { iommus = <&apps_smmu 0x160 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; + phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; port { @@ -3086,9 +3044,10 @@ mdss_dp0: displayport-controller@ae90000 { assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; + assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - phys = <&usb_prim_dpphy>; + phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; @@ -3163,9 +3122,10 @@ mdss_dp1: displayport-controller@ae98000 { assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; - assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; + assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - phys = <&usb_sec_dpphy>; + phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; @@ -3312,12 +3272,12 @@ dispcc: clock-controller@af00000 { <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <&usb_prim_dpphy 0>, - <&usb_prim_dpphy 1>, + <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&edp_phy 0>, <&edp_phy 1>, - <&usb_sec_dpphy 0>, - <&usb_sec_dpphy 1>; + <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", From patchwork Sat May 11 22:04:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 797044 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F0C94F215 for ; Sat, 11 May 2024 22:04:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715465057; cv=none; b=RRMqOn9ahX2QLh9DlNYU7/31b6bWUv+ZhzEEiy+XLBcRBz2yDyn/TuloE1IDAYyGgkCiAyD5mNG5LD7gUbXHva56/C62gkBcMBUaQBmMV498G/ecfUE1OlqkwM22tT2wQXaVL2Qeedb5w9CGAwMNltJAgriwdVIgwU5ye9AAXME= ARC-Message-Signature: i=1; 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a=openpgp-sha256; l=5234; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=S9N9mh3qsGiXOgKkwEQkt0VVAuKxPDthH/EXJb68S6I=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmP+tYH+Bj46Zpzic2moUVpeMPRBQeGf2/cn1fJ c3QOIzrTWCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj/rWAAKCRCLPIo+Aiko 1ejtB/9peY6QCFOlRJJSXC/YuLjsVa1M90VEvcwV5EDLTC36UMRB++PEKw7cdYfdGuFfR9VNhy3 K/hl3W+Y64qyhzY2rsQPtbUf7NVZaKVkt/pCe/Ao/PPlVm4EfMYxnW07BFkj33co+RSZ2UXrul5 fYvwTpBSwUSKOhfAeyrDCWhzbqFxLUZ6IQfSq2BAJwmmhwFaQkZYhAokoqdSli4pAzsJRmG+078 5yTeJ+zXESPxUX84PDr2ZWaU8qwu3J3mZGp4oZ/km3d0s0xQLPilA66d4JdZW6kO5UAfEX2vtfr jnIV8lhkxqIBq9bz1bc503wRv/6xWbCqB3miRsipG77qTjH9 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by: Dmitry Baryshkov --- .../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 ++++---- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 20 +++++----- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 46 +++++++++++++++++++--- 3 files changed, 58 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 6af99116c715..5b226577f9d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -68,7 +68,7 @@ port@0 { reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_prim_role_switch>; + remote-endpoint = <&usb_prim_dwc3_hs>; }; }; @@ -103,7 +103,7 @@ port@0 { reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_sec_role_switch>; + remote-endpoint = <&usb_sec_dwc3_hs>; }; }; @@ -582,6 +582,10 @@ &usb_prim_dwc3 { dr_mode = "host"; }; +&usb_prim_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_prim_qmpphy_dp_in { remote-endpoint = <&mdss_dp0_out>; }; @@ -590,8 +594,8 @@ &usb_prim_qmpphy_out { remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_prim_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; +&usb_sec_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; }; &usb_sec_hsphy { @@ -619,10 +623,6 @@ &usb_sec_qmpphy_out { remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_sec_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_sec { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index bfee60c93ccc..65d923497a05 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -71,7 +71,7 @@ port@0 { reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_prim_role_switch>; + remote-endpoint = <&usb_prim_dwc3_hs>; }; }; @@ -106,7 +106,7 @@ port@0 { reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_sec_role_switch>; + remote-endpoint = <&usb_sec_dwc3_hs>; }; }; @@ -648,6 +648,10 @@ &usb_prim_dwc3 { dr_mode = "host"; }; +&usb_prim_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_prim_qmpphy_dp_in { remote-endpoint = <&mdss_dp0_out>; }; @@ -656,10 +660,6 @@ &usb_prim_qmpphy_out { remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_prim_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_sec_hsphy { vdda-pll-supply = <&vreg_l5e_0p88>; vdda18-supply = <&vreg_l12a_1p8>; @@ -685,10 +685,6 @@ &usb_sec_qmpphy_out { remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_sec_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_sec { status = "okay"; }; @@ -697,6 +693,10 @@ &usb_sec_dwc3 { dr_mode = "host"; }; +&usb_sec_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &wifi { memory-region = <&wlan_mem>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 897c0f51a612..2d2cbbff4e13 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2547,7 +2547,9 @@ port@0 { port@1 { reg = <1>; - usb_prim_qmpphy_usb_ss_in: endpoint {}; + usb_prim_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_prim_dwc3_ss>; + }; }; port@2 { @@ -2592,7 +2594,9 @@ port@0 { port@1 { reg = <1>; - usb_sec_qmpphy_usb_ss_in: endpoint {}; + usb_sec_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_sec_dwc3_ss>; + }; }; port@2 { @@ -2672,8 +2676,23 @@ usb_prim_dwc3: usb@a600000 { phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_prim_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_prim_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_prim_dwc3_ss: endpoint { + remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>; + }; }; }; }; @@ -2729,8 +2748,23 @@ usb_sec_dwc3: usb@a800000 { phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_sec_role_switch: endpoint { + ports { + #address-cells = <1>; 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Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 20 ++++---- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 ++++---- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 54 ++++++++++++++++++++-- 3 files changed, 70 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 41215567b3ae..a2627ab4db9a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -56,7 +56,7 @@ port@0 { reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_0_role_switch>; + remote-endpoint = <&usb_0_dwc3_hs>; }; }; @@ -91,7 +91,7 @@ port@0 { reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_1_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -675,6 +675,10 @@ &usb_0_dwc3 { dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -700,10 +704,6 @@ &usb_0_qmpphy_out { remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_0_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_1 { status = "okay"; }; @@ -712,6 +712,10 @@ &usb_1_dwc3 { dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -737,10 +741,6 @@ &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_1_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &xo_board_clk { clock-frequency = <38400000>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index e937732abede..cd914fffcf06 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -117,7 +117,7 @@ port@0 { reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_0_role_switch>; + remote-endpoint = <&usb_0_dwc3_hs>; }; }; @@ -152,7 +152,7 @@ port@0 { reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_1_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -1131,6 +1131,10 @@ &usb_0_dwc3 { dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -1156,10 +1160,6 @@ &usb_0_qmpphy_out { remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_0_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_1 { status = "okay"; }; @@ -1168,6 +1168,10 @@ &usb_1_dwc3 { dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -1193,10 +1197,6 @@ &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_1_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0549ba1fbeea..e87196b2ace0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3222,6 +3222,14 @@ port@0 { usb_0_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + port@2 { reg = <2>; @@ -3275,6 +3283,14 @@ port@0 { usb_1_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + port@2 { reg = <2>; @@ -3560,8 +3576,23 @@ usb_0_dwc3: usb@a600000 { phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3622,8 +3653,23 @@ usb_1_dwc3: usb@a800000 { phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; 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a=openpgp-sha256; l=4103; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=a9kcVLJINRQjpoiZC2UmTOwWA8hvy6/mvWba1iebDR0=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmP+tYsFqapM1YYmxE836Xc/0sqOR8DJWESBPvS QvSvWS3Z/SJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj/rWAAKCRCLPIo+Aiko 1ZF+B/4wL1OetoBeuvqaIhWgG9oIV7YNxQKCafZNUz9F+oZ2a5jWm65Tc6tSxscv/20DEfDbR7G 9aJQlOqC8ogI+wKNOXvYv3I0kBfommG6BV4T6/zNrUTG2hl8+Q2E0vzdGiRD1TXWXzqVDnBEPVQ 3/M6tvSMjOYk87UuDlZSRo9871VUqBnnKTCU3/ajVjzG7EYomL96m5/866f4MzOBGeo0OM33/d8 gJjjsTc76PP5Mmx0jpaVwYEM2Q9EimlQ3U1r1/3+7EVymDzryS3pbaX5YHtMb77rL7lJ2hGTiv5 E81UQ6hKl9vudQ0XID3hfsn/Dhi+SFg1teJqqzJN95uyF/LT X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 149 +++++++++++++++++++++++++++++++-- 1 file changed, 141 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5f90a0b3c016..cf8d8d5b1870 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2543,6 +2543,33 @@ usb_1_ss0_qmpphy: phy@fd5000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss0_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1_ss1_hsphy: phy@fd9000 { @@ -2583,6 +2610,33 @@ usb_1_ss1_qmpphy: phy@fda000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss1_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1_ss2_hsphy: phy@fde000 { @@ -2623,6 +2677,33 @@ usb_1_ss2_qmpphy: phy@fdf000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss2_qmpphy_dp_in: endpoint { + }; + }; + }; }; cnoc_main: interconnect@1500000 { @@ -3445,8 +3526,23 @@ usb_1_ss2_dwc3: usb@a000000 { dma-coherent; - port { - usb_1_ss2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3514,8 +3610,15 @@ usb_2_dwc3: usb@a200000 { phy-names = "usb2-phy"; maximum-speed = "high-speed"; - port { - usb_2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_dwc3_hs: endpoint { + }; }; }; }; @@ -3590,8 +3693,23 @@ usb_1_ss0_dwc3: usb@a600000 { dma-coherent; - port { - usb_1_ss0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3673,8 +3791,23 @@ usb_1_ss1_dwc3: usb@a800000 { dma-coherent; - port { - usb_1_ss1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 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Sat, 11 May 2024 15:04:17 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-521f38d878fsm1123875e87.206.2024.05.11.15.04.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 May 2024 15:04:17 -0700 (PDT) From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:15 +0300 Subject: [PATCH v4 9/9] arm64: dts: qcom: sm8150-hdk: rename Type-C HS endpoints Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240512-typec-fix-sm8250-v4-9-ad153c747a97@linaro.org> References: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> In-Reply-To: <20240512-typec-fix-sm8250-v4-0-ad153c747a97@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=948; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=2X9TSF9mpPgpbniBtbr3RQy14gET4Nt7uQSs8F1H82k=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmP+tYCqjWTMqYT9C9MzILCW2xppEsFrszHxcGD 9qoZpVEtyCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZj/rWAAKCRCLPIo+Aiko 1bJeB/9dYlm2ImAAYIpoDO3azYyYwVLOLaqOX/SDTnE4+gwhzOpuEqtbY5JiqriY60KKW9ij7/a 1mxB0aOSWJt2Ky3k53n27tKZ1Crys9glIyen8SE0QNwxhf6Brl7GbxNgW7kMi+i4J93b36eps5J FZ8qFpj1BwynxQCkhoU4rbQvJ1TXWGhDTbjRX1+nBhENSy5lY2j5dbgawc74H0qAG6RbUzUM3MJ h5enTm7NSR+G40BziJa9JNIQXfPsqwoWX28LRRn5PDx8auXoNhHOtJIhVkykOAdnFv7nCCEvxXs Y/fuJLyIAIIueu01Gxgaojt3fl34BbpnN6ohh32m2RW9ZVe3 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Follow other Qualcomm platforms and rename pm8150b_role_switch_in to pm8150_hs_in. Corresponding port is described as HS port rather than role switching. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 6cb6f503fdac..e9b9abc18746 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -556,7 +556,7 @@ ports { port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { + pm8150b_hs_in: endpoint { remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -708,7 +708,7 @@ &usb_1_dwc3 { }; &usb_1_dwc3_hs { - remote-endpoint = <&pm8150b_role_switch_in>; + remote-endpoint = <&pm8150b_hs_in>; }; &usb_1_dwc3_ss {