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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 01/45] target/hppa: Move cpu_get_tb_cpu_state out of line Date: Mon, 13 May 2024 09:46:33 +0200 Message-Id: <20240513074717.130949-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 43 ++----------------------------------------- target/hppa/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 41 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fb2e4c4a98..61f1353133 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -314,47 +314,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 -static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - uint32_t flags = env->psw_n * PSW_N; - - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ -#ifdef CONFIG_USER_ONLY - *pc = env->iaoq_f & -4; - *cs_base = env->iaoq_b & -4; - flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#else - /* ??? E, T, H, L, B bits need to be here, when implemented. */ - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); - flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); - *cs_base = env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a page. - Failure is indicated by a zero difference. */ - if (env->iasq_f == env->iasq_b) { - target_long diff = env->iaoq_b - env->iaoq_f; - if (diff == (int32_t)diff) { - *cs_base |= (uint32_t)diff; - } - } - if ((env->sr[4] == env->sr[5]) - & (env->sr[4] == env->sr[6]) - & (env->sr[4] == env->sr[7])) { - flags |= TB_FLAG_SR_SAME; - } -#endif - - *pflags = flags; -} +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags); target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 393a81988d..582036b31e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -43,6 +43,48 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) return cpu->env.iaoq_f; } +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags = env->psw_n * PSW_N; + + /* TB lookup assumes that PC contains the complete virtual address. + If we leave space+offset separate, we'll get ITLB misses to an + incomplete virtual address. This also means that we must separate + out current cpu privilege from the low bits of IAOQ_F. */ +#ifdef CONFIG_USER_ONLY + *pc = env->iaoq_f & -4; + *cs_base = env->iaoq_b & -4; + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#else + /* ??? E, T, H, L, B bits need to be here, when implemented. */ + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); + *cs_base = env->iasq_f; + + /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero + low 32-bits of CS_BASE. This will succeed for all direct branches, + which is the primary case we care about -- using goto_tb within a page. + Failure is indicated by a zero difference. */ + if (env->iasq_f == env->iasq_b) { + target_long diff = env->iaoq_b - env->iaoq_f; + if (diff == (int32_t)diff) { + *cs_base |= (uint32_t)diff; + } + } + if ((env->sr[4] == env->sr[5]) + & (env->sr[4] == env->sr[6]) + & (env->sr[4] == env->sr[7])) { + flags |= TB_FLAG_SR_SAME; + } +#endif + + *pflags = flags; +} + static void hppa_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { From patchwork Mon May 13 07:46:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796545 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884839wra; Mon, 13 May 2024 00:54:54 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVIvqdKkhqlj3xu0K3sEQ0f2sN0vYnbjBCIZR67Nqg8PloASdK6VWY6inbQsKOCbSpgZ02jaKOGaxuXqTebjI8W X-Google-Smtp-Source: AGHT+IGi3Y1aEXnxRUiTdK5KXiQVHfkos3jHR8oeJzauHAng6BoGXcJM0JALOE3PD0gE+p83tbnh X-Received: by 2002:a05:622a:13ce:b0:43e:1ae6:dcec with SMTP id d75a77b69052e-43e1ae6def1mr19954781cf.55.1715586894637; Mon, 13 May 2024 00:54:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586894; cv=none; d=google.com; s=arc-20160816; b=hi3/DLFXHiU3zLonsUpTMr0uHKIko0SrvsC8PVMrgoZJiswa3MSfC4ml9kBqAfcQkv +DAqtWeDoaXrLDf7VtorCly2kGhw0ynPmGpb2h3CRsMKFPuQusgANhMPp38FfWRIt0af XjkzlHqd1zvZV4cm1GkaaQ9/TKuliFJhff2JLqM1Krbe8mSs0Ky8LdxLRpvio0Rk1+q1 0BmLunppe5zjUEcqY0RBQ15hZeEjYtwXtVnc3cdSzYMzu0lse6oBfSyqLNEQoLecQdJT CBIwu5llrCOLUSoMiEb23jua71WAYkmTmpfBL3A1P4YbxJz4EK+nJ8OhJQVSCBSth7RO AH7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+9boudcCOGEVYkNrscgu8HWtkLEddppv4wDb4lWwH3M=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=R0OFBosH33AvdKaHuE3v7KH5Jc24V3QlhBFRAKr4fJ9Flzc3IumVGsx2cW9WenpGn8 NdZgTsYG3htknwQrJz2OZ9ZKT2KtqBFHQOkoJ2jYzsnCocPm1kpRL4hVwi0AzIOYyf5l ef6B/wUlPBCfCFSNi70ZVaFEIjw54MsEIKqFl4V8z6HxaUNC3+9LDrZeUsNJFUuKLh2e IRMcDWwuEL/loMVzWFjDIwa2M/o8EiqHg5xehqWkyVfRDZiKdbLUgDD+v0Lf1DL7jyyL tAH3CLWFWZnMJ/3AY73ugSgMg7fXF7Y6c/1r5bXPCZsidlwe0w+zt1qdLuJN6OkmR8WW zo2Q==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="THxqmqN/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 02/45] target/hppa: Use hppa_form_gva_psw in hppa_cpu_get_pc Date: Mon, 13 May 2024 09:46:34 +0200 Message-Id: <20240513074717.130949-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is for log_pc(), which needs to produce a similar result to cpu_get_tb_cpu_state(). Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 582036b31e..be8c558014 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -38,9 +38,10 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) static vaddr hppa_cpu_get_pc(CPUState *cs) { - HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = cpu_env(cs); - return cpu->env.iaoq_f; + return hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, @@ -61,8 +62,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); + *pc = hppa_cpu_get_pc(env_cpu(env)); *cs_base = env->iasq_f; /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero From patchwork Mon May 13 07:46:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796501 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1882991wra; Mon, 13 May 2024 00:47:50 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUXNiU2jDAGsInEkf8N62XkIDRAm3p0GRxFmJvejKKMJd+QiQspoFk86R+I3JK4cr1eQY3Zwks0Uy6yHzv6N0ni X-Google-Smtp-Source: AGHT+IHGneBTQ8Zkf/JngZht6BrufwQQs//bxa9ZMd55+QKWK1ymtZRyyuOb5M9KuihYI3j2x82l X-Received: by 2002:a05:6214:4806:b0:6a0:ce12:b88f with SMTP id 6a1803df08f44-6a1681f18e7mr109459946d6.22.1715586470766; Mon, 13 May 2024 00:47:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586470; cv=none; d=google.com; s=arc-20160816; b=jiwD+DewHCoZLyOToWIeDJ8Cic2qSRM95IbDKQsr/BfPUSzoZyZkgeS5Vfs9/d3P8w n6owpn65zM0dSvruF5NG/ETCLwW2rho3EzgTy5YC5DPKic0KCkOEZwYZEDLAc5zfoPQj twPaYIVSW3XGbFRNjj+dtOl9a7k54VsTvooKVEUrgKpcpuV0QxmyJ8IHsWn8of35IXP6 5eVX50J4uM6k5apWII1EYXLtwbP/5u9dgHcRiqe9C3pANzi0m2MGhBzobcWXv0uvOfop JZveJLIX3Wj04DQ7/atf1/2/9e5cDZhQASMXrQvp5Xe0/uTZnwgbifi0dR5bojbPuHX4 kXnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DRvEbVFABG0rQ6mtoE7EPY1IsVsNamdAxtlX4BxsiVU=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=DrGEAzR6gtmqV0HW1znjjmZafyvw+Dtf/W/Rec0R4LGjjyi2xULw1YqhrwiLFIE6x7 /g2zuDZXE4aCC/R4TApGj44wA/1914NcjrYjzDBBSE2wlUx2IyQxPFDkIrutqBJSixD+ e8KvWhUE1mdhD9V9VKALtVZA1NZkFw8fb5Ws6BBnGzqd0UMjDHWfbGLY3p2Ch8vu5HyP fIqqC6wmMbwspyhTye60CUC2+CIbqSPkhd8L5bmUYKGk5nzQA230BD274QilxY9GqRxZ TeHbqBS3hHwtu4x3DzwBK+I8OM+QtHtzO1kEVvcCG8cw+0wRCbtYOTmMpggWmSceqWRe 9UMQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ta4I31Tp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 03/45] target/hppa: Move constant destination check into use_goto_tb Date: Mon, 13 May 2024 09:46:35 +0200 Message-Id: <20240513074717.130949-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Share this check between gen_goto_tb and hppa_tr_translate_insn. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6d45611888..398803981c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -662,9 +662,10 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif -static bool use_goto_tb(DisasContext *ctx, uint64_t dest) +static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) { - return translator_use_goto_tb(&ctx->base, dest); + return (bofs != -1 && nofs != -1 && + translator_use_goto_tb(&ctx->base, bofs)); } /* If the next insn is to be nullified, and it's on the same page, @@ -678,16 +679,16 @@ static bool use_nullify_skip(DisasContext *ctx) } static void gen_goto_tb(DisasContext *ctx, int which, - uint64_t f, uint64_t b) + uint64_t b, uint64_t n) { - if (f != -1 && b != -1 && use_goto_tb(ctx, f)) { + if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - copy_iaoq_entry(ctx, cpu_iaoq_f, f, NULL); - copy_iaoq_entry(ctx, cpu_iaoq_b, b, NULL); + copy_iaoq_entry(ctx, cpu_iaoq_f, b, NULL); + copy_iaoq_entry(ctx, cpu_iaoq_b, n, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, f, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, b, ctx->iaoq_n_var); + copy_iaoq_entry(ctx, cpu_iaoq_f, b, cpu_iaoq_b); + copy_iaoq_entry(ctx, cpu_iaoq_b, n, ctx->iaoq_n_var); tcg_gen_lookup_and_goto_ptr(); } } @@ -4744,8 +4745,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { - if (ctx->iaoq_b != -1 && ctx->iaoq_n != -1 - && use_goto_tb(ctx, ctx->iaoq_b) + if (use_goto_tb(ctx, ctx->iaoq_b, ctx->iaoq_n) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); From patchwork Mon May 13 07:46:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796546 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884861wra; Mon, 13 May 2024 00:54:59 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVRPL/1Do6IK7Tu0LW981TGGaMl0NSEDgN4qU0pxxTuXSsEV7udPKtouv3m6MKshgBU2msga+sjRJtrQRNqyE9G X-Google-Smtp-Source: AGHT+IGS3/Qd1Iq6dAyjgWI2jMshkI7XeIhfM9dgXCTN83285QJHFp7MoiPvr/DWr78UcS4CbwBm X-Received: by 2002:a05:622a:8b:b0:43a:be31:10ab with SMTP id d75a77b69052e-43dfda8eafamr98490411cf.5.1715586899614; Mon, 13 May 2024 00:54:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586899; cv=none; d=google.com; s=arc-20160816; b=SD0Fayjn3DeFV6ZCM15YW9TkzpzLFA7RSfJC6qFdznl53Z0yGfGYxsXGrqohP6rw7t qZMuBOQ0lzaxAylIzsAlUZE+tcdvtvzB5aafJhbItURzOzyVOriDGQt+7pA31WcAxeOT cTQ348IfbBvqJnf6B4k+DpMbBIKBga06Q+b8dvx7fcNCXkd0jAZA6m1fzoOK4EDhMl60 MLh8R3kwxJPmJjlQA2n5X4YOeBsd1UBk1ptIjjmwLzsGbaDer19rdKAnMbDFhEHk6tZp VqeyDEwQcMroa6pnUqAXhFYDVUMH6gMkqPa5Vy+a862naHcxH/O5yAlPXqTjjnqHRPsx hJYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EF71oCEKPx9KffJ0nhQbR+6fCow0EB4c3hkf8VxLkbs=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=gMUSTj/EEk550mbQpW0wny6qjw8xstq2qXnEh3u/V+AYNVuTQTrzJeFojIt1BtL0Bn +AIje+/ItqEJyYjJqsa1e4pI2LH8Dj2cWGdx61PfmfsEZGjDwB01LDMrye283tf6AlPG wqiMC5imbdNcrzwFzJh3sXSLNs/hgt1lbDMYHYaTA1Mrf4NqVBgAasUxJev2aBn4ElWB 83I8osrTaQupv1dY0NEy6Rl6ZaXv7M4JUAzRWCYDqCCb3qY4cx/VWYFEtZjf8RsarojD X7euwfsmbgwqO25TtkO5NpEZS+QE+UP6utW++L2a/UQ84CK4F8NIzNQcqIYqQee2Ds+y 0dGQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MYpWRI/2"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 04/45] target/hppa: Pass displacement to do_dbranch Date: Mon, 13 May 2024 09:46:36 +0200 Message-Id: <20240513074717.130949-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass a displacement instead of an absolute value. In trans_be, remove the user-only do_dbranch case. The branch we are attempting to optimize is to the zero page, which is perforce on a different page than the code currently executing, which means that we will *not* use a goto_tb. Use a plain indirect branch instead, which is what we got out of the attempted direct branch anyway. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 33 +++++++++------------------------ 1 file changed, 9 insertions(+), 24 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 398803981c..4c42b518c5 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1766,9 +1766,11 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static bool do_dbranch(DisasContext *ctx, uint64_t dest, +static bool do_dbranch(DisasContext *ctx, int64_t disp, unsigned link, bool is_n) { + uint64_t dest = iaoq_dest(ctx, disp); + if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { if (link != 0) { copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); @@ -1815,10 +1817,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, /* Handle TRUE and NEVER as direct branches. */ if (c == TCG_COND_ALWAYS) { - return do_dbranch(ctx, dest, 0, is_n && disp >= 0); - } - if (c == TCG_COND_NEVER) { - return do_dbranch(ctx, ctx->iaoq_n, 0, is_n && disp < 0); + return do_dbranch(ctx, disp, 0, is_n && disp >= 0); } taken = gen_new_label(); @@ -3914,22 +3913,6 @@ static bool trans_be(DisasContext *ctx, arg_be *a) { TCGv_i64 tmp; -#ifdef CONFIG_USER_ONLY - /* ??? It seems like there should be a good way of using - "be disp(sr2, r0)", the canonical gateway entry mechanism - to our advantage. But that appears to be inconvenient to - manage along side branch delay slots. Therefore we handle - entry into the gateway page via absolute address. */ - /* Since we don't implement spaces, just branch. Do notice the special - case of "be disp(*,r0)" using a direct branch to disp, so that we can - goto_tb to the TB containing the syscall. */ - if (a->b == 0) { - return do_dbranch(ctx, a->disp, a->l, a->n); - } -#else - nullify_over(ctx); -#endif - tmp = tcg_temp_new_i64(); tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); tmp = do_ibranch_priv(ctx, tmp); @@ -3939,6 +3922,8 @@ static bool trans_be(DisasContext *ctx, arg_be *a) #else TCGv_i64 new_spc = tcg_temp_new_i64(); + nullify_over(ctx); + load_spr(ctx, new_spc, a->sp); if (a->l) { copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); @@ -3968,7 +3953,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) static bool trans_bl(DisasContext *ctx, arg_bl *a) { - return do_dbranch(ctx, iaoq_dest(ctx, a->disp), a->l, a->n); + return do_dbranch(ctx, a->disp, a->l, a->n); } static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) @@ -4022,7 +4007,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } - return do_dbranch(ctx, dest, 0, a->n); + return do_dbranch(ctx, dest - iaoq_dest(ctx, 0), 0, a->n); } static bool trans_blr(DisasContext *ctx, arg_blr *a) @@ -4035,7 +4020,7 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) return do_ibranch(ctx, tmp, a->l, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ - return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n); + return do_dbranch(ctx, 0, a->l, a->n); } } From patchwork Mon May 13 07:46:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796503 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883266wra; Mon, 13 May 2024 00:48:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVwtnukZA5AQXEbPjdTBaB0GB2fsuNAb1h5l4o2ITg3bQAqh/PB9OmcLtUQuiqyH2qUtkZWMm7JTs32Kn5vQdY0 X-Google-Smtp-Source: AGHT+IE4X4ucRJnThrwZe5YCH+KYaCrJX2Ac44z+XIpBcufcFA9AIxY1jfLfcQWs9hgk5vLTCSzA X-Received: by 2002:a05:622a:6113:b0:437:4813:431b with SMTP id d75a77b69052e-43dfdb7b85cmr104580251cf.35.1715586536654; Mon, 13 May 2024 00:48:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586536; cv=none; d=google.com; s=arc-20160816; b=RfutLwc3F3mH0UXQbsZeToUdVRZQMeC8z8LlMy0AW8OSsXxjl7NXFolx5Xrvs6lqxe b+GPm1OJkFvUPwrRCB3ReRun9lDUi9eIQrxs5C6B1rPYdeKK0BmxEdB7qsTi69oNh2eE fGPxcqMpmkpobQEfmoj5CVLDuIXXAVklWKWM6Z0ixatBEvRlWghNu/pxFIuKQjWG1zE/ QaS/byVDTZtqJ8DPhmdbQjkMhilsnb2Y5gYRCYvJnEwAVkCyWvGlErftTqwFwvprs5Am EzOsDAsOmItRquUcF/tKRi3nqSvdurDsBsFK3QTdyawX2/QOi7B6z7PD8rHqj6+I9hy+ q82w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CAJ+Dwjcdmii7teUjtvDvc6ZzqaDM6m0amLzUomnego=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=pd/7o4NytZCLvWPgMkjGcjwpxDCB9vx5JbHq8srirzJr7kv3/hmxIQAw68UtCz0U45 LAUunxGBERVAnRwKXfv7+/eRGIam+Am1/HhT57PXxqJ86uzW4LzXvVCMTR0CGj4bN86I bXXIAvbEJRCPjJBsJPFiJycwF4TGYsy6Eu9cVOlDXBFzDbiqqkNlygMZBYINqDEkWjp4 kzz4XstnvesZ9PDRW+s313rVLds7Mt75w+KnJbuhX7m8Jzaik7IYrn+5jM9sVWH+h3l8 CrGo3GfTcK8Sb5sIYetq2E3JNTSAWGevy+wb5eGrTF5dL/un99k9J9IQQOVUNtRpP55P 2Slw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v3lzTkxu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 05/45] target/hppa: Allow prior nullification in do_ibranch Date: Mon, 13 May 2024 09:46:37 +0200 Message-Id: <20240513074717.130949-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Simplify the function by not attempting a conditional move on the branch destination -- just use nullify_over normally. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 73 +++++++++++------------------------------ 1 file changed, 20 insertions(+), 53 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4c42b518c5..140dfb747a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1871,17 +1871,15 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, unsigned link, bool is_n) { - TCGv_i64 a0, a1, next, tmp; - TCGCond c; + TCGv_i64 next; - assert(ctx->null_lab == NULL); + if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { + next = tcg_temp_new_i64(); + tcg_gen_mov_i64(next, dest); - if (ctx->null_cond.c == TCG_COND_NEVER) { if (link != 0) { copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next); @@ -1895,60 +1893,29 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } ctx->iaoq_n = -1; ctx->iaoq_n_var = next; - } else if (is_n && use_nullify_skip(ctx)) { - /* The (conditional) branch, B, nullifies the next insn, N, - and we're allowed to skip execution N (no single-step or - tracepoint in effect). Since the goto_ptr that we must use - for the indirect branch consumes no special resources, we - can (conditionally) skip B and continue execution. */ - /* The use_nullify_skip test implies we have a known control path. */ - tcg_debug_assert(ctx->iaoq_b != -1); - tcg_debug_assert(ctx->iaoq_n != -1); + return true; + } - /* We do have to handle the non-local temporary, DEST, before - branching. Since IOAQ_F is not really live at this point, we - can simply store DEST optimistically. Similarly with IAOQ_B. */ + nullify_over(ctx); + + if (is_n && use_nullify_skip(ctx)) { copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest); next = tcg_temp_new_i64(); tcg_gen_addi_i64(next, dest, 4); copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); - - nullify_over(ctx); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } - tcg_gen_lookup_and_goto_ptr(); - return nullify_end(ctx); + nullify_set(ctx, 0); } else { - c = ctx->null_cond.c; - a0 = ctx->null_cond.a0; - a1 = ctx->null_cond.a1; - - tmp = tcg_temp_new_i64(); - next = tcg_temp_new_i64(); - - copy_iaoq_entry(ctx, tmp, ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest); - ctx->iaoq_n = -1; - ctx->iaoq_n_var = next; - - if (link != 0) { - tcg_gen_movcond_i64(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp); - } - - if (is_n) { - /* The branch nullifies the next insn, which means the state of N - after the branch is the inverse of the state of N that applied - to the branch. */ - tcg_gen_setcond_i64(tcg_invert_cond(c), cpu_psw_n, a0, a1); - cond_free(&ctx->null_cond); - ctx->null_cond = cond_make_n(); - ctx->psw_n_nonzero = true; - } else { - cond_free(&ctx->null_cond); - } + copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); + nullify_set(ctx, is_n); } - return true; + if (link != 0) { + copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); + } + + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; + return nullify_end(ctx); } /* Implement From patchwork Mon May 13 07:46:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796504 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883295wra; Mon, 13 May 2024 00:49:02 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVqQiqHtVS4XmwBkJTDmqmzYqbBs6nXIxaU6mrIZHNLolu9ILeu/W3Ui2FYiXWztnQc8SBZTtiOVgqxjdNPTB+3 X-Google-Smtp-Source: AGHT+IHpXkx9DT/BnGgvdItwF6HG63WBC37fG/gzlKBxYYmLbXw6rgmZnxR6CB01nbtYXJAbyQ0I X-Received: by 2002:a05:620a:341:b0:792:b70a:2224 with SMTP id af79cd13be357-792c75f4b4emr999376585a.60.1715586542047; Mon, 13 May 2024 00:49:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586542; cv=none; d=google.com; s=arc-20160816; b=kFkIIIk/l2ja0AiDyTL+jsiB4TZxfLr1y1fr/QZBepOjRIj38QzZhhoR6vXtvbjQtI TYJ5/lsQIp5CWFRRS/WF47ujOhcecql9PSOwlxauq5gBsCgvDK9CgJEBwKvu4m0z7IV9 gzLDSzUeoZwXCWjrln5ZQ2F8br3zoLQ/tgU4VWlYU1GagHPQopZ9aIK564f6DIEp+w7c iUplKMKmys17et5J+YKz3kRPK3/oST+86Az4qqt3lnAnYQl+PV5iNaQ3i2qFuGANQjRf NoodMannsuviiDvH06XYAJNl7J9i5/ImJzUveakG3op9wYjLB1w9rPJP9SEth+KE23p9 /XGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5zJVPddiwqndhAfsv4bxEk5QwYGlyRAHKsQYLRbwnmM=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=nRIqsbkCJ1w+2+rR39MBB+ixsTJuyBDF94x51iHMq5bNE/EJpV/xzoenXEsPvMX3AF tjMM7QFoZB42LFdB6t/mOvMPri9sRVu+ciAD9uwa1GDIhjXYCq8VumLzeZZOtI1UMh/z nTpDrn7az4hoocxx6jiTJGfPuF+nej0rpHC5UcQaEHbgsXLxMaWD65hEorA3zrpN3FrX w7vEeErYirrqQ9U55FNX7g1xSZvri3l3DmfcD7sFTnAlaktwQG606j2OkokYF3IK8zso 3awTXMHx++QjJJycz7Iknb6BMcymRfhNVCoWCM45v6qW5VWfyWLRvvdKGdw8hJGiSk7J G/cw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OoCip7xl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 06/45] target/hppa: Use CF_BP_PAGE instead of cpu_breakpoint_test Date: Mon, 13 May 2024 09:46:38 +0200 Message-Id: <20240513074717.130949-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The generic tcg driver will have already checked for breakpoints. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 140dfb747a..d272be0e6e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -674,8 +674,9 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) executing a TB that merely branches to the next TB. */ static bool use_nullify_skip(DisasContext *ctx) { - return (((ctx->iaoq_b ^ ctx->iaoq_f) & TARGET_PAGE_MASK) == 0 - && !cpu_breakpoint_test(ctx->cs, ctx->iaoq_b, BP_ANY)); + return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) + && ctx->iaoq_b != -1 + && is_same_page(&ctx->base, ctx->iaoq_b)); } static void gen_goto_tb(DisasContext *ctx, int which, From patchwork Mon May 13 07:46:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796513 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883575wra; Mon, 13 May 2024 00:50:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUCdFfjIgYCXdI4IaGNc+WY2BEu6pdkke13fOGE89NsZkq3ZSvcTx/a18WqfnDIEWOnHt1JxwS1MEJe6peXpbdT X-Google-Smtp-Source: AGHT+IHLmzAx+jPIEo2sXh1w/l2FarLXJHbT1z6pF32ftlGEQtPIZzPNfpAQixZfWEDQdAYy92Tp X-Received: by 2002:a05:620a:4f0:b0:791:110:b5c0 with SMTP id af79cd13be357-792c75ef8b5mr997584985a.58.1715586606063; Mon, 13 May 2024 00:50:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586606; cv=none; d=google.com; s=arc-20160816; b=j8ZnaP/xu8w4yL226/Hx+Y/7ux85CTKNiB62Kg+ws7cL1F43nTgcwPQ8dqQZq7JIva wM7BTNwugfCxeaAHe4dZQXKIbHSL8Jgb6Ja+2MJW9b1YZ8H+FkwlECU9zEsY4UUBipcg FUqCQrSW3uEt3BBrLrt5+6+Djze0L1KVdJZQuDPkoAeAqtwH8CjAW0ihSRQXGd7R46kP JiBDETbh/A4N5k5wYK8i/oPstmsFjwGFd4PK4s29z4qHt4SIDuKiQ7emGlhWsYoWrhlK LOcuepRbfXjqpvHU7EzI8lQKFinnrC8MJNpm8FWNXX58OcFQYzwD9FOHtbVyhTOZVAam OJDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8fqWIFmvD9JUaraiZpom6kTf9G8T11TFsgyyJnV2gt8=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=A9yTJgI1caaN2zzc7qfz7NlDC3/MxRzZIodrwzyVqhZH4J6iFtTICYCEbg1nwvOGaB wn2HaykVKT3Zqwh1nlqtpGnXev3/vEoYm2Fe3PljSsmQIlqVZmrjlrjNBcB911aOlP+G L8tTgqRW8EzWkiMb8DC5MeUJxIorvi89zvOhw0ONr3Gv2rI2OXOqM54H34N6gcrfvjxe m4ZJrWYLz/QNyuXr8AfZgFuq7imTulMI5uao9TEQUlTvZXt05u/u880nt0KJYrTbRdWr pRCchEmXxU58jjoTcT/uqwinWA2GeOpnO7xzO8Rs5uD2HNhy2QLj86HMWcVxbBVKTX8O djAQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fmmoYJm9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 07/45] target/hppa: Add install_iaq_entries Date: Mon, 13 May 2024 09:46:39 +0200 Message-Id: <20240513074717.130949-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of two separate cpu_iaoq_entry calls, use one call to update both IAQ_Front and IAQ_Back. Simplify with an argument combination that automatically handles a simple increment from Front to Back. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 64 +++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d272be0e6e..08d5e2a4bc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -617,6 +617,23 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, } } +static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, + uint64_t ni, TCGv_i64 nv) +{ + copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); + + /* Allow ni variable, with nv null, to indicate a trivial advance. */ + if (ni != -1 || nv) { + copy_iaoq_entry(ctx, cpu_iaoq_b, ni, nv); + } else if (bi != -1) { + copy_iaoq_entry(ctx, cpu_iaoq_b, bi + 4, NULL); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); + } +} + static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) { return ctx->iaoq_f + disp + 8; @@ -629,8 +646,7 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -684,12 +700,10 @@ static void gen_goto_tb(DisasContext *ctx, int which, { if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - copy_iaoq_entry(ctx, cpu_iaoq_f, b, NULL); - copy_iaoq_entry(ctx, cpu_iaoq_b, n, NULL); + install_iaq_entries(ctx, b, NULL, n, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, n, ctx->iaoq_n_var); + install_iaq_entries(ctx, b, cpu_iaoq_b, n, ctx->iaoq_n_var); tcg_gen_lookup_and_goto_ptr(); } } @@ -1883,9 +1897,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } if (is_n) { if (use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, next); - tcg_gen_addi_i64(next, next, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, -1, next, -1, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1900,14 +1912,10 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, nullify_over(ctx); if (is_n && use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, dest); - next = tcg_temp_new_i64(); - tcg_gen_addi_i64(next, dest, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, -1, dest, -1, NULL); nullify_set(ctx, 0); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); nullify_set(ctx, is_n); } if (link != 0) { @@ -1998,9 +2006,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); tmp = tcg_temp_new_i64(); tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); - tcg_gen_addi_i64(tmp, tmp, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); + install_iaq_entries(ctx, -1, tmp, -1, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; break; @@ -2744,8 +2750,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, + ctx->iaoq_n, ctx->iaoq_n_var); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3898,18 +3904,15 @@ static bool trans_be(DisasContext *ctx, arg_be *a) tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); } if (a->n && use_nullify_skip(ctx)) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, tmp); - tcg_gen_addi_i64(tmp, tmp, 4); - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); + install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); nullify_set(ctx, 0); } else { - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, tmp); tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); } @@ -4018,11 +4021,10 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) nullify_over(ctx); dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, dest); tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); if (a->l) { copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); @@ -4721,8 +4723,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: if (ctx->iaoq_f == -1) { - copy_iaoq_entry(ctx, cpu_iaoq_f, -1, cpu_iaoq_b); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, -1, cpu_iaoq_b, + ctx->iaoq_n, ctx->iaoq_n_var); #ifndef CONFIG_USER_ONLY tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); #endif @@ -4751,8 +4753,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: - copy_iaoq_entry(ctx, cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); - copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, + ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); /* FALLTHRU */ case DISAS_IAQ_N_UPDATED: From patchwork Mon May 13 07:46:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796516 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883684wra; Mon, 13 May 2024 00:50:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 08/45] target/hppa: Add install_link Date: Mon, 13 May 2024 09:46:40 +0200 Message-Id: <20240513074717.130949-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a common routine for writing the return address. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 54 +++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 08d5e2a4bc..f816b337ee 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -634,6 +634,23 @@ static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, } } +static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) +{ + tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); + if (link) { + if (ctx->iaoq_b == -1) { + tcg_gen_addi_i64(cpu_gr[link], cpu_iaoq_b, 4); + } else { + tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_b + 4); + } +#ifndef CONFIG_USER_ONLY + if (with_sr0) { + tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); + } +#endif + } +} + static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) { return ctx->iaoq_f + disp + 8; @@ -1787,9 +1804,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, uint64_t dest = iaoq_dest(ctx, disp); if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } + install_link(ctx, link, false); ctx->iaoq_n = dest; if (is_n) { ctx->null_cond.c = TCG_COND_ALWAYS; @@ -1797,10 +1812,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, } else { nullify_over(ctx); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } - + install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); gen_goto_tb(ctx, 0, dest, dest + 4); @@ -1892,9 +1904,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } + install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, next, -1, NULL); @@ -1911,16 +1921,17 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, nullify_over(ctx); + next = tcg_temp_new_i64(); + tcg_gen_mov_i64(next, dest); + + install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, dest, -1, NULL); + install_iaq_entries(ctx, -1, next, -1, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, next); nullify_set(ctx, is_n); } - if (link != 0) { - copy_iaoq_entry(ctx, cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); - } tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; @@ -3899,10 +3910,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) nullify_over(ctx); load_spr(ctx, new_spc, a->sp); - if (a->l) { - copy_iaoq_entry(ctx, cpu_gr[31], ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); - } + install_link(ctx, a->l, true); if (a->n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); @@ -4019,16 +4027,16 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) return do_ibranch(ctx, dest, a->l, a->n); #else nullify_over(ctx); - dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); + dest = tcg_temp_new_i64(); + tcg_gen_mov_i64(dest, load_gpr(ctx, a->b)); + dest = do_ibranch_priv(ctx, dest); + install_link(ctx, a->l, false); install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); if (ctx->iaoq_b == -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); - if (a->l) { - copy_iaoq_entry(ctx, cpu_gr[a->l], ctx->iaoq_n, ctx->iaoq_n_var); - } nullify_set(ctx, a->n); tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; From patchwork Mon May 13 07:46:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796529 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884465wra; Mon, 13 May 2024 00:53:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWgpS/uBizVmG0aJPQqRykiiuYlygUUFvNLArNqpNDsdOkrNgMoN48iNUky/1Ob6O7eMliBtgupMaA3W/qe7eqC X-Google-Smtp-Source: AGHT+IFHAPJfKf6HV8ER/somqSufVtkLQA/EWXSdBS1MSPsqyvv/V/xey7mvAo0YVR2CY8VWXUUX X-Received: by 2002:a05:6122:d95:b0:4dc:d7aa:ccf9 with SMTP id 71dfb90a1353d-4df8834b383mr5778364e0c.12.1715586814979; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 09/45] target/hppa: Delay computation of IAQ_Next Date: Mon, 13 May 2024 09:46:41 +0200 Message-Id: <20240513074717.130949-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We no longer have to allocate a temp and perform an addition before translation of the rest of the insn. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f816b337ee..a9196050dc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1806,6 +1806,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); ctx->iaoq_n = dest; + ctx->iaoq_n_var = NULL; if (is_n) { ctx->null_cond.c = TCG_COND_ALWAYS; } @@ -1862,11 +1863,6 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, ctx->null_lab = NULL; } nullify_set(ctx, n); - if (ctx->iaoq_n == -1) { - /* The temporary iaoq_n_var died at the branch above. - Regenerate it here instead of saving it. */ - tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); - } gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); } @@ -4630,8 +4626,6 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); #endif - ctx->iaoq_n = -1; - ctx->iaoq_n_var = NULL; ctx->zero = tcg_constant_i64(0); @@ -4683,14 +4677,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ - if (ctx->iaoq_b == -1) { - ctx->iaoq_n = -1; - ctx->iaoq_n_var = tcg_temp_new_i64(); - tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); - } else { - ctx->iaoq_n = ctx->iaoq_b + 4; - ctx->iaoq_n_var = NULL; - } + ctx->iaoq_n_var = NULL; + ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4741,7 +4729,13 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ? DISAS_EXIT : DISAS_IAQ_N_UPDATED); } else if (ctx->iaoq_b == -1) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + if (ctx->iaoq_n_var) { + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); + } } break; From patchwork Mon May 13 07:46:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796521 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884187wra; Mon, 13 May 2024 00:52:26 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUp3Qs3X1qD/Ap3oCY7ycVtGP8oNBMzeVRN3sZppj0n68fBCbPBcCpyaexluVXB9u4JLLpeEr26VyFARGwfYrxb X-Google-Smtp-Source: AGHT+IEOWDZ8LN+JU5ZhJjV7mfWHC3OJqMzeELejTp4RoloWx9FlD5okYxH3W/n+clFbjql7IG2h X-Received: by 2002:a05:620a:2950:b0:792:e36a:9dea with SMTP id af79cd13be357-792e36a9f87mr108914785a.77.1715586746381; Mon, 13 May 2024 00:52:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586746; cv=none; d=google.com; s=arc-20160816; b=qJFlszVDPn7wvb4lJPU5we9wpc+Z5xiDzSWYV5KQkM+AiQ1oaTnqvZNZm7c7uZMPDt t1fP6nVAgpGOArbDJgbARguXlDmQxzoNpuF7sLjP5eVfrrjxrP2B2Qw+OC3haVEX1lo9 7er3YOH/QJGVZXMQQVY05ZGcSvyZGeO5LLe2Rc4RkfMXmblc8Y5Vbt1Pp5vfU1jah52q RdEPINCiAkLIvnEFrqCwBlLrUDrnRkCAoffz1CRp7087c3SmCdjx2I/3kd7JTTqY6cnr JrgroOBatxVK7MhA9p5oRV96n2ppSAxaqwegaygDk8vFwTkQcVIt75qTrzW8uj78pSty yyXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2VF6uhgMTXvCNMpmE9TGG3M5Ce9XJhasOpTWLXUhXUs=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=GdywPJF6hhU2V8lGVGFavX8ggC3J+/k4X790LFk3//BCbiueEt1TUhsZOcFfkfeJMQ LzCx53vviTIwSsGSmwQjJ4SapBhFlt4aEaZnC9CpOE2fZ+R5kq4cfurWwdy8UshbGpAw dsbc+vyr1xFWBpPQPTNg10B8eYQKBcCbvgMO2gW8+bKD0ru4dXlJ4V50K5Ksd1shhhVZ xX8BV4I/GA2SQxkq0UuDAphJP46wQmGjJhy58AQfQ9rePr1Vz/R0JGQuqYdZdLHhwEnl 6IgGsLcEsshSjqKCcIlkbCgjUJZ8IYafNPj2uuZsV/1vKvbRlckVVFOllUnuANtReuu6 tbgA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=to7oM5G2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 10/45] target/hppa: Skip nullified insns in unconditional dbranch path Date: Mon, 13 May 2024 09:46:42 +0200 Message-Id: <20240513074717.130949-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a9196050dc..ca979f4137 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1805,11 +1805,17 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); - ctx->iaoq_n = dest; - ctx->iaoq_n_var = NULL; if (is_n) { + if (use_nullify_skip(ctx)) { + nullify_set(ctx, 0); + gen_goto_tb(ctx, 0, dest, dest + 4); + ctx->base.is_jmp = DISAS_NORETURN; + return true; + } ctx->null_cond.c = TCG_COND_ALWAYS; } + ctx->iaoq_n = dest; + ctx->iaoq_n_var = NULL; } else { nullify_over(ctx); From patchwork Mon May 13 07:46:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796544 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884720wra; Mon, 13 May 2024 00:54:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXpV0JgE09fD1LhzmOrDVOVb9Fuuy6UQ2yDaD8SrkNOPg1eQT8444OZJSUEVwGmIT68c75+lcny8DDGEQoLyTYM X-Google-Smtp-Source: AGHT+IETAAAHqN1+2Sxj48m5MY7S51qGH7WqmxZkcTbZOEUo0X97lFgTmOU0uqDu2CvEVK3WAClx X-Received: by 2002:ac8:5f4b:0:b0:439:fd29:3e9 with SMTP id d75a77b69052e-43dfdb70c17mr89189101cf.27.1715586869549; Mon, 13 May 2024 00:54:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586869; cv=none; d=google.com; s=arc-20160816; b=sTH6JyVM+VG/RxOKAkXPLL9Oas+8rDzap0vpf3QN5kuwSohAX7CD6PYTqJWL3sydDz hqe8aPZDYYmc2PYn9gMfVAtitdH0wFyvNGYnHq5Jmb6RQnd/PYFo0QPydIFFyZPuAX3+ LUjC0Dn8c043osQyltAYmz7L8RR/jiV3Fo4kpzGjiyRYTnoptRzh1prXieNGrGQJRKdK xOxacCq/uP5dH9rcuicYk1DVlZaQPdysKoewSXmTxd6fpIv/WBMG4l0zIOQROe8tTh7W Q3w2vAwH28w1l3hWe8BBxsjEbNVHVpSgm/RByRdV/oLEX0C1GA9/WTStQz7/K3Gsmdvv 0Z0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GJWeNRY/eXd8vSY+AX7pwEwfAqiZIocZhPOl7aCY6u0=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=CA731aRuqFa/qrH/N1MZPiF8kmv8eM8CLfpZJqBI2JTxpTRecLhz13fUvAhesnqqKb wvaHx06WVHlSEcbcOD1oPnKeTAhFtzQeB0UqlhDkDqYwcGtzfPcN7/MLIn7fYygPLpJ0 H0Rlc37ovEwrSDyfm4j5ZFvRmfX7/y4gvj5BrKt6FHHfvsmuOI0Z4pPoao4+QjISpEOj YL/ss9eexMLcNf36r1QElIICT0c47JveA1VgKTGUG11IbpjSORtPmROAG8UKPsh48pbd I69fhnwsm4hvq8ZJEL1qXuv5KtuFgWPIwg02rkWomFw68DHzO9i5xlWc27lIob8iDf1Y 6zbw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dPxZpqDZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 11/45] target/hppa: Simplify TB end Date: Mon, 13 May 2024 09:46:43 +0200 Message-Id: <20240513074717.130949-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Minimize the amount of code in hppa_tr_translate_insn advancing the insn queue for the next insn. Move the goto_tb path to hppa_tr_tb_stop. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 109 +++++++++++++++++++++------------------- 1 file changed, 57 insertions(+), 52 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ca979f4137..13a48d1b6c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4699,54 +4699,31 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } } - /* Advance the insn queue. Note that this check also detects - a priority change within the instruction queue. */ - if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { - if (use_goto_tb(ctx, ctx->iaoq_b, ctx->iaoq_n) - && (ctx->null_cond.c == TCG_COND_NEVER - || ctx->null_cond.c == TCG_COND_ALWAYS)) { - nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); - gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); - ctx->base.is_jmp = ret = DISAS_NORETURN; - } else { - ctx->base.is_jmp = ret = DISAS_IAQ_N_STALE; - } + /* If the TranslationBlock must end, do so. */ + ctx->base.pc_next += 4; + if (ret != DISAS_NEXT) { + return; } + /* Note this also detects a priority change. */ + if (ctx->iaoq_b != ctx->iaoq_f + 4) { + ctx->base.is_jmp = DISAS_IAQ_N_STALE; + return; + } + + /* + * Advance the insn queue. + * The only exit now is DISAS_TOO_MANY from the translator loop. + */ ctx->iaoq_f = ctx->iaoq_b; ctx->iaoq_b = ctx->iaoq_n; - ctx->base.pc_next += 4; - - switch (ret) { - case DISAS_NORETURN: - case DISAS_IAQ_N_UPDATED: - break; - - case DISAS_NEXT: - case DISAS_IAQ_N_STALE: - case DISAS_IAQ_N_STALE_EXIT: - if (ctx->iaoq_f == -1) { - install_iaq_entries(ctx, -1, cpu_iaoq_b, - ctx->iaoq_n, ctx->iaoq_n_var); -#ifndef CONFIG_USER_ONLY - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); -#endif - nullify_save(ctx); - ctx->base.is_jmp = (ret == DISAS_IAQ_N_STALE_EXIT - ? DISAS_EXIT - : DISAS_IAQ_N_UPDATED); - } else if (ctx->iaoq_b == -1) { - if (ctx->iaoq_n_var) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); - } + if (ctx->iaoq_b == -1) { + if (ctx->iaoq_n_var) { + copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); + } else { + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); + tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, + gva_offset_mask(ctx->tb_flags)); } - break; - - default: - g_assert_not_reached(); } } @@ -4754,23 +4731,51 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasJumpType is_jmp = ctx->base.is_jmp; + uint64_t fi, bi; + TCGv_i64 fv, bv; + TCGv_i64 fs; + + /* Assume the insn queue has not been advanced. */ + fi = ctx->iaoq_b; + fv = cpu_iaoq_b; + fs = fi == -1 ? cpu_iasq_b : NULL; + bi = ctx->iaoq_n; + bv = ctx->iaoq_n_var; switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: - case DISAS_IAQ_N_STALE: - case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, - ctx->iaoq_b, cpu_iaoq_b); - nullify_save(ctx); + /* The insn queue has not been advanced. */ + bi = fi; + bv = fv; + fi = ctx->iaoq_f; + fv = NULL; + fs = NULL; /* FALLTHRU */ - case DISAS_IAQ_N_UPDATED: - if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { - tcg_gen_lookup_and_goto_ptr(); + case DISAS_IAQ_N_STALE: + if (use_goto_tb(ctx, fi, bi) + && (ctx->null_cond.c == TCG_COND_NEVER + || ctx->null_cond.c == TCG_COND_ALWAYS)) { + nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); + gen_goto_tb(ctx, 0, fi, bi); break; } /* FALLTHRU */ + case DISAS_IAQ_N_STALE_EXIT: + install_iaq_entries(ctx, fi, fv, bi, bv); + if (fs) { + tcg_gen_mov_i64(cpu_iasq_f, fs); + } + nullify_save(ctx); + if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { + tcg_gen_exit_tb(NULL, 0); + break; + } + /* FALLTHRU */ + case DISAS_IAQ_N_UPDATED: + tcg_gen_lookup_and_goto_ptr(); + break; case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; From patchwork Mon May 13 07:46:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796542 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884704wra; Mon, 13 May 2024 00:54:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVTVXVjEj+kevOKGhyByLs6OYij0k07AzpNyaNHsKCiyOH7lJ11MtJNDeH+TxujOMxsyx8bwtBzrKX5XHjpznTt X-Google-Smtp-Source: AGHT+IGKuHWPXhgxVuf6UfGwz5HrcrSMo5Dn8jfQe3c8fKvF+BcWoJ0weFIoz9mWElWyOL3d50HV X-Received: by 2002:a25:268b:0:b0:dcd:2d3a:b528 with SMTP id 3f1490d57ef6-dee4f1ce6bamr7587522276.9.1715586864158; Mon, 13 May 2024 00:54:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586864; cv=none; d=google.com; s=arc-20160816; b=b7Yn0Aq0Y3zO1wMzXdT94aRfnTCY45kY5yOqfeEQUNNO976gkKU8HkoCi6wCjO8bpw aELz6+ootF0tjMEU5I2ab4heBWjAPCiyQPgLTOoz+SJVdG4lgq2hCNPhMHpK5ObQVnLV jJBOwrkRgj5/+OIP3rVuPJ8yv+WR0d5pNe8P1Ml1MJy2IsAZ3NIlCaVVxniRBHZvF8hR fqWU72+iiyakHi0oH23aeoogclh/a4ZFSWXoeZ3pxu6ThQEpF5DoBC8grUoSl7I9YA6l SIQPMu8cSEfv0cvsKEu74bjO6d/7ZTV5Hvipn+Knc/QHXYeO5B3NO1JxrKQBfDeHdMre VsbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=98Yc6UutVteeKcS1a+PabWfW1CAzoS9/dEERHMGPons=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=pvOhRN2oPmjQIPHm4D2l6F1HXRT2uKopqbfPBiSgLMJzBYTpQLl6I5TanhdQRlxQY6 HnOjV7UFXZ6BK3YbKv7NkrGBSnDsXRmm0dMxELSPTLXEVHBfS9VCUt5ndRhWBVFp0J0C rZ0tqMrq6oFzglhYE2lMINlcjaJTeq1MW53AtWQmMowFwd8zwPnuGqY2OTznUr4LGodj PoIA3iSyJUUze5y65FML1kysjTWFltCXoU1aG/Z7PG8VKeDJAdVwA46EIgKciBpbbAhY /kgiQm3VvEFQxyPqSBH/fuXIpPvcTit1jIHKhjedOHxcNfl2ctX8yVISYEt+Gr3Rh/xy UYLw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W1PBNajL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 12/45] target/hppa: Add IASQ entries to DisasContext Date: Mon, 13 May 2024 09:46:44 +0200 Message-Id: <20240513074717.130949-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add variable to track space changes to IAQ. So far, no such changes are introduced, but the new checks vs ctx->iasq_b may eliminate an unnecessary copy to cpu_iasq_f with e.g. BLR. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 13a48d1b6c..d24220c60f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -50,6 +50,13 @@ typedef struct DisasContext { uint64_t iaoq_b; uint64_t iaoq_n; TCGv_i64 iaoq_n_var; + /* + * Null when IASQ_Back unchanged from IASQ_Front, + * or cpu_iasq_b, when IASQ_Back has been changed. + */ + TCGv_i64 iasq_b; + /* Null when IASQ_Next unchanged from IASQ_Back, or set by branch. */ + TCGv_i64 iasq_n; DisasCond null_cond; TCGLabel *null_lab; @@ -3916,12 +3923,12 @@ static bool trans_be(DisasContext *ctx, arg_be *a) if (a->n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, -1, tmp, -1, NULL); tcg_gen_mov_i64(cpu_iasq_f, new_spc); - tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); + tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, 0); } else { install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); - if (ctx->iaoq_b == -1) { - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + if (ctx->iasq_b) { + tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); @@ -4035,8 +4042,8 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) install_link(ctx, a->l, false); install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); - if (ctx->iaoq_b == -1) { - tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); + if (ctx->iasq_b) { + tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); } tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); nullify_set(ctx, a->n); @@ -4617,6 +4624,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; + ctx->iasq_b = NULL; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4631,6 +4639,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); + ctx->iasq_b = (diff ? NULL : cpu_iasq_b); #endif ctx->zero = tcg_constant_i64(0); @@ -4683,6 +4692,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Set up the IA queue for the next insn. This will be overwritten by a branch. */ + ctx->iasq_n = NULL; ctx->iaoq_n_var = NULL; ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; @@ -4705,7 +4715,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } /* Note this also detects a priority change. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4) { + if (ctx->iaoq_b != ctx->iaoq_f + 4 || ctx->iasq_b) { ctx->base.is_jmp = DISAS_IAQ_N_STALE; return; } @@ -4725,6 +4735,10 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) gva_offset_mask(ctx->tb_flags)); } } + if (ctx->iasq_n) { + tcg_gen_mov_i64(cpu_iasq_b, ctx->iasq_n); + ctx->iasq_b = cpu_iasq_b; + } } static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) @@ -4733,14 +4747,15 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) DisasJumpType is_jmp = ctx->base.is_jmp; uint64_t fi, bi; TCGv_i64 fv, bv; - TCGv_i64 fs; + TCGv_i64 fs, bs; /* Assume the insn queue has not been advanced. */ fi = ctx->iaoq_b; fv = cpu_iaoq_b; - fs = fi == -1 ? cpu_iasq_b : NULL; + fs = ctx->iasq_b; bi = ctx->iaoq_n; bv = ctx->iaoq_n_var; + bs = ctx->iasq_n; switch (is_jmp) { case DISAS_NORETURN: @@ -4749,12 +4764,15 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) /* The insn queue has not been advanced. */ bi = fi; bv = fv; + bs = fs; fi = ctx->iaoq_f; fv = NULL; fs = NULL; /* FALLTHRU */ case DISAS_IAQ_N_STALE: - if (use_goto_tb(ctx, fi, bi) + if (fs == NULL + && bs == NULL + && use_goto_tb(ctx, fi, bi) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); @@ -4767,6 +4785,9 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) if (fs) { tcg_gen_mov_i64(cpu_iasq_f, fs); } + if (bs) { + tcg_gen_mov_i64(cpu_iasq_b, bs); + } nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); From patchwork Mon May 13 07:46:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796511 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883484wra; Mon, 13 May 2024 00:49:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUMHvA2uskwxKY4t3aQI2hTlsUyFRkf7aSRd16WBMTCS1qi2XwDlS6EDxlISVUuPOaMo6U6Oa6MTCYnrn6vJ9aQ X-Google-Smtp-Source: AGHT+IFPF8Ah87RPpMvmJynH6s/xkvl8WvlJpI+uqlCsysXBSAxuUPMABMbMR5ASbjeZtIquS7ia X-Received: by 2002:a05:622a:1906:b0:43a:f262:ec6e with SMTP id d75a77b69052e-43dfdb4dea0mr101493351cf.32.1715586585922; Mon, 13 May 2024 00:49:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586585; cv=none; d=google.com; s=arc-20160816; b=hLwIE5qNHlBItQ02JW9E7pang9MsuhHmqOzMeRaL5d6uAIDZ9PohqJ/fk0zKik9rY/ JVSyygGdX6aKL2e4oiNS++NXPeOLzzdesa1ulfB9uG2GjTEue7wdYTbCs0MBPMMqbJs6 1FuXrRRnguvxIqXrlIIobYBTSJ16HJTg4KzHtsJ5d8AixA+CzkUkmpdb87/BAoBmpqDu 4jn8FOiUMXQYOdL+TZyjLBqGZQWlE7SbEWSGzM31aKak4kZciUmTicCGOJ+D1sK5Z9MG wftf+r/V72UNgG2R4YhRTfwteSrEwGwjxdbJU1XHo9VypXI7530is1QwW/nJ8cNAy3Km nLPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZeHTNmgl5VcWCzWyaGiTmj8h8z3iRV8Wt7l8INt8uKM=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=xUZ1VUvOE4XeIgn08TxOm6IkVwCPQlYJvoYFzgDj3EhCsnjNIoMU1ysMQV4zBJ67aw 2NJlC1CCo2wbnw5fZOvvdQCNjuqBd8oLRxzRvPFZAh0beEJmNfrjhX8uzTgUOVW6v84L 1w3mXZ9AG1ZSsFpslnXKI78suzNbOej1Rf2qHOry6sW9aC1rXviDMDvAHn1IZvPPA03p aSpxZ7HyU3XGy6/GNMcE6py4J9x5ZZQibCzA+N87d4gs65JPKX5reWx+EY3kBOzdO7YD bbHeSy+qvjcsof+ubfPlwhXUJYYF7dl9nQ4AkkUDnZ3Rge6VAijVgk1ETJeP5nMxjERf 674A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r6vcA7G6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 13/45] target/hppa: Add space arguments to install_iaq_entries Date: Mon, 13 May 2024 09:46:45 +0200 Message-Id: <20240513074717.130949-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move space assighments to a central location. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 58 +++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d24220c60f..05383dcd04 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -624,8 +624,9 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, } } -static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, - uint64_t ni, TCGv_i64 nv) +static void install_iaq_entries(DisasContext *ctx, + uint64_t bi, TCGv_i64 bv, TCGv_i64 bs, + uint64_t ni, TCGv_i64 nv, TCGv_i64 ns) { copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); @@ -639,6 +640,12 @@ static void install_iaq_entries(DisasContext *ctx, uint64_t bi, TCGv_i64 bv, tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, gva_offset_mask(ctx->tb_flags)); } + if (bs) { + tcg_gen_mov_i64(cpu_iasq_f, bs); + } + if (ns || bs) { + tcg_gen_mov_i64(cpu_iasq_b, ns ? ns : bs); + } } static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) @@ -670,7 +677,8 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, ctx->iaoq_b, cpu_iaoq_b); + install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, NULL, + ctx->iaoq_b, cpu_iaoq_b, NULL); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -724,10 +732,11 @@ static void gen_goto_tb(DisasContext *ctx, int which, { if (use_goto_tb(ctx, b, n)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, b, NULL, n, NULL); + install_iaq_entries(ctx, b, NULL, NULL, n, NULL, NULL); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, b, cpu_iaoq_b, n, ctx->iaoq_n_var); + install_iaq_entries(ctx, b, cpu_iaoq_b, ctx->iasq_b, + n, ctx->iaoq_n_var, ctx->iasq_n); tcg_gen_lookup_and_goto_ptr(); } } @@ -1916,7 +1925,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, -1, NULL); + install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1935,10 +1944,11 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, -1, NULL); + install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, next); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, next, NULL); nullify_set(ctx, is_n); } @@ -2026,7 +2036,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); tmp = tcg_temp_new_i64(); tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - install_iaq_entries(ctx, -1, tmp, -1, NULL); + install_iaq_entries(ctx, -1, tmp, NULL, -1, NULL, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; break; @@ -2770,8 +2780,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, - ctx->iaoq_n, ctx->iaoq_n_var); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + ctx->iaoq_n, ctx->iaoq_n_var, ctx->iasq_n); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3921,16 +3931,11 @@ static bool trans_be(DisasContext *ctx, arg_be *a) load_spr(ctx, new_spc, a->sp); install_link(ctx, a->l, true); if (a->n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, tmp, -1, NULL); - tcg_gen_mov_i64(cpu_iasq_f, new_spc); - tcg_gen_mov_i64(cpu_iasq_b, new_spc); + install_iaq_entries(ctx, -1, tmp, new_spc, -1, NULL, new_spc); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, tmp); - if (ctx->iasq_b) { - tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); - } - tcg_gen_mov_i64(cpu_iasq_b, new_spc); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, tmp, new_spc); nullify_set(ctx, a->n); } tcg_gen_lookup_and_goto_ptr(); @@ -4041,11 +4046,8 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) dest = do_ibranch_priv(ctx, dest); install_link(ctx, a->l, false); - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, -1, dest); - if (ctx->iasq_b) { - tcg_gen_mov_i64(cpu_iasq_f, ctx->iasq_b); - } - tcg_gen_mov_i64(cpu_iasq_b, space_select(ctx, 0, dest)); + install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, + -1, dest, space_select(ctx, 0, dest)); nullify_set(ctx, a->n); tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; @@ -4781,13 +4783,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) } /* FALLTHRU */ case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, fi, fv, bi, bv); - if (fs) { - tcg_gen_mov_i64(cpu_iasq_f, fs); - } - if (bs) { - tcg_gen_mov_i64(cpu_iasq_b, bs); - } + install_iaq_entries(ctx, fi, fv, fs, bi, bv, bs); nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 14/45] target/hppa: Add space argument to do_ibranch Date: Mon, 13 May 2024 09:46:46 +0200 Message-Id: <20240513074717.130949-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This allows unification of BE, BLR, BV, BVE with a common helper. Since we can now track space with IAQ_Next, we can now let the TranslationBlock continue across the delay slot with BE, BVE. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 76 ++++++++++++++--------------------------- 1 file changed, 26 insertions(+), 50 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 05383dcd04..ae66068123 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1913,8 +1913,8 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, - unsigned link, bool is_n) +static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, + unsigned link, bool with_sr0, bool is_n) { TCGv_i64 next; @@ -1922,10 +1922,10 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - install_link(ctx, link, false); + install_link(ctx, link, with_sr0); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); + install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; @@ -1934,6 +1934,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, } ctx->iaoq_n = -1; ctx->iaoq_n_var = next; + ctx->iasq_n = dspc; return true; } @@ -1942,13 +1943,13 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, next = tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); - install_link(ctx, link, false); + install_link(ctx, link, with_sr0); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, NULL, -1, NULL, NULL); + install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); nullify_set(ctx, 0); } else { install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, next, NULL); + -1, next, dspc); nullify_set(ctx, is_n); } @@ -3915,33 +3916,18 @@ static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_i64 tmp; + TCGv_i64 dest = tcg_temp_new_i64(); + TCGv_i64 space = NULL; - tmp = tcg_temp_new_i64(); - tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); - tmp = do_ibranch_priv(ctx, tmp); + tcg_gen_addi_i64(dest, load_gpr(ctx, a->b), a->disp); + dest = do_ibranch_priv(ctx, dest); -#ifdef CONFIG_USER_ONLY - return do_ibranch(ctx, tmp, a->l, a->n); -#else - TCGv_i64 new_spc = tcg_temp_new_i64(); - - nullify_over(ctx); - - load_spr(ctx, new_spc, a->sp); - install_link(ctx, a->l, true); - if (a->n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, tmp, new_spc, -1, NULL, new_spc); - nullify_set(ctx, 0); - } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, tmp, new_spc); - nullify_set(ctx, a->n); - } - tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; - return nullify_end(ctx); +#ifndef CONFIG_USER_ONLY + space = tcg_temp_new_i64(); + load_spr(ctx, space, a->sp); #endif + + return do_ibranch(ctx, dest, space, a->l, true, a->n); } static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -4010,7 +3996,7 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ - return do_ibranch(ctx, tmp, a->l, a->n); + return do_ibranch(ctx, tmp, NULL, a->l, false, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4029,30 +4015,20 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest = do_ibranch_priv(ctx, dest); - return do_ibranch(ctx, dest, 0, a->n); + return do_ibranch(ctx, dest, NULL, 0, false, a->n); } static bool trans_bve(DisasContext *ctx, arg_bve *a) { - TCGv_i64 dest; + TCGv_i64 b = load_gpr(ctx, a->b); + TCGv_i64 dest = do_ibranch_priv(ctx, b); + TCGv_i64 space = NULL; -#ifdef CONFIG_USER_ONLY - dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b)); - return do_ibranch(ctx, dest, a->l, a->n); -#else - nullify_over(ctx); - dest = tcg_temp_new_i64(); - tcg_gen_mov_i64(dest, load_gpr(ctx, a->b)); - dest = do_ibranch_priv(ctx, dest); - - install_link(ctx, a->l, false); - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, dest, space_select(ctx, 0, dest)); - nullify_set(ctx, a->n); - tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; - return nullify_end(ctx); +#ifndef CONFIG_USER_ONLY + space = space_select(ctx, 0, b); #endif + + return do_ibranch(ctx, dest, space, a->l, false, a->n); } static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) From patchwork Mon May 13 07:46:47 2024 Content-Type: text/plain; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 15/45] target/hppa: Use umax in do_ibranch_priv Date: Mon, 13 May 2024 09:46:47 +0200 Message-Id: <20240513074717.130949-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ae66068123..22935f4645 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1981,7 +1981,7 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) dest = tcg_temp_new_i64(); tcg_gen_andi_i64(dest, offset, -4); tcg_gen_ori_i64(dest, dest, ctx->privilege); - tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset); + tcg_gen_umax_i64(dest, dest, offset); break; } return dest; From patchwork Mon May 13 07:46:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796517 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883850wra; Mon, 13 May 2024 00:51:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV+5nI5/gy7Fzk7cpJSxrDOGuu/Q4URWAx2orC5lURE60bTrTXK20lflDTtMgucmGQIe8qs/sramSnvAWEsjicJ X-Google-Smtp-Source: AGHT+IEQ7LxwhcgM0WFijwZqmOy+xDrQLZLqAfD7s7qUitWeJvWeM5EDf7RDDZ/4AqLiK0kFK6go X-Received: by 2002:a05:620a:21c2:b0:792:bba2:2cbe with SMTP id af79cd13be357-792c75b0232mr1009748285a.35.1715586668366; Mon, 13 May 2024 00:51:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586668; cv=none; d=google.com; s=arc-20160816; b=rDjUAI/Of6+yaca2g6KZYCoHWhidiJfr2xZNCGB8RMtnNxitcVeDlHWAj3IiNAqXEd yj4SeKvzHY6Ag/SexxeaT2FuS3nIYM/V80r0ia07odSKGgvfdiphMASEOGP3z6PN9ygu 9t9LTnusfi+Q0BqOaX65XJjzbQi4sLV//tZJq985gvvcIZcTsnczgQSZNdgU4dvnR9dp T0hoGhQ7DBJvmJom+9f71FFzbFKajUijs/oCXGS6F7471OCje49ro5LE5YcQldL0VKwp FQ5+vsRemtAiB2BYxKsvk9FbPG+Kz3sBm+MsWne307k7OeCR1+ulFD0zIgs6oUFANuQp QJ2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iNBogQkAhCPuNJXeM44os2k6SzPQFDH25UufdeGcgDY=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=KT3omP2VfyfzYG5EKzwnzz228bIIp5W9aR3RC14vuOOmNqvvHWWEkLaKxExiE2r1/G O2qWf8o8L/WFMzt0r+bhgXn3jUjthA6C9RVNvtUNh8vk4Xhwt0geu839Atl/ZBYgg3lb C1fBKvgECmfuo0dtYfLQD4BclC+xJamzGnOejLjKPDYYSzIDxvuKyUyAxRmq+UYDLEtO gAuzycDRW48JbVxfvTKlooYSA7+gl+39qfHKkdwTP4a1D2h77cXbXUNqfv764fDSDD3f tSosSBdwp9Aa3z8DpFWqehSTJ/UWr6AmHa+CULdn2ql9NA/1CWbQvZyWC83M+8LTSxxa kIiA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fqPb4JBN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 16/45] target/hppa: Always make a copy in do_ibranch_priv Date: Mon, 13 May 2024 09:46:48 +0200 Message-Id: <20240513074717.130949-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This simplifies callers, which might otherwise have to make another copy. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hppa/translate.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 22935f4645..f267de14c6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1967,18 +1967,17 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, */ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) { - TCGv_i64 dest; + TCGv_i64 dest = tcg_temp_new_i64(); switch (ctx->privilege) { case 0: /* Privilege 0 is maximum and is allowed to decrease. */ - return offset; + tcg_gen_mov_i64(dest, offset); + break; case 3: /* Privilege 3 is minimum and is never allowed to increase. */ - dest = tcg_temp_new_i64(); tcg_gen_ori_i64(dest, offset, 3); break; default: - dest = tcg_temp_new_i64(); tcg_gen_andi_i64(dest, offset, -4); tcg_gen_ori_i64(dest, dest, ctx->privilege); tcg_gen_umax_i64(dest, dest, offset); From patchwork Mon May 13 07:46:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796510 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883482wra; Mon, 13 May 2024 00:49:45 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCX1YwG/3NL6Ey69FfCF9xjrh5TpKWaHSqmnI14GTE5zBpE7tfZdXlvrsZFSVziJrpu1F7AuJUu2V+OwA+J8vT1b X-Google-Smtp-Source: AGHT+IHCAYEKiimKKT0C/aB/Qs+l5rQvpWErxxzjzpjX00Dc+OK589wEqaKQu0TZ0cIxzTRPmtsf X-Received: by 2002:a05:622a:1a01:b0:43b:355:3a5f with SMTP id d75a77b69052e-43dfce2b8b8mr165404091cf.27.1715586585598; Mon, 13 May 2024 00:49:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586585; cv=none; d=google.com; s=arc-20160816; b=y5IfSEXsiLv/WN9cNu2WnCISsy3TfH8AFzN7z9d77rqEnJSP/1g3QY4aUTmtjTYPCm K9KwwiQ2QmwUwKAgq0yAy6/ow64OyNyIII1RqV3JDCGWVxnaryIdyZZcDWSNSXMeSclH G5GRT2NmmMaUgFDujoMEKNDLGgc4Q44yMkIRibBz/W2eTxfwh2/A6eQrOE711Y37dGws N5i2uBtRAA+xgfk38yiNJpRC5RDRrFOqTWLvhKTEqUiIAY9OU7uBtn7z09pSpwMMQjWV q/RMs7YOt9O08A1YMXBbpBoD4QAefLjO8g3V81/6gAX2amy5p09DvWDVpeOuTVMmsvkR Lc5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ADkbGYKP910g+fruRN3VmASk0ItWfrwKOLvahbn+fLw=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=lPeRqyl9GrmloUPoacsezV5q0fO+OG8jZZsSCdb0sfQYqg54ix9VRsZyJZSQORyRaN hx983I2SU5dwQZpT/w4uCEFZ6arbhJEWF5vco4AyivLPHh3zM4tGNxCS6JcjMQG7nSPj U7o/VxdHTXNvDe30Qw236QIh0W4PSpFt6GxoaDIendvBBZxZiHQtxUmKv9acg28yI9ov Wf2z4zuDmblvDpdyDtzYce97OTh8XWtiaeDxYtaFEGpzpoO9qkhb86UAXAyw8agvzZLt b1s1/6XUMw8m7c5ya10DowdnFk7dL3TTKNmzlhaOutKBXrMjqiwHOrSnA/tXfM4rGRFQ +2Qw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kmURmhjR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 17/45] target/hppa: Introduce and use DisasIAQE for branch management Date: Mon, 13 May 2024 09:46:49 +0200 Message-Id: <20240513074717.130949-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Wrap offset and space together in one structure, ensuring that they're copied together as required. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 378 +++++++++++++++++++++------------------- 1 file changed, 198 insertions(+), 180 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f267de14c6..4e2e35f9cc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -42,21 +42,23 @@ typedef struct DisasCond { TCGv_i64 a0, a1; } DisasCond; +typedef struct DisasIAQE { + /* IASQ; may be null for no change from TB. */ + TCGv_i64 space; + /* IAOQ base; may be null for immediate absolute address. */ + TCGv_i64 base; + /* IAOQ addend; absolute immedate address if base is null. */ + int64_t disp; +} DisasIAQE; + typedef struct DisasContext { DisasContextBase base; CPUState *cs; - uint64_t iaoq_f; - uint64_t iaoq_b; - uint64_t iaoq_n; - TCGv_i64 iaoq_n_var; - /* - * Null when IASQ_Back unchanged from IASQ_Front, - * or cpu_iasq_b, when IASQ_Back has been changed. - */ - TCGv_i64 iasq_b; - /* Null when IASQ_Next unchanged from IASQ_Back, or set by branch. */ - TCGv_i64 iasq_n; + /* IAQ_Front, IAQ_Back. */ + DisasIAQE iaq_f, iaq_b; + /* IAQ_Next, for jumps, otherwise null for simple advance. */ + DisasIAQE iaq_j, *iaq_n; DisasCond null_cond; TCGLabel *null_lab; @@ -602,49 +604,67 @@ static bool nullify_end(DisasContext *ctx) return true; } +static bool iaqe_variable(const DisasIAQE *e) +{ + return e->base || e->space; +} + +static DisasIAQE iaqe_incr(const DisasIAQE *e, int64_t disp) +{ + return (DisasIAQE){ + .space = e->space, + .base = e->base, + .disp = e->disp + disp, + }; +} + +static DisasIAQE iaqe_branchi(DisasContext *ctx, int64_t disp) +{ + return (DisasIAQE){ + .space = ctx->iaq_b.space, + .disp = ctx->iaq_f.disp + 8 + disp, + }; +} + +static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) +{ + return (DisasIAQE){ + .space = ctx->iaq_b.space, + .base = var, + }; +} + static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, - uint64_t ival, TCGv_i64 vval) + const DisasIAQE *src) { uint64_t mask = gva_offset_mask(ctx->tb_flags); - if (ival != -1) { - tcg_gen_movi_i64(dest, ival & mask); - return; - } - tcg_debug_assert(vval != NULL); - - /* - * We know that the IAOQ is already properly masked. - * This optimization is primarily for "iaoq_f = iaoq_b". - */ - if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) { - tcg_gen_mov_i64(dest, vval); + if (src->base == NULL) { + tcg_gen_movi_i64(dest, src->disp & mask); + } else if (src->disp == 0) { + tcg_gen_andi_i64(dest, src->base, mask); } else { - tcg_gen_andi_i64(dest, vval, mask); + tcg_gen_addi_i64(dest, src->base, src->disp); + tcg_gen_andi_i64(dest, dest, mask); } } -static void install_iaq_entries(DisasContext *ctx, - uint64_t bi, TCGv_i64 bv, TCGv_i64 bs, - uint64_t ni, TCGv_i64 nv, TCGv_i64 ns) +static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, + const DisasIAQE *b) { - copy_iaoq_entry(ctx, cpu_iaoq_f, bi, bv); + DisasIAQE b_next; - /* Allow ni variable, with nv null, to indicate a trivial advance. */ - if (ni != -1 || nv) { - copy_iaoq_entry(ctx, cpu_iaoq_b, ni, nv); - } else if (bi != -1) { - copy_iaoq_entry(ctx, cpu_iaoq_b, bi + 4, NULL); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); + if (b == NULL) { + b_next = iaqe_incr(f, 4); + b = &b_next; } - if (bs) { - tcg_gen_mov_i64(cpu_iasq_f, bs); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + copy_iaoq_entry(ctx, cpu_iaoq_b, b); + if (f->space) { + tcg_gen_mov_i64(cpu_iasq_f, f->space); } - if (ns || bs) { - tcg_gen_mov_i64(cpu_iasq_b, ns ? ns : bs); + if (b->space || f->space) { + tcg_gen_mov_i64(cpu_iasq_b, b->space ? : f->space); } } @@ -652,10 +672,11 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) { tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); if (link) { - if (ctx->iaoq_b == -1) { - tcg_gen_addi_i64(cpu_gr[link], cpu_iaoq_b, 4); + if (ctx->iaq_b.base) { + tcg_gen_addi_i64(cpu_gr[link], ctx->iaq_b.base, + ctx->iaq_b.disp + 4); } else { - tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_b + 4); + tcg_gen_movi_i64(cpu_gr[link], ctx->iaq_b.disp + 4); } #ifndef CONFIG_USER_ONLY if (with_sr0) { @@ -665,11 +686,6 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) } } -static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) -{ - return ctx->iaoq_f + disp + 8; -} - static void gen_excp_1(int exception) { gen_helper_excp(tcg_env, tcg_constant_i32(exception)); @@ -677,8 +693,7 @@ static void gen_excp_1(int exception) static void gen_excp(DisasContext *ctx, int exception) { - install_iaq_entries(ctx, ctx->iaoq_f, cpu_iaoq_f, NULL, - ctx->iaoq_b, cpu_iaoq_b, NULL); + install_iaq_entries(ctx, &ctx->iaq_f, &ctx->iaq_b); nullify_save(ctx); gen_excp_1(exception); ctx->base.is_jmp = DISAS_NORETURN; @@ -710,10 +725,12 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif -static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) +static bool use_goto_tb(DisasContext *ctx, const DisasIAQE *f, + const DisasIAQE *b) { - return (bofs != -1 && nofs != -1 && - translator_use_goto_tb(&ctx->base, bofs)); + return (!iaqe_variable(f) && + (b == NULL || !iaqe_variable(b)) && + translator_use_goto_tb(&ctx->base, f->disp)); } /* If the next insn is to be nullified, and it's on the same page, @@ -723,20 +740,19 @@ static bool use_goto_tb(DisasContext *ctx, uint64_t bofs, uint64_t nofs) static bool use_nullify_skip(DisasContext *ctx) { return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) - && ctx->iaoq_b != -1 - && is_same_page(&ctx->base, ctx->iaoq_b)); + && !iaqe_variable(&ctx->iaq_b) + && is_same_page(&ctx->base, ctx->iaq_b.disp)); } static void gen_goto_tb(DisasContext *ctx, int which, - uint64_t b, uint64_t n) + const DisasIAQE *f, const DisasIAQE *b) { - if (use_goto_tb(ctx, b, n)) { + if (use_goto_tb(ctx, f, b)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, b, NULL, NULL, n, NULL, NULL); + install_iaq_entries(ctx, f, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, b, cpu_iaoq_b, ctx->iasq_b, - n, ctx->iaoq_n_var, ctx->iasq_n); + install_iaq_entries(ctx, f, b); tcg_gen_lookup_and_goto_ptr(); } } @@ -1817,37 +1833,35 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, static bool do_dbranch(DisasContext *ctx, int64_t disp, unsigned link, bool is_n) { - uint64_t dest = iaoq_dest(ctx, disp); + ctx->iaq_j = iaqe_branchi(ctx, disp); if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, dest, dest + 4); + gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); ctx->base.is_jmp = DISAS_NORETURN; return true; } ctx->null_cond.c = TCG_COND_ALWAYS; } - ctx->iaoq_n = dest; - ctx->iaoq_n_var = NULL; + ctx->iaq_n = &ctx->iaq_j; } else { nullify_over(ctx); install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, dest, dest + 4); + gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); } else { nullify_set(ctx, is_n); - gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); + gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); } - nullify_end(ctx); nullify_set(ctx, 0); - gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); + gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); ctx->base.is_jmp = DISAS_NORETURN; } return true; @@ -1858,7 +1872,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, DisasCond *cond) { - uint64_t dest = iaoq_dest(ctx, disp); + DisasIAQE next; TCGLabel *taken = NULL; TCGCond c = cond->c; bool n; @@ -1878,26 +1892,29 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, n = is_n && disp < 0; if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 0, ctx->iaoq_n, ctx->iaoq_n + 4); + next = iaqe_incr(&ctx->iaq_b, 4); + gen_goto_tb(ctx, 0, &next, NULL); } else { if (!n && ctx->null_lab) { gen_set_label(ctx->null_lab); ctx->null_lab = NULL; } nullify_set(ctx, n); - gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); + gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); } gen_set_label(taken); /* Taken: Condition satisfied; nullify on forward branches. */ n = is_n && disp >= 0; + + next = iaqe_branchi(ctx, disp); if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); - gen_goto_tb(ctx, 1, dest, dest + 4); + gen_goto_tb(ctx, 1, &next, NULL); } else { nullify_set(ctx, n); - gen_goto_tb(ctx, 1, ctx->iaoq_b, dest); + gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); } /* Not taken: the branch itself was nullified. */ @@ -1911,45 +1928,36 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, return true; } -/* Emit an unconditional branch to an indirect target. This handles - nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 dspc, - unsigned link, bool with_sr0, bool is_n) +/* + * Emit an unconditional branch to an indirect target, in ctx->iaq_j. + * This handles nullification of the branch itself. + */ +static bool do_ibranch(DisasContext *ctx, unsigned link, + bool with_sr0, bool is_n) { - TCGv_i64 next; - if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); - install_link(ctx, link, with_sr0); if (is_n) { if (use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); + install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; return true; } ctx->null_cond.c = TCG_COND_ALWAYS; } - ctx->iaoq_n = -1; - ctx->iaoq_n_var = next; - ctx->iasq_n = dspc; + ctx->iaq_n = &ctx->iaq_j; return true; } nullify_over(ctx); - next = tcg_temp_new_i64(); - tcg_gen_mov_i64(next, dest); - install_link(ctx, link, with_sr0); if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, -1, next, dspc, -1, NULL, NULL); + install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); } else { - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - -1, next, dspc); + install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); nullify_set(ctx, is_n); } @@ -1996,8 +2004,6 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) aforementioned BE. */ static void do_page_zero(DisasContext *ctx) { - TCGv_i64 tmp; - /* If by some means we get here with PSW[N]=1, that implies that the B,GATE instruction would be skipped, and we'd fault on the next insn within the privileged page. */ @@ -2017,11 +2023,11 @@ static void do_page_zero(DisasContext *ctx) non-sequential instruction execution. Normally the PSW[B] bit detects this by disallowing the B,GATE instruction to execute under such conditions. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { goto do_sigill; } - switch (ctx->iaoq_f & -4) { + switch (ctx->iaq_f.disp & -4) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); ctx->base.is_jmp = DISAS_NORETURN; @@ -2033,11 +2039,15 @@ static void do_page_zero(DisasContext *ctx) break; case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); - tmp = tcg_temp_new_i64(); - tcg_gen_ori_i64(tmp, cpu_gr[31], 3); - install_iaq_entries(ctx, -1, tmp, NULL, -1, NULL, NULL); - ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; + { + DisasIAQE next = { .base = tcg_temp_new_i64() }; + + tcg_gen_st_i64(cpu_gr[26], tcg_env, + offsetof(CPUHPPAState, cr[27])); + tcg_gen_ori_i64(next.base, cpu_gr[31], 3); + install_iaq_entries(ctx, &next, NULL); + ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; + } break; case 0x100: /* SYSCALL */ @@ -2076,11 +2086,12 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a) static bool trans_mfia(DisasContext *ctx, arg_mfia *a) { - unsigned rt = a->t; - TCGv_i64 tmp = dest_gpr(ctx, rt); - tcg_gen_movi_i64(tmp, ctx->iaoq_f & ~3ULL); - save_gpr(ctx, rt, tmp); + TCGv_i64 dest = dest_gpr(ctx, a->t); + copy_iaoq_entry(ctx, dest, &ctx->iaq_f); + tcg_gen_andi_i64(dest, dest, -4); + + save_gpr(ctx, a->t, dest); cond_free(&ctx->null_cond); return true; } @@ -2780,8 +2791,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) nullify_over(ctx); /* Advance the instruction queue. */ - install_iaq_entries(ctx, ctx->iaoq_b, cpu_iaoq_b, ctx->iasq_b, - ctx->iaoq_n, ctx->iaoq_n_var, ctx->iasq_n); + install_iaq_entries(ctx, &ctx->iaq_b, NULL); nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ @@ -3915,18 +3925,18 @@ static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a) static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_i64 dest = tcg_temp_new_i64(); - TCGv_i64 space = NULL; - - tcg_gen_addi_i64(dest, load_gpr(ctx, a->b), a->disp); - dest = do_ibranch_priv(ctx, dest); - #ifndef CONFIG_USER_ONLY - space = tcg_temp_new_i64(); - load_spr(ctx, space, a->sp); + ctx->iaq_j.space = tcg_temp_new_i64(); + load_spr(ctx, ctx->iaq_j.space, a->sp); #endif - return do_ibranch(ctx, dest, space, a->l, true, a->n); + ctx->iaq_j.base = tcg_temp_new_i64(); + ctx->iaq_j.disp = 0; + + tcg_gen_addi_i64(ctx->iaq_j.base, load_gpr(ctx, a->b), a->disp); + ctx->iaq_j.base = do_ibranch_priv(ctx, ctx->iaq_j.base); + + return do_ibranch(ctx, a->l, true, a->n); } static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -3936,7 +3946,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { - uint64_t dest = iaoq_dest(ctx, a->disp); + int64_t disp = a->disp; nullify_over(ctx); @@ -3951,7 +3961,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) * b evil * in which instructions at evil would run with increased privs. */ - if (ctx->iaoq_b == -1 || ctx->iaoq_b != ctx->iaoq_f + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { return gen_illegal(ctx); } @@ -3969,10 +3979,11 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) } /* No change for non-gateway pages or for priv decrease. */ if (type >= 4 && type - 4 < ctx->privilege) { - dest = deposit64(dest, 0, 2, type - 4); + disp -= ctx->privilege; + disp += type - 4; } } else { - dest &= -4; /* priv = 0 */ + disp -= ctx->privilege; /* priv = 0 */ } #endif @@ -3985,17 +3996,23 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } - return do_dbranch(ctx, dest - iaoq_dest(ctx, 0), 0, a->n); + return do_dbranch(ctx, disp, 0, a->n); } static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); - tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); + DisasIAQE next = iaqe_incr(&ctx->iaq_f, 8); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + /* The computation here never changes privilege level. */ - return do_ibranch(ctx, tmp, NULL, a->l, false, a->n); + copy_iaoq_entry(ctx, t0, &next); + tcg_gen_shli_i64(t1, load_gpr(ctx, a->x), 3); + tcg_gen_add_i64(t0, t0, t1); + + ctx->iaq_j = iaqe_next_absv(ctx, t0); + return do_ibranch(ctx, a->l, false, a->n); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4014,20 +4031,22 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest = do_ibranch_priv(ctx, dest); - return do_ibranch(ctx, dest, NULL, 0, false, a->n); + ctx->iaq_j = iaqe_next_absv(ctx, dest); + + return do_ibranch(ctx, 0, false, a->n); } static bool trans_bve(DisasContext *ctx, arg_bve *a) { TCGv_i64 b = load_gpr(ctx, a->b); - TCGv_i64 dest = do_ibranch_priv(ctx, b); - TCGv_i64 space = NULL; #ifndef CONFIG_USER_ONLY - space = space_select(ctx, 0, b); + ctx->iaq_j.space = space_select(ctx, 0, b); #endif + ctx->iaq_j.base = do_ibranch_priv(ctx, b); + ctx->iaq_j.disp = 0; - return do_ibranch(ctx, dest, space, a->l, false, a->n); + return do_ibranch(ctx, a->l, false, a->n); } static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) @@ -4599,9 +4618,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx = MMU_USER_IDX; - ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; - ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; - ctx->iasq_b = NULL; + ctx->iaq_f.disp = ctx->base.pc_first | ctx->privilege; + ctx->iaq_b.disp = ctx->base.tb->cs_base | ctx->privilege; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4614,9 +4632,13 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) uint64_t iasq_f = cs_base & ~0xffffffffull; int32_t diff = cs_base; - ctx->iaoq_f = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; - ctx->iaoq_b = (diff ? ctx->iaoq_f + diff : -1); - ctx->iasq_b = (diff ? NULL : cpu_iasq_b); + ctx->iaq_f.disp = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + if (diff) { + ctx->iaq_b.disp = ctx->iaq_f.disp + diff; + } else { + ctx->iaq_b.base = cpu_iaoq_b; + ctx->iaq_b.space = cpu_iasq_b; + } #endif ctx->zero = tcg_constant_i64(0); @@ -4644,7 +4666,10 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0); + tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); + tcg_gen_insn_start(ctx->iaq_f.disp, + iaqe_variable(&ctx->iaq_b) ? -1 : ctx->iaq_b.disp, + 0); ctx->insn_start_updated = false; } @@ -4667,11 +4692,12 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) the page permissions for execute. */ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next); - /* Set up the IA queue for the next insn. - This will be overwritten by a branch. */ - ctx->iasq_n = NULL; - ctx->iaoq_n_var = NULL; - ctx->iaoq_n = ctx->iaoq_b == -1 ? -1 : ctx->iaoq_b + 4; + /* + * Set up the IA queue for the next insn. + * This will be overwritten by a branch. + */ + ctx->iaq_n = NULL; + memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4692,7 +4718,8 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) return; } /* Note this also detects a priority change. */ - if (ctx->iaoq_b != ctx->iaoq_f + 4 || ctx->iasq_b) { + if (iaqe_variable(&ctx->iaq_b) + || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { ctx->base.is_jmp = DISAS_IAQ_N_STALE; return; } @@ -4701,20 +4728,25 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) * Advance the insn queue. * The only exit now is DISAS_TOO_MANY from the translator loop. */ - ctx->iaoq_f = ctx->iaoq_b; - ctx->iaoq_b = ctx->iaoq_n; - if (ctx->iaoq_b == -1) { - if (ctx->iaoq_n_var) { - copy_iaoq_entry(ctx, cpu_iaoq_b, -1, ctx->iaoq_n_var); - } else { - tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_b, 4); - tcg_gen_andi_i64(cpu_iaoq_b, cpu_iaoq_b, - gva_offset_mask(ctx->tb_flags)); - } + ctx->iaq_f.disp = ctx->iaq_b.disp; + if (!ctx->iaq_n) { + ctx->iaq_b.disp += 4; + return; } - if (ctx->iasq_n) { - tcg_gen_mov_i64(cpu_iasq_b, ctx->iasq_n); - ctx->iasq_b = cpu_iasq_b; + /* + * If IAQ_Next is variable in any way, we need to copy into the + * IAQ_Back globals, in case the next insn raises an exception. + */ + if (ctx->iaq_n->base) { + copy_iaoq_entry(ctx, cpu_iaoq_b, ctx->iaq_n); + ctx->iaq_b.base = cpu_iaoq_b; + ctx->iaq_b.disp = 0; + } else { + ctx->iaq_b.disp = ctx->iaq_n->disp; + } + if (ctx->iaq_n->space) { + tcg_gen_mov_i64(cpu_iasq_b, ctx->iaq_n->space); + ctx->iaq_b.space = cpu_iasq_b; } } @@ -4722,43 +4754,29 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasJumpType is_jmp = ctx->base.is_jmp; - uint64_t fi, bi; - TCGv_i64 fv, bv; - TCGv_i64 fs, bs; - /* Assume the insn queue has not been advanced. */ - fi = ctx->iaoq_b; - fv = cpu_iaoq_b; - fs = ctx->iasq_b; - bi = ctx->iaoq_n; - bv = ctx->iaoq_n_var; - bs = ctx->iasq_n; + DisasIAQE *f = &ctx->iaq_b; + DisasIAQE *b = ctx->iaq_n; switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: /* The insn queue has not been advanced. */ - bi = fi; - bv = fv; - bs = fs; - fi = ctx->iaoq_f; - fv = NULL; - fs = NULL; + f = &ctx->iaq_f; + b = &ctx->iaq_b; /* FALLTHRU */ case DISAS_IAQ_N_STALE: - if (fs == NULL - && bs == NULL - && use_goto_tb(ctx, fi, bi) + if (use_goto_tb(ctx, f, b) && (ctx->null_cond.c == TCG_COND_NEVER || ctx->null_cond.c == TCG_COND_ALWAYS)) { nullify_set(ctx, ctx->null_cond.c == TCG_COND_ALWAYS); - gen_goto_tb(ctx, 0, fi, bi); + gen_goto_tb(ctx, 0, f, b); break; } /* FALLTHRU */ case DISAS_IAQ_N_STALE_EXIT: - install_iaq_entries(ctx, fi, fv, fs, bi, bv, bs); + install_iaq_entries(ctx, f, b); nullify_save(ctx); if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { tcg_gen_exit_tb(NULL, 0); @@ -4814,6 +4832,6 @@ static const TranslatorOps hppa_tr_ops = { void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { - DisasContext ctx; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 18/45] target/hppa: Use displacements in DisasIAQE Date: Mon, 13 May 2024 09:46:50 +0200 Message-Id: <20240513074717.130949-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is a first step in enabling CF_PCREL, but for now we regenerate the absolute address before writeback. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 43 ++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4e2e35f9cc..196297422b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -45,9 +45,9 @@ typedef struct DisasCond { typedef struct DisasIAQE { /* IASQ; may be null for no change from TB. */ TCGv_i64 space; - /* IAOQ base; may be null for immediate absolute address. */ + /* IAOQ base; may be null for relative address. */ TCGv_i64 base; - /* IAOQ addend; absolute immedate address if base is null. */ + /* IAOQ addend; if base is null, relative to ctx->iaoq_first. */ int64_t disp; } DisasIAQE; @@ -60,6 +60,9 @@ typedef struct DisasContext { /* IAQ_Next, for jumps, otherwise null for simple advance. */ DisasIAQE iaq_j, *iaq_n; + /* IAOQ_Front at entry to TB. */ + uint64_t iaoq_first; + DisasCond null_cond; TCGLabel *null_lab; @@ -640,7 +643,7 @@ static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, uint64_t mask = gva_offset_mask(ctx->tb_flags); if (src->base == NULL) { - tcg_gen_movi_i64(dest, src->disp & mask); + tcg_gen_movi_i64(dest, (ctx->iaoq_first + src->disp) & mask); } else if (src->disp == 0) { tcg_gen_andi_i64(dest, src->base, mask); } else { @@ -672,12 +675,8 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0) { tcg_debug_assert(ctx->null_cond.c == TCG_COND_NEVER); if (link) { - if (ctx->iaq_b.base) { - tcg_gen_addi_i64(cpu_gr[link], ctx->iaq_b.base, - ctx->iaq_b.disp + 4); - } else { - tcg_gen_movi_i64(cpu_gr[link], ctx->iaq_b.disp + 4); - } + DisasIAQE next = iaqe_incr(&ctx->iaq_b, 4); + copy_iaoq_entry(ctx, cpu_gr[link], &next); #ifndef CONFIG_USER_ONLY if (with_sr0) { tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_b); @@ -730,7 +729,7 @@ static bool use_goto_tb(DisasContext *ctx, const DisasIAQE *f, { return (!iaqe_variable(f) && (b == NULL || !iaqe_variable(b)) && - translator_use_goto_tb(&ctx->base, f->disp)); + translator_use_goto_tb(&ctx->base, ctx->iaoq_first + f->disp)); } /* If the next insn is to be nullified, and it's on the same page, @@ -741,7 +740,8 @@ static bool use_nullify_skip(DisasContext *ctx) { return (!(tb_cflags(ctx->base.tb) & CF_BP_PAGE) && !iaqe_variable(&ctx->iaq_b) - && is_same_page(&ctx->base, ctx->iaq_b.disp)); + && (((ctx->iaoq_first + ctx->iaq_b.disp) ^ ctx->iaoq_first) + & TARGET_PAGE_MASK) == 0); } static void gen_goto_tb(DisasContext *ctx, int which, @@ -2004,6 +2004,8 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) aforementioned BE. */ static void do_page_zero(DisasContext *ctx) { + assert(ctx->iaq_f.disp == 0); + /* If by some means we get here with PSW[N]=1, that implies that the B,GATE instruction would be skipped, and we'd fault on the next insn within the privileged page. */ @@ -2023,11 +2025,11 @@ static void do_page_zero(DisasContext *ctx) non-sequential instruction execution. Normally the PSW[B] bit detects this by disallowing the B,GATE instruction to execute under such conditions. */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { + if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != 4) { goto do_sigill; } - switch (ctx->iaq_f.disp & -4) { + switch (ctx->base.pc_first) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_IMP); ctx->base.is_jmp = DISAS_NORETURN; @@ -4618,8 +4620,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx = MMU_USER_IDX; - ctx->iaq_f.disp = ctx->base.pc_first | ctx->privilege; - ctx->iaq_b.disp = ctx->base.tb->cs_base | ctx->privilege; + ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; + ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; @@ -4632,9 +4634,10 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) uint64_t iasq_f = cs_base & ~0xffffffffull; int32_t diff = cs_base; - ctx->iaq_f.disp = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + ctx->iaoq_first = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; + if (diff) { - ctx->iaq_b.disp = ctx->iaq_f.disp + diff; + ctx->iaq_b.disp = diff; } else { ctx->iaq_b.base = cpu_iaoq_b; ctx->iaq_b.space = cpu_iasq_b; @@ -4667,9 +4670,9 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); - tcg_gen_insn_start(ctx->iaq_f.disp, - iaqe_variable(&ctx->iaq_b) ? -1 : ctx->iaq_b.disp, - 0); + tcg_gen_insn_start(ctx->iaoq_first + ctx->iaq_f.disp, + (iaqe_variable(&ctx->iaq_b) ? -1 : + ctx->iaoq_first + ctx->iaq_b.disp), 0); ctx->insn_start_updated = false; } From patchwork Mon May 13 07:46:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796514 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883576wra; Mon, 13 May 2024 00:50:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU6RVUAU9KuvmoEhJKIfSMyylCIyUGbCiwaT4p51GP8cAH9r7BQM8oMld0USv5CeRJuBtppibSuXwHQeDWp54Ey X-Google-Smtp-Source: AGHT+IFYNYlTo9aN3CTzMQLex4mEoxRlQ/GjeyIkE47ULBYPEKTqXWSaGOG2cP6+W+GVfFjkGV6r X-Received: by 2002:a05:6122:31a1:b0:4df:1d07:5ffa with SMTP id 71dfb90a1353d-4df88283d2fmr7110529e0c.3.1715586606008; Mon, 13 May 2024 00:50:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586605; cv=none; d=google.com; s=arc-20160816; b=sP2F3FDZRIZaU2Mv9CX2DDI+u3bZgtY7KL3sCSOg0KAD1+1elGgNTI4zqtSZHnfcLf e07WIYeWRGFrXCZj3ZLOx0J6ggYXveq++dMB0WV6JG/dcMmBmoBtmTBqrCYGy14pmT2z D/9GaNX+hyJ4gm2HzubkrfGGup0GKjfUShRhYsMgSZVAUrEFLPZflmqaHfBa8FuIaQnC k9+07mdrQ75YOZ2ETNlKRsey3+MyANAaeStDBv54pSV2wpTlsAafAnIr/8/+zw11VpYi Sof69uwYIAff8M5aelJK3DRTCG5IMfhlbTtBcE3JkALwQEBiJ4C+Plavrk7QM40VRM42 a1Sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fgExMg673JAx2cq5L5XNhe8VfWiBmskFq1MitzRUfrY=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=BcBos8lAA/Cue7WK+hsJJ5F7UZOgm3AnJ9H2UfOZ6sK+QHB1BmxKAV71S42J4IlGGt SZUnyhbI7Z4jx9ksVx8Z7WVTtzQed4K4KmXlAVZLnrzYmHddvsCEA3rzRDniecbVoArf wR2GJWkAUtyuy73/ntcpAMPgib5ydy1kABy8CkBbHsANgDNgm6y43TDkwJzp5mpMy4sK vjkOZGDIGUQnnauQ5shwNm8Ymy+BDJL+NXQ6u3jI65UNnLBkW5yisl81T+ChFSAey+eO FtmHVPQ4nLAf9LriP0lNgAZ1x0P7k6YLSwXM8DB7flPNeNSb3vA6CaKV23jT+NJkdSU9 akTg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TMPO7lsq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 19/45] target/hppa: Rename cond_make_* helpers Date: Mon, 13 May 2024 09:46:51 +0200 Message-Id: <20240513074717.130949-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use 'v' for a variable that needs copying, 't' for a temp that doesn't need copying, and 'i' for an immediate, and use this naming for both arguments of the comparison. So: cond_make_tmp -> cond_make_tt cond_make_0_tmp -> cond_make_ti cond_make_0 -> cond_make_vi cond_make -> cond_make_vv Pass 0 explictly, rather than implicitly in the function name. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 52 ++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 196297422b..5e32d985c9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -345,32 +345,32 @@ static DisasCond cond_make_n(void) }; } -static DisasCond cond_make_tmp(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) +static DisasCond cond_make_tt(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 }; } -static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0) +static DisasCond cond_make_ti(TCGCond c, TCGv_i64 a0, uint64_t imm) { - return cond_make_tmp(c, a0, tcg_constant_i64(0)); + return cond_make_tt(c, a0, tcg_constant_i64(imm)); } -static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0) +static DisasCond cond_make_vi(TCGCond c, TCGv_i64 a0, uint64_t imm) { TCGv_i64 tmp = tcg_temp_new_i64(); tcg_gen_mov_i64(tmp, a0); - return cond_make_0_tmp(c, tmp); + return cond_make_ti(c, tmp, imm); } -static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) +static DisasCond cond_make_vv(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); tcg_gen_mov_i64(t0, a0); tcg_gen_mov_i64(t1, a1); - return cond_make_tmp(c, t0, t1); + return cond_make_tt(c, t0, t1); } static void cond_free(DisasCond *cond) @@ -788,7 +788,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32u_i64(tmp, res); res = tmp; } - cond = cond_make_0(TCG_COND_EQ, res); + cond = cond_make_vi(TCG_COND_EQ, res, 0); break; case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); @@ -796,7 +796,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, if (!d) { tcg_gen_ext32s_i64(tmp, tmp); } - cond = cond_make_0_tmp(TCG_COND_LT, tmp); + cond = cond_make_ti(TCG_COND_LT, tmp, 0); break; case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ /* @@ -818,10 +818,10 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_sari_i64(tmp, tmp, 63); tcg_gen_and_i64(tmp, tmp, res); } - cond = cond_make_0_tmp(TCG_COND_EQ, tmp); + cond = cond_make_ti(TCG_COND_EQ, tmp, 0); break; case 4: /* NUV / UV (!UV / UV) */ - cond = cond_make_0(TCG_COND_EQ, uv); + cond = cond_make_vi(TCG_COND_EQ, uv, 0); break; case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */ tmp = tcg_temp_new_i64(); @@ -829,7 +829,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, if (!d) { tcg_gen_ext32u_i64(tmp, tmp); } - cond = cond_make_0_tmp(TCG_COND_EQ, tmp); + cond = cond_make_ti(TCG_COND_EQ, tmp, 0); break; case 6: /* SV / NSV (V / !V) */ if (!d) { @@ -837,12 +837,12 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32s_i64(tmp, sv); sv = tmp; } - cond = cond_make_0(TCG_COND_LT, sv); + cond = cond_make_ti(TCG_COND_LT, sv, 0); break; case 7: /* OD / EV */ tmp = tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, res, 1); - cond = cond_make_0_tmp(TCG_COND_NE, tmp); + cond = cond_make_ti(TCG_COND_NE, tmp, 0); break; default: g_assert_not_reached(); @@ -904,9 +904,9 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, tcg_gen_ext32s_i64(t1, in1); tcg_gen_ext32s_i64(t2, in2); } - return cond_make_tmp(tc, t1, t2); + return cond_make_tt(tc, t1, t2); } - return cond_make(tc, in1, in2); + return cond_make_vv(tc, in1, in2); } /* @@ -978,9 +978,9 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, } else { tcg_gen_ext32s_i64(tmp, res); } - return cond_make_0_tmp(tc, tmp); + return cond_make_ti(tc, tmp, 0); } - return cond_make_0(tc, res); + return cond_make_vi(tc, res, 0); } /* Similar, but for shift/extract/deposit conditions. */ @@ -1039,7 +1039,7 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) tcg_gen_andc_i64(tmp, tmp, res); tcg_gen_andi_i64(tmp, tmp, sgns); - return cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp); + return cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp, 0); } static TCGv_i64 get_carry(DisasContext *ctx, bool d, @@ -1453,7 +1453,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } tcg_gen_andi_i64(cb, cb, test_cb); - cond = cond_make_0_tmp(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb); + cond = cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, cb, 0); } if (is_tc) { @@ -3542,7 +3542,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) tcg_gen_shl_i64(tmp, tcg_r, tmp); } - cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); return do_cbranch(ctx, a->disp, a->n, &cond); } @@ -3559,7 +3559,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) p = a->p | (a->d ? 0 : 32); tcg_gen_shli_i64(tmp, tcg_r, p); - cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); return do_cbranch(ctx, a->disp, a->n, &cond); } @@ -4363,7 +4363,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) switch (a->c) { case 0: /* simple */ tcg_gen_andi_i64(t, t, 0x4000000); - ctx->null_cond = cond_make_0(TCG_COND_NE, t); + ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); goto done; case 2: /* rej */ inv = true; @@ -4393,16 +4393,16 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) if (inv) { TCGv_i64 c = tcg_constant_i64(mask); tcg_gen_or_i64(t, t, c); - ctx->null_cond = cond_make(TCG_COND_EQ, t, c); + ctx->null_cond = cond_make_tt(TCG_COND_EQ, t, c); } else { tcg_gen_andi_i64(t, t, mask); - ctx->null_cond = cond_make_0(TCG_COND_EQ, t); + ctx->null_cond = cond_make_ti(TCG_COND_EQ, t, 0); } } else { unsigned cbit = (a->y ^ 1) - 1; tcg_gen_extract_i64(t, t, 21 - cbit, 1); - ctx->null_cond = cond_make_0(TCG_COND_NE, t); + ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); } done: From patchwork Mon May 13 07:46:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796519 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884098wra; Mon, 13 May 2024 00:52:08 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU03/umgTDHTHhrG+Uq85/NsMcFG4AeyDIMGzcwRaMOq+9RhxBnqPTlTQitF5A4UIn51pk+0ZdeNn2/7U6LiOkT X-Google-Smtp-Source: AGHT+IH//D2x5Id4SfcE96KwTyKmCPGdFTPORvkLCaRuwaFGDsl9hMQm+QhYWcqULZvYFgeyD6NH X-Received: by 2002:ac8:574d:0:b0:43a:f64f:c2a with SMTP id d75a77b69052e-43dfdb43761mr129112071cf.46.1715586728446; Mon, 13 May 2024 00:52:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586728; cv=none; d=google.com; s=arc-20160816; b=cX4r1fnSC7Jjc7qQ1dT21OBTpff64Q9zSc1Ab8SpqqoYWM3V3Cny1tzBKjER3QggJk JxVKGOngQdcMxxkXzKGMrXV8n3pQd6Rola42AbMeajdHr8xEAAR1CsN3ZmxSdPsMWDqB 5bTwIkhrdzeI4AFnhheX4aDHREVYarcSPxKje66mWY3SAVPS8aGVzemN8wmKt23e/5ex bdFFonicvn75MfNEycZ12hbnJ4OChxMlcE2hsHxwlE+r62n5C+lLPXlIiOEdlNRjJKWI nfeuL7Afnf7K8RfkkV3o1NVXp7E+SGJ8xh6gEj0F2+AtY7TgJlArxJD7kOsWpFKTwsWt oi8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ytQjG6Gl1mpHlQJot6xkpWtqvAkw0tueQGjZp7W5mw4=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=r9Zr3o7vgkrUXIa/I46lHccoAWjkrcSr2x4z3KfMKwS4KzpNkiovXVgoaJMiJmImIk Vi0KuEmPcFPQ2D/sYSxletKOstVXCyfCyDp9NjLBgJzo1N3+oEkBx8AzYvvTU2FzXW7J +D3DJLpDaWRdRt1WqP/pXCFQlBxbAJfEPzQVXgm/N37OAOFIKCQlASRXPwBHo4qxuH5r pmnjen9WnpngStS5Oxcdml6vAqCjmvkHptltPtI2WHfbZPyyH94//vTRJv96Ib5ncJla gaisG0uP+y6eAi/y9PeiY7wX8RTwP8BtFR8TbqG1aGOAXiIyDSIEIlv9idePSAOsqAzx nPSA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l0cNlrTB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 20/45] target/hppa: Use TCG_COND_TST* in do_cond Date: Mon, 13 May 2024 09:46:52 +0200 Message-Id: <20240513074717.130949-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We can directly test bits of a 32-bit comparison without zero or sign-extending an intermediate result. We can directly test bit 0 for odd/even. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 64 ++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 36 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5e32d985c9..421b0df9d4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -775,28 +775,36 @@ static bool cond_need_cb(int c) static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, TCGv_i64 res, TCGv_i64 uv, TCGv_i64 sv) { + TCGCond sign_cond, zero_cond; + uint64_t sign_imm, zero_imm; DisasCond cond; TCGv_i64 tmp; + if (d) { + /* 64-bit condition. */ + sign_imm = 0; + sign_cond = TCG_COND_LT; + zero_imm = 0; + zero_cond = TCG_COND_EQ; + } else { + /* 32-bit condition. */ + sign_imm = 1ull << 31; + sign_cond = TCG_COND_TSTNE; + zero_imm = UINT32_MAX; + zero_cond = TCG_COND_TSTEQ; + } + switch (cf >> 1) { case 0: /* Never / TR (0 / 1) */ cond = cond_make_f(); break; case 1: /* = / <> (Z / !Z) */ - if (!d) { - tmp = tcg_temp_new_i64(); - tcg_gen_ext32u_i64(tmp, res); - res = tmp; - } - cond = cond_make_vi(TCG_COND_EQ, res, 0); + cond = cond_make_vi(zero_cond, res, zero_imm); break; case 2: /* < / >= (N ^ V / !(N ^ V) */ tmp = tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); - if (!d) { - tcg_gen_ext32s_i64(tmp, tmp); - } - cond = cond_make_ti(TCG_COND_LT, tmp, 0); + cond = cond_make_ti(sign_cond, tmp, sign_imm); break; case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */ /* @@ -804,21 +812,15 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, * (N ^ V) | Z * ((res < 0) ^ (sv < 0)) | !res * ((res ^ sv) < 0) | !res - * (~(res ^ sv) >= 0) | !res - * !(~(res ^ sv) >> 31) | !res - * !(~(res ^ sv) >> 31 & res) + * ((res ^ sv) < 0 ? 1 : !res) + * !((res ^ sv) < 0 ? 0 : res) */ tmp = tcg_temp_new_i64(); - tcg_gen_eqv_i64(tmp, res, sv); - if (!d) { - tcg_gen_sextract_i64(tmp, tmp, 31, 1); - tcg_gen_and_i64(tmp, tmp, res); - tcg_gen_ext32u_i64(tmp, tmp); - } else { - tcg_gen_sari_i64(tmp, tmp, 63); - tcg_gen_and_i64(tmp, tmp, res); - } - cond = cond_make_ti(TCG_COND_EQ, tmp, 0); + tcg_gen_xor_i64(tmp, res, sv); + tcg_gen_movcond_i64(sign_cond, tmp, + tmp, tcg_constant_i64(sign_imm), + ctx->zero, res); + cond = cond_make_ti(zero_cond, tmp, zero_imm); break; case 4: /* NUV / UV (!UV / UV) */ cond = cond_make_vi(TCG_COND_EQ, uv, 0); @@ -826,23 +828,13 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, case 5: /* ZNV / VNZ (!UV | Z / UV & !Z) */ tmp = tcg_temp_new_i64(); tcg_gen_movcond_i64(TCG_COND_EQ, tmp, uv, ctx->zero, ctx->zero, res); - if (!d) { - tcg_gen_ext32u_i64(tmp, tmp); - } - cond = cond_make_ti(TCG_COND_EQ, tmp, 0); + cond = cond_make_ti(zero_cond, tmp, zero_imm); break; case 6: /* SV / NSV (V / !V) */ - if (!d) { - tmp = tcg_temp_new_i64(); - tcg_gen_ext32s_i64(tmp, sv); - sv = tmp; - } - cond = cond_make_ti(TCG_COND_LT, sv, 0); + cond = cond_make_vi(sign_cond, sv, sign_imm); break; case 7: /* OD / EV */ - tmp = tcg_temp_new_i64(); - tcg_gen_andi_i64(tmp, res, 1); - cond = cond_make_ti(TCG_COND_NE, tmp, 0); + cond = cond_make_vi(TCG_COND_TSTNE, res, 1); break; default: g_assert_not_reached(); From patchwork Mon May 13 07:46:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796523 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884317wra; Mon, 13 May 2024 00:52:56 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV+Kwl4TpGUwSwZvI/skTgsCVIaLOomK/ugKeIqLbUvW7OEjj6v29G82J7VsiGzJvbke1CwMPB9YnW24Glc2GDw X-Google-Smtp-Source: AGHT+IG04WnkKSuT0NmLZ9dM0U7f7y4v09ADhQLULcryLtT/34H88U0YsW1NosMpPUydO1djOvmI X-Received: by 2002:a05:620a:258c:b0:790:f369:396e with SMTP id af79cd13be357-792bbe4e4admr1922960885a.31.1715586776499; Mon, 13 May 2024 00:52:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586776; cv=none; d=google.com; s=arc-20160816; b=ewFdWGJmzbGKGuupZLqb7I5tdOtIsEFIDlv4qwvIA9gbisYJ5FFY7LjxDFnR55ke5h dZkEpmiaW+aBwnQlSGaJsu1o74oNiDpFV6heokot5C+8PWW7HJmPTtVs7o92IUZymHmh /9eGmbxZhxDEPb1+FteilLnCR2TUeDwWQ6LFvqjjtcFFt9U0kTC3bYWtHD/CIzrkbSD0 3riShNsV2bKSEYLpurucXfaMKsTIZhTahjC1hQxF5HcyedXmCSy+AeA45IiHx46b1DgI DLIIesPA9YAne8UJjNZ2eAKF2bVgBz/bJ/vIkKKwOO5e1JA+LdQOyud+KAMt8vIp1a9Z cRvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hthpAUDZCE7MsS8KK7tEgLctoSvSemW+A0a2D7pgGUw=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=CPQn4DRPDc8/RhJdhGea+Sf4mqlasG+hQ+w0dYQQCqmVwGRODP2ae6LK3Mk8MTQoKA eBM/lY385PU2wJN7ygJRhf5DcvW4wN8pMyxgd3naDydHDg2/4asiPfuzFKMGPg5FaB0u HYS7PtG+f1b46Y7+cUGUvRNz8DqQYmeVSXiaqiw8aGL2xOFuqNmJzWlCeSUd6Kc97i8U sQzYK/8RFuH0qeEflctlKH4vthizqtPOHfjQsdk7OX/Yci5L3AvFkJI15HkH9HcwKOap nWlLJqz/p+WbdI6gpMphTiLJbM7WF8E4A6ag6x4QUglrYVJy0RsqSRnJINAPsF3fpyQ2 isVA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OR3wn0BR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 21/45] target/hppa: Use TCG_COND_TST* in do_log_cond Date: Mon, 13 May 2024 09:46:53 +0200 Message-Id: <20240513074717.130949-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We can directly test bits of a 32-bit comparison without zero or sign-extending an intermediate result. We can directly test bit 0 for odd/even. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 78 ++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 51 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 421b0df9d4..e4e8034c5f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -914,65 +914,41 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, TCGv_i64 res) { TCGCond tc; - bool ext_uns; + uint64_t imm; - switch (cf) { - case 0: /* never */ - case 9: /* undef, C */ - case 11: /* undef, C & !Z */ - case 12: /* undef, V */ - return cond_make_f(); - - case 1: /* true */ - case 8: /* undef, !C */ - case 10: /* undef, !C | Z */ - case 13: /* undef, !V */ - return cond_make_t(); - - case 2: /* == */ - tc = TCG_COND_EQ; - ext_uns = true; + switch (cf >> 1) { + case 0: /* never / always */ + case 4: /* undef, C */ + case 5: /* undef, C & !Z */ + case 6: /* undef, V */ + return cf & 1 ? cond_make_t() : cond_make_f(); + case 1: /* == / <> */ + tc = d ? TCG_COND_EQ : TCG_COND_TSTEQ; + imm = d ? 0 : UINT32_MAX; break; - case 3: /* <> */ - tc = TCG_COND_NE; - ext_uns = true; + case 2: /* < / >= */ + tc = d ? TCG_COND_LT : TCG_COND_TSTNE; + imm = d ? 0 : 1ull << 31; break; - case 4: /* < */ - tc = TCG_COND_LT; - ext_uns = false; + case 3: /* <= / > */ + tc = cf & 1 ? TCG_COND_GT : TCG_COND_LE; + if (!d) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_ext32s_i64(tmp, res); + return cond_make_ti(tc, tmp, 0); + } + return cond_make_vi(tc, res, 0); + case 7: /* OD / EV */ + tc = TCG_COND_TSTNE; + imm = 1; break; - case 5: /* >= */ - tc = TCG_COND_GE; - ext_uns = false; - break; - case 6: /* <= */ - tc = TCG_COND_LE; - ext_uns = false; - break; - case 7: /* > */ - tc = TCG_COND_GT; - ext_uns = false; - break; - - case 14: /* OD */ - case 15: /* EV */ - return do_cond(ctx, cf, d, res, NULL, NULL); - default: g_assert_not_reached(); } - - if (!d) { - TCGv_i64 tmp = tcg_temp_new_i64(); - - if (ext_uns) { - tcg_gen_ext32u_i64(tmp, res); - } else { - tcg_gen_ext32s_i64(tmp, res); - } - return cond_make_ti(tc, tmp, 0); + if (cf & 1) { + tc = tcg_invert_cond(tc); } - return cond_make_vi(tc, res, 0); + return cond_make_vi(tc, res, imm); } /* Similar, but for shift/extract/deposit conditions. */ From patchwork Mon May 13 07:46:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796525 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884457wra; Mon, 13 May 2024 00:53:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWl3jlFv8qrNTtBUY+7jMudM/iP6YvA5uy+zMZDZG3Hr847KiYU5kPSTndRq8myqjDi0KxFgxJllz6+1SfWYVRm X-Google-Smtp-Source: AGHT+IE3VwwIeIvY5yV6sMB6Bv7tXUlSWpcA+nIBw/FzLMIfmpg60dDX2dWIVM4sXezonc5mfj88 X-Received: by 2002:a05:620a:244a:b0:792:b0ad:eaeb with SMTP id af79cd13be357-792c757907cmr1147061085a.5.1715586813607; Mon, 13 May 2024 00:53:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586813; cv=none; d=google.com; s=arc-20160816; b=VIZSI8S19yWy2mHwXnGmVyk5xhPv+i+D4hGyNnYZ75SzGjb59umA19fsItONPnkiXt d/ywdcS83A4ckv9wFNJ4/86LC+0EbQbfWSzoT4Q8vIBqacjvP3ThTkl7JyV/WxOst/7R SLRzXFOmOc9Gof7VRowsTdphUpELbrjWP1fqJgid49vcZwMt6TOZnt8V0NDGYUAwhINM BciLXgk6//vna3h48++S6Ktcng0/g/btTl7JpKC56bg8rqmBJpfAA44AxBADazXm9W5b UaxyV8XNirBxMmSzmOLRXEJXVzrhn4g/btmuWyXf3lhc/i8fQ8qfK8xbtK4OR1m6Hb/X xEXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OH/TFNVOaT2AXYWTY9lqS1dHX1CKyczy6W2/79bycMU=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=COh95tKkorKa/kU2en71mUmiENOkjRTX+AEmRoNdZrwt3CPgFYH0qSJka1A6SnB0mu O6O5gch9r0OTUXrJGCcJAD8l+vw8+pmDKSejnYB6clNhawNPnD+0lPdVlo+EtsTlr4Ca zhl2O21MuOCnqB4IAJjDS9cHWBhq1rWD7qU9YhPgzpGbzAYDc3ZcHz/XhG7nquPZ+T5f rOWUg2Iz+P0/9oILAo0u5l4chfjUuw9MuMT9/norzblT4hf45FTjxnmDKj1C3JS43oHl 4ho4T8VmzoxSGlUbP4sa0mR1wECmThufS9eQlyxKeGBLbkP7IbGsyWsfjgxnz3pAj1b5 CYgQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GFfBhUOY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 22/45] target/hppa: Use TCG_COND_TST* in do_unit_zero_cond Date: Mon, 13 May 2024 09:46:54 +0200 Message-Id: <20240513074717.130949-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e4e8034c5f..50cc6decd8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1005,9 +1005,8 @@ static DisasCond do_unit_zero_cond(unsigned cf, bool d, TCGv_i64 res) tmp = tcg_temp_new_i64(); tcg_gen_subi_i64(tmp, res, ones); tcg_gen_andc_i64(tmp, tmp, res); - tcg_gen_andi_i64(tmp, tmp, sgns); - return cond_make_ti(cf & 1 ? TCG_COND_EQ : TCG_COND_NE, tmp, 0); + return cond_make_ti(cf & 1 ? TCG_COND_TSTEQ : TCG_COND_TSTNE, tmp, sgns); } static TCGv_i64 get_carry(DisasContext *ctx, bool d, From patchwork Mon May 13 07:46:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796537 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884637wra; Mon, 13 May 2024 00:54:11 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVstjcJ6sTUNXW38OAaeUFpeq4tGnZQ2Ft66ygZQykKYn4moe7NhBa3dCx+bQaWfmpfWxZmPSvo5gNIfY5q1Eya X-Google-Smtp-Source: AGHT+IH1S2d6rFePmK3JFlh8DWv/F3QrZKdFFtzAXjz+h+9y7LXXsb83uAbheDLVOLTQEWJe1+Vf X-Received: by 2002:a05:620a:2987:b0:792:c683:1f48 with SMTP id af79cd13be357-792c75af002mr1284726685a.36.1715586851097; Mon, 13 May 2024 00:54:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586851; cv=none; d=google.com; s=arc-20160816; b=j33JtRcdEaX8pnU7RfsY5Kn9/xVaCk9E9zP7JyQTkZfHrR5K6dLNRRALFidJysK1jG m2Z3UEwVeE6N/6gfzrh6aDf4hLAK4K3fZqYf5Q3Hx0ZwYLSueKJUW7r5sCAvTykFSbzX 9enI478KvVsoR0b8kXgC9PbLYzPScVCjSSJpQ7tKsFz8f+jYvLHuO3GAJlrAt9mwZ7sz QPVHtnPFg4QGHO2n4Xw23Ec3UTi9Fa3969Q4STOQevSB258UQGtYoh6qOXHmttt0D3t7 VBHn/wwQklpaNQRSC9nDg6kcLp2CiIbU53ISGYSYTnbAw/P2TKg+neQHuXja3MVMGVgg ODUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Snzaxs9GYAdAfilaaEFzVoEJKRW+Fg+Xd5Y1VwkG6O4=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=Hh513RSXMijqWJj1Y7qKHRMVJ/On1yioWB/QLSRH5qDZwxa4w3B51lhe09NRw0mNbA 4PsagtDs9cU2VxnzVFyiWxTDM/xQJOP5Za/Bnvy+66FL+GktxLQHbf0ZToQBulmi+6Fp q714Dz2jhxDOcbFUbUBaclcFKywu0axYyoVLqmmtYsDYjN1YAqsIAq8MqDhaRThNfLLP pemBYmQqluezKnLRZU6tCq5/Ba6OqBx+Hj4f2uTV8lm6mEJrsXvXNgV+XtzhSVvo98VQ 7mulYuOfMF4NJG94PUU8181tKVS3Zhr8zSyNLlvseccpfpKpg2rgm0FEXBL1gn9Sw/45 11vw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nPShHEw6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 23/45] target/hppa: Use TCG_COND_TST* in do_unit_addsub Date: Mon, 13 May 2024 09:46:55 +0200 Message-Id: <20240513074717.130949-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 50cc6decd8..47f4b23d1b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1419,8 +1419,8 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, tcg_gen_shri_i64(cb, cb, 1); } - tcg_gen_andi_i64(cb, cb, test_cb); - cond = cond_make_ti(cf & 1 ? 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 24/45] target/hppa: Use TCG_COND_TST* in trans_bb_imm Date: Mon, 13 May 2024 09:46:56 +0200 Message-Id: <20240513074717.130949-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 47f4b23d1b..d8973a63df 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3515,18 +3515,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) { - TCGv_i64 tmp, tcg_r; DisasCond cond; - int p; + int p = a->p | (a->d ? 0 : 32); nullify_over(ctx); - - tmp = tcg_temp_new_i64(); - tcg_r = load_gpr(ctx, a->r); - p = a->p | (a->d ? 0 : 32); - tcg_gen_shli_i64(tmp, tcg_r, p); - - cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0); + cond = cond_make_vi(a->c ? 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 25/45] target/hppa: Use registerfields.h for FPSR Date: Mon, 13 May 2024 09:46:57 +0200 Message-Id: <20240513074717.130949-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define all of the context dependent field definitions. Use FIELD_EX32 and FIELD_DP32 with named fields instead of extract32 and deposit32 with raw constants. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 25 +++++++++++++++++++++++++ target/hppa/fpu_helper.c | 26 +++++++++++++------------- target/hppa/translate.c | 18 ++++++++---------- 3 files changed, 46 insertions(+), 23 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 61f1353133..c37b4e12fb 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -24,6 +24,7 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" +#include "hw/registerfields.h" #define MMU_ABS_W_IDX 6 #define MMU_ABS_IDX 7 @@ -152,6 +153,30 @@ #define CR_IPSW 22 #define CR_EIRR 23 +FIELD(FPSR, ENA_I, 0, 1) +FIELD(FPSR, ENA_U, 1, 1) +FIELD(FPSR, ENA_O, 2, 1) +FIELD(FPSR, ENA_Z, 3, 1) +FIELD(FPSR, ENA_V, 4, 1) +FIELD(FPSR, ENABLES, 0, 5) +FIELD(FPSR, D, 5, 1) +FIELD(FPSR, T, 6, 1) +FIELD(FPSR, RM, 9, 2) +FIELD(FPSR, CQ, 11, 11) +FIELD(FPSR, CQ0_6, 15, 7) +FIELD(FPSR, CQ0_4, 17, 5) +FIELD(FPSR, CQ0_2, 19, 3) +FIELD(FPSR, CQ0, 21, 1) +FIELD(FPSR, CA, 15, 7) +FIELD(FPSR, CA0, 21, 1) +FIELD(FPSR, C, 26, 1) +FIELD(FPSR, FLG_I, 27, 1) +FIELD(FPSR, FLG_U, 28, 1) +FIELD(FPSR, FLG_O, 29, 1) +FIELD(FPSR, FLG_Z, 30, 1) +FIELD(FPSR, FLG_V, 31, 1) +FIELD(FPSR, FLAGS, 27, 5) + typedef struct HPPATLBEntry { union { IntervalTreeNode itree; diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 576f283b04..deaed2b65d 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -30,7 +30,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) env->fr0_shadow = shadow; - switch (extract32(shadow, 9, 2)) { + switch (FIELD_EX32(shadow, FPSR, RM)) { default: rm = float_round_nearest_even; break; @@ -46,7 +46,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) } set_float_rounding_mode(rm, &env->fp_status); - d = extract32(shadow, 5, 1); + d = FIELD_EX32(shadow, FPSR, D); set_flush_to_zero(d, &env->fp_status); set_flush_inputs_to_zero(d, &env->fp_status); } @@ -57,7 +57,7 @@ void cpu_hppa_loaded_fr0(CPUHPPAState *env) } #define CONVERT_BIT(X, SRC, DST) \ - ((SRC) > (DST) \ + ((unsigned)(SRC) > (unsigned)(DST) \ ? (X) / ((SRC) / (DST)) & (DST) \ : ((X) & (SRC)) * ((DST) / (SRC))) @@ -73,12 +73,12 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) } set_float_exception_flags(0, &env->fp_status); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, 1u << 0); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, 1u << 1); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, 1u << 2); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, 1u << 3); - hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, 1u << 4); - shadow |= hard_exp << (32 - 5); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_inexact, R_FPSR_ENA_I_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_underflow, R_FPSR_ENA_U_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_overflow, R_FPSR_ENA_O_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_divbyzero, R_FPSR_ENA_Z_MASK); + hard_exp |= CONVERT_BIT(soft_exp, float_flag_invalid, R_FPSR_ENA_V_MASK); + shadow |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); env->fr0_shadow = shadow; env->fr[0] = (uint64_t)shadow << 32; @@ -378,15 +378,15 @@ static void update_fr0_cmp(CPUHPPAState *env, uint32_t y, if (y) { /* targeted comparison */ /* set fpsr[ca[y - 1]] to current compare */ - shadow = deposit32(shadow, 21 - (y - 1), 1, c); + shadow = deposit32(shadow, R_FPSR_CA0_SHIFT - (y - 1), 1, c); } else { /* queued comparison */ /* shift cq right by one place */ - shadow = deposit32(shadow, 11, 10, extract32(shadow, 12, 10)); + shadow = (shadow & ~R_FPSR_CQ_MASK) | ((shadow >> 1) & R_FPSR_CQ_MASK); /* move fpsr[c] to fpsr[cq[0]] */ - shadow = deposit32(shadow, 21, 1, extract32(shadow, 26, 1)); + shadow = FIELD_DP32(shadow, FPSR, CQ0, FIELD_EX32(shadow, FPSR, C)); /* set fpsr[c] to current compare */ - shadow = deposit32(shadow, 26, 1, c); + shadow = FIELD_DP32(shadow, FPSR, C, c); } env->fr0_shadow = shadow; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d8973a63df..6d76599ea0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4323,29 +4323,28 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) switch (a->c) { case 0: /* simple */ - tcg_gen_andi_i64(t, t, 0x4000000); - ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); - goto done; + mask = R_FPSR_C_MASK; + break; case 2: /* rej */ inv = true; /* fallthru */ case 1: /* acc */ - mask = 0x43ff800; + mask = R_FPSR_C_MASK | R_FPSR_CQ_MASK; break; case 6: /* rej8 */ inv = true; /* fallthru */ case 5: /* acc8 */ - mask = 0x43f8000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_6_MASK; break; case 9: /* acc6 */ - mask = 0x43e0000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_4_MASK; break; case 13: /* acc4 */ - mask = 0x4380000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_2_MASK; break; case 17: /* acc2 */ - mask = 0x4200000; + mask = R_FPSR_C_MASK | R_FPSR_CQ0_MASK; break; default: gen_illegal(ctx); @@ -4362,11 +4361,10 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) } else { unsigned cbit = (a->y ^ 1) - 1; - tcg_gen_extract_i64(t, t, 21 - cbit, 1); + tcg_gen_extract_i64(t, t, R_FPSR_CA0_SHIFT - cbit, 1); ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); } - done: return nullify_end(ctx); } From patchwork Mon May 13 07:46:58 2024 Content-Type: text/plain; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 26/45] target/hppa: Use TCG_COND_TST* in trans_ftest Date: Mon, 13 May 2024 09:46:58 +0200 Message-Id: <20240513074717.130949-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6d76599ea0..ef62cd7e94 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4310,6 +4310,8 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) static bool trans_ftest(DisasContext *ctx, arg_ftest *a) { + TCGCond tc = TCG_COND_TSTNE; + uint32_t mask; TCGv_i64 t; nullify_over(ctx); @@ -4318,21 +4320,18 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); if (a->y == 1) { - int mask; - bool inv = false; - switch (a->c) { case 0: /* simple */ mask = R_FPSR_C_MASK; break; case 2: /* rej */ - inv = true; + tc = TCG_COND_TSTEQ; /* fallthru */ case 1: /* acc */ mask = R_FPSR_C_MASK | R_FPSR_CQ_MASK; break; case 6: /* rej8 */ - inv = true; + tc = TCG_COND_TSTEQ; /* fallthru */ case 5: /* acc8 */ mask = R_FPSR_C_MASK | R_FPSR_CQ0_6_MASK; @@ -4350,21 +4349,12 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a) gen_illegal(ctx); return true; } - if (inv) { - TCGv_i64 c = tcg_constant_i64(mask); - tcg_gen_or_i64(t, t, c); - ctx->null_cond = cond_make_tt(TCG_COND_EQ, t, c); - } else { - tcg_gen_andi_i64(t, t, mask); - ctx->null_cond = cond_make_ti(TCG_COND_EQ, t, 0); - } } else { unsigned cbit = (a->y ^ 1) - 1; - - tcg_gen_extract_i64(t, t, R_FPSR_CA0_SHIFT - cbit, 1); - ctx->null_cond = cond_make_ti(TCG_COND_NE, t, 0); + mask = R_FPSR_CA0_MASK >> cbit; } + ctx->null_cond = cond_make_ti(tc, t, mask); return nullify_end(ctx); } From patchwork Mon May 13 07:46:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796540 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884656wra; Mon, 13 May 2024 00:54:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU9mc8JuAHjgr8Y9V+tLJ4G5lk9rsz9zd+iTTh5hLUtiXjOoklGMkpx/kM/qwnRstHxMjmCwW4MKeYxYLg1NQro X-Google-Smtp-Source: AGHT+IHsvn8yuwt3pvH3cO12YpYXlEBv/64sXbY3hZVAMgwKWt+6VfwrZADzAaEUxweOVFHA5SU3 X-Received: by 2002:a05:6122:7c9:b0:4da:dff6:16bc with SMTP id 71dfb90a1353d-4df88369c07mr6162401e0c.15.1715586854854; Mon, 13 May 2024 00:54:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586854; cv=none; d=google.com; s=arc-20160816; b=n7V89E8uLCT28dOaeKI7Ok/YAroitQu5v9krrzn4zlR6YHvvuvXPASSjEp6AofxifG w67qwSL0l6iNZq235IiAK01pY8x7wQ+xMHyvxV01eslqxhBT0Ew3aGi17pId5GrXAc8p mQP4xrlOdqo+tODr0RbZ/kEJL84ZI5+NnNmoDB9XCQcUqvDPTyfuJcW7WEO+RqqB3SbL c1Je/W4rhXGHoflA0ZIUiCdGzrhEWHt9FIf0Q+g5ZCD5Nth/ZQToO5wX251zf76/GhCC i3p2LrSuA8cwVOWP+Nqg9tWgwzNRcrp5LOL/rAs1KJIivek3XU3PJe0lgE/zZkquR0fo igxg== ARC-Message-Signature: i=1; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 27/45] target/hppa: Remove cond_free Date: Mon, 13 May 2024 09:46:59 +0200 Message-Id: <20240513074717.130949-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we do not need to free tcg temporaries, the only thing cond_free does is reset the condition to never. Instead, simply write a new condition over the old, which may be simply cond_make_f() for the never condition. The do_*_cond functions do the right thing with c or cf == 0, so there's no need for a special case anymore. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/translate.c | 102 +++++++++++----------------------------- 1 file changed, 27 insertions(+), 75 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ef62cd7e94..e06c14dd15 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -373,21 +373,6 @@ static DisasCond cond_make_vv(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) return cond_make_tt(c, t0, t1); } -static void cond_free(DisasCond *cond) -{ - switch (cond->c) { - default: - cond->a0 = NULL; - cond->a1 = NULL; - /* fallthru */ - case TCG_COND_ALWAYS: - cond->c = TCG_COND_NEVER; - break; - case TCG_COND_NEVER: - break; - } -} - static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg == 0) { @@ -537,7 +522,7 @@ static void nullify_over(DisasContext *ctx) tcg_gen_brcond_i64(ctx->null_cond.c, ctx->null_cond.a0, ctx->null_cond.a1, ctx->null_lab); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); } } @@ -555,7 +540,7 @@ static void nullify_save(DisasContext *ctx) ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero = true; } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); } /* Set a PSW[N] to X. The intention is that this is used immediately @@ -1165,7 +1150,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1262,7 +1246,6 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1317,7 +1300,6 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1332,10 +1314,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_i64 in1, save_gpr(ctx, rt, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (cf) { - ctx->null_cond = do_log_cond(ctx, cf, d, dest); - } + ctx->null_cond = do_log_cond(ctx, cf, d, dest); } static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, @@ -1430,7 +1409,6 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } save_gpr(ctx, rt, dest); - cond_free(&ctx->null_cond); ctx->null_cond = cond; } @@ -1853,7 +1831,6 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, taken = gen_new_label(); tcg_gen_brcond_i64(c, cond->a0, cond->a1, taken); - cond_free(cond); /* Not taken: Condition not satisfied; nullify on backward branches. */ n = is_n && disp < 0; @@ -2035,7 +2012,7 @@ static void do_page_zero(DisasContext *ctx) static bool trans_nop(DisasContext *ctx, arg_nop *a) { - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2049,7 +2026,7 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a) /* No point in nullifying the memory barrier. */ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2061,7 +2038,7 @@ static bool trans_mfia(DisasContext *ctx, arg_mfia *a) tcg_gen_andi_i64(dest, dest, -4); save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2076,7 +2053,7 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) save_gpr(ctx, rt, t0); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2121,7 +2098,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) save_gpr(ctx, rt, tmp); done: - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2161,7 +2138,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2235,7 +2212,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2252,7 +2229,7 @@ static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) #endif save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2414,7 +2391,7 @@ static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) tcg_gen_add_i64(dest, src1, src2); save_gpr(ctx, a->b, dest); } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2656,7 +2633,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) since the entire address space is coherent. */ save_gpr(ctx, a->t, ctx->zero); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -2733,7 +2710,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) unsigned rt = a->t; if (rt == 0) { /* NOP */ - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } if (r2 == 0) { /* COPY */ @@ -2744,7 +2721,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) } else { save_gpr(ctx, rt, cpu_gr[r1]); } - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } #ifndef CONFIG_USER_ONLY @@ -2809,11 +2786,7 @@ static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) tcg_gen_xor_i64(dest, tcg_r1, tcg_r2); save_gpr(ctx, a->t, dest); - cond_free(&ctx->null_cond); - if (a->cf) { - ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); - } - + ctx->null_cond = do_unit_zero_cond(a->cf, a->d, dest); return nullify_end(ctx); } @@ -2839,7 +2812,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) tcg_gen_subi_i64(tmp, tmp, 1); } save_gpr(ctx, a->t, tmp); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3365,7 +3338,7 @@ static bool trans_ldil(DisasContext *ctx, arg_ldil *a) tcg_gen_movi_i64(tcg_rt, a->i); save_gpr(ctx, a->t, tcg_rt); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3376,7 +3349,7 @@ static bool trans_addil(DisasContext *ctx, arg_addil *a) tcg_gen_addi_i64(tcg_r1, tcg_rt, a->i); save_gpr(ctx, 1, tcg_r1); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3392,7 +3365,7 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a) tcg_gen_addi_i64(tcg_rt, cpu_gr[a->b], a->i); } save_gpr(ctx, a->t, tcg_rt); - cond_free(&ctx->null_cond); + ctx->null_cond = cond_make_f(); return true; } @@ -3618,10 +3591,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3661,10 +3631,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3706,10 +3673,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3742,10 +3706,7 @@ static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3782,10 +3743,7 @@ static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3818,10 +3776,7 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) save_gpr(ctx, a->t, dest); /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); - } + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); return nullify_end(ctx); } @@ -3855,10 +3810,7 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, save_gpr(ctx, rt, dest); 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 28/45] target/hppa: Introduce DisasDelayException Date: Mon, 13 May 2024 09:47:00 +0200 Message-Id: <20240513074717.130949-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Allow an exception to be emitted at the end of the TranslationBlock, leaving only the conditional branch inline. Use it for simple exception instructions like break, which happen to be nullified. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 60 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 5 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e06c14dd15..e75e7e5b54 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -51,6 +51,17 @@ typedef struct DisasIAQE { int64_t disp; } DisasIAQE; +typedef struct DisasDelayException { + struct DisasDelayException *next; + TCGLabel *lab; + uint32_t insn; + bool set_iir; + int8_t set_n; + uint8_t excp; + /* Saved state at parent insn. */ + DisasIAQE iaq_f, iaq_b; +} DisasDelayException; + typedef struct DisasContext { DisasContextBase base; CPUState *cs; @@ -66,6 +77,7 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; + DisasDelayException *delay_excp_list; TCGv_i64 zero; uint32_t insn; @@ -683,13 +695,38 @@ static void gen_excp(DisasContext *ctx, int exception) ctx->base.is_jmp = DISAS_NORETURN; } +static DisasDelayException *delay_excp(DisasContext *ctx, uint8_t excp) +{ + DisasDelayException *e = tcg_malloc(sizeof(DisasDelayException)); + + memset(e, 0, sizeof(*e)); + e->next = ctx->delay_excp_list; + ctx->delay_excp_list = e; + + e->lab = gen_new_label(); + e->insn = ctx->insn; + e->set_iir = true; + e->set_n = ctx->psw_n_nonzero ? 0 : -1; + e->excp = excp; + e->iaq_f = ctx->iaq_f; + e->iaq_b = ctx->iaq_b; + + return e; +} + static bool gen_excp_iir(DisasContext *ctx, int exc) { - nullify_over(ctx); - tcg_gen_st_i64(tcg_constant_i64(ctx->insn), - tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); - gen_excp(ctx, exc); - return nullify_end(ctx); + if (ctx->null_cond.c == TCG_COND_NEVER) { + tcg_gen_st_i64(tcg_constant_i64(ctx->insn), + tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); + gen_excp(ctx, exc); + } else { + DisasDelayException *e = delay_excp(ctx, exc); + tcg_gen_brcond_i64(tcg_invert_cond(ctx->null_cond.c), + ctx->null_cond.a0, ctx->null_cond.a1, e->lab); + ctx->null_cond = cond_make_f(); + } + return true; } static bool gen_illegal(DisasContext *ctx) @@ -4696,6 +4733,19 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) default: g_assert_not_reached(); } + + for (DisasDelayException *e = ctx->delay_excp_list; e ; e = e->next) { + gen_set_label(e->lab); + if (e->set_n >= 0) { + tcg_gen_movi_i64(cpu_psw_n, e->set_n); + } + if (e->set_iir) { + tcg_gen_st_i64(tcg_constant_i64(e->insn), tcg_env, + offsetof(CPUHPPAState, cr[CR_IIR])); + } + install_iaq_entries(ctx, &e->iaq_f, &e->iaq_b); + gen_excp_1(e->excp); + } } static void hppa_tr_disas_log(const DisasContextBase *dcbase, From patchwork Mon May 13 07:47:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796524 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884445wra; Mon, 13 May 2024 00:53:31 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUsyaT/TigIsq192P4Uphm7A1bIReoQ/4W6ANLbQTz/JfeWoG22uN6/WEQbpuiNjJUVmrnwL8vfXyx1HEgEGdug X-Google-Smtp-Source: AGHT+IHxGDnOufl3Tf5XPy6g2Y4oxHu/CymHaw59d5bAwIJfFmdKIc4HgJ3smf511dR5YehDX9gm X-Received: by 2002:a05:620a:430d:b0:78e:e45c:cc1a with SMTP id af79cd13be357-792c7601063mr1171688685a.73.1715586811605; Mon, 13 May 2024 00:53:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586811; cv=none; d=google.com; s=arc-20160816; b=y0rZfUIB26epYEeuNCC6Fb5FbcmRhdImtg7bN0p+87QmKFGznyE04dmmpiYAFTWK/y 217qva9or+jRrDFOlRqAoZhOOyPG8COGC57IOPRAHnK7XcOK8ZLxX7f3JL3eRgjZsicB bt5joDCkwI3EYDhtbFVKaJG5MlGvNesmIbO9OGhBaaspf5U01ZV9nUyglGIbq5edBrKn HPJkCQ5yxGv9Yh4PcpDYIB3kMRY02+M76S65HIhD3DI9VmrvDNUDUcipWB+zKP/38Qj1 RhM7VOQZKAGevAQIKOM6lDDmjaG62SCbOwrSjCCj0XzPWhF4hAXEk5C8TS0FeJ+IjDVN Iarg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bJ2zWrxauyBUqiQFnwtq38MnWD5HOgNqg9osnBJC91k=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=I+ojCK4hy6HJva78NYL5xf8wm/lSCe0XYGy+RUzhArg3Kh3hhnxhUWYmT66/PAP2Dt EVI2Is95BT/96OslVW2pXVQ2igD55XoWwWGotcgv6Bhdmg/nirNYGr6xtZkEi/Uox8f6 LtEW+h56KvOg3KyDD8JLB1MtLVWYiXd0UXqdKqa3PGw5xKlgS00f+/DVggcf2EAFuISF QwymIYrAWKxaBpipCWnd8aO3ErJLRHzNmY/oyfVZvfE9AIQh22D77dPt/4mSg6+hmu0E 6rF436xSPF9uNnkqqGmamnIV0kmO5WERZsp6c7WDNexN3bBKVtK6GZGHd0RvPejQ395N DKNQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VtCtym0I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 29/45] target/hppa: Use delay_excp for conditional traps Date: Mon, 13 May 2024 09:47:01 +0200 Message-Id: <20240513074717.130949-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/helper.h | 1 - target/hppa/int_helper.c | 2 +- target/hppa/op_helper.c | 7 ------- target/hppa/translate.c | 41 ++++++++++++++++++++++++++++++---------- 4 files changed, 32 insertions(+), 19 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 5900fd70bc..3d0d143aed 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,6 +1,5 @@ DEF_HELPER_2(excp, noreturn, env, int) DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) -DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index a667ee380d..1aa3e88ef1 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -134,13 +134,13 @@ void hppa_cpu_do_interrupt(CPUState *cs) switch (i) { case EXCP_ILL: case EXCP_BREAK: + case EXCP_COND: case EXCP_PRIV_REG: case EXCP_PRIV_OPR: /* IIR set via translate.c. */ break; case EXCP_OVERFLOW: - case EXCP_COND: case EXCP_ASSIST: case EXCP_DTLB_MISS: case EXCP_NA_ITLB_MISS: diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 6cf49f33b7..a8b69fd481 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -49,13 +49,6 @@ void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) } } -void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) -{ - if (unlikely(cond)) { - hppa_dynamic_excp(env, EXCP_COND, GETPC()); - } -} - static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e75e7e5b54..7fa0c86a8f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1116,6 +1116,25 @@ static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, return sv; } +static void gen_tc(DisasContext *ctx, DisasCond *cond) +{ + DisasDelayException *e; + + switch (cond->c) { + case TCG_COND_NEVER: + break; + case TCG_COND_ALWAYS: + gen_excp_iir(ctx, EXCP_COND); + break; + default: + e = delay_excp(ctx, EXCP_COND); + tcg_gen_brcond_i64(cond->c, cond->a0, cond->a1, e->lab); + /* In the non-trap path, the condition is known false. */ + *cond = cond_make_f(); + break; + } +} + static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) @@ -1174,9 +1193,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, /* Emit any conditional trap before any writeback. */ cond = do_cond(ctx, cf, d, dest, uv, sv); if (is_tc) { - tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + gen_tc(ctx, &cond); } /* Write back the result. */ @@ -1195,6 +1212,10 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, { TCGv_i64 tcg_r1, tcg_r2; + if (unlikely(is_tc && a->cf == 1)) { + /* Unconditional trap on condition. */ + return gen_excp_iir(ctx, EXCP_COND); + } if (a->cf) { nullify_over(ctx); } @@ -1210,6 +1231,10 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, { TCGv_i64 tcg_im, tcg_r2; + if (unlikely(is_tc && a->cf == 1)) { + /* Unconditional trap on condition. */ + return gen_excp_iir(ctx, EXCP_COND); + } if (a->cf) { nullify_over(ctx); } @@ -1224,7 +1249,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, TCGv_i64 in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf, bool d) { - TCGv_i64 dest, sv, cb, cb_msb, tmp; + TCGv_i64 dest, sv, cb, cb_msb; unsigned c = cf >> 1; DisasCond cond; @@ -1272,9 +1297,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, /* Emit any conditional trap before any writeback. */ if (is_tc) { - tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + gen_tc(ctx, &cond); } /* Write back the result. */ @@ -1440,9 +1463,7 @@ static void do_unit_addsub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, } if (is_tc) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(tcg_env, tmp); + gen_tc(ctx, &cond); } save_gpr(ctx, rt, dest); From patchwork Mon May 13 07:47:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796508 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883404wra; Mon, 13 May 2024 00:49:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW1LGjiDd+/b2tGEFdZ2Q0abVAAuWIg7JLy89sQ2oyUdnbJhNzB0ywKRZWNUMD1v2yqcqCeCc4WZ4/xNXNI0aa2 X-Google-Smtp-Source: AGHT+IHLFp44DGnHCIhMy1yWrExGQoPZbRoNiMFrcezdynPl57zabUWmYgHBLM0WUcvlrn46xlfS X-Received: by 2002:a05:620a:5e52:b0:790:cc3b:fe65 with SMTP id af79cd13be357-792c7577559mr967561185a.10.1715586572186; Mon, 13 May 2024 00:49:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586572; cv=none; d=google.com; s=arc-20160816; b=Nigde0l60s/XRHQcqYfVs362IB2N9v8ZxmxiQX/TNKHxZsF/Gj4WKHjSa8YboPx5B+ IWYC3EFEHHJKSmFbb7nupKUFaZPghDFMsuxb7nrqj6KIGxwGnt6FYOl4E+segG5YMrkz SR3ZUMb6EMePrO1w14mewYLRBQ8NUunL+1OTtMFJvPcdi4Q1G4iz44ynpw/fIDry1AwE XxBoswNR0oSDoDYFziEN9gkV/2cIudOvddH2wP7HCtxdfnrDRUzSIF51HZhtObZf0zDA IBbLcMAwjuXL369X0CazUGH3YB4Inwyv8mFONj1Jf/yLisbVVf97q4Ld+LIN0dyw1Fat wZEg== ARC-Message-Signature: i=1; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 30/45] target/hppa: Use delay_excp for conditional trap on overflow Date: Mon, 13 May 2024 09:47:02 +0200 Message-Id: <20240513074717.130949-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/helper.h | 1 - target/hppa/int_helper.c | 2 +- target/hppa/op_helper.c | 7 ------- target/hppa/translate.c | 21 +++++++++++++-------- 4 files changed, 14 insertions(+), 17 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 3d0d143aed..c12b48a04a 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,5 +1,4 @@ DEF_HELPER_2(excp, noreturn, env, int) -DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 1aa3e88ef1..97e5f0b9a7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -134,13 +134,13 @@ void hppa_cpu_do_interrupt(CPUState *cs) switch (i) { case EXCP_ILL: case EXCP_BREAK: + case EXCP_OVERFLOW: case EXCP_COND: case EXCP_PRIV_REG: case EXCP_PRIV_OPR: /* IIR set via translate.c. */ break; - case EXCP_OVERFLOW: case EXCP_ASSIST: case EXCP_DTLB_MISS: case EXCP_NA_ITLB_MISS: diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a8b69fd481..66cad78a57 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -42,13 +42,6 @@ G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra) cpu_loop_exit_restore(cs, ra); } -void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) -{ - if (unlikely((target_long)cond < 0)) { - hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC()); - } -} - static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, uint32_t val, uint32_t mask, uintptr_t ra) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7fa0c86a8f..d061b30191 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1135,6 +1135,17 @@ static void gen_tc(DisasContext *ctx, DisasCond *cond) } } +static void gen_tsv(DisasContext *ctx, TCGv_i64 *sv, bool d) +{ + DisasCond cond = do_cond(ctx, /* SV */ 12, d, NULL, NULL, *sv); + DisasDelayException *e = delay_excp(ctx, EXCP_OVERFLOW); + + tcg_gen_brcond_i64(cond.c, cond.a0, cond.a1, e->lab); + + /* In the non-trap path, V is known zero. */ + *sv = tcg_constant_i64(0); +} + static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) @@ -1177,10 +1188,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1, if (is_tsv || cond_need_sv(c)) { sv = do_add_sv(ctx, dest, in1, in2, orig_in1, shift, d); if (is_tsv) { - if (!d) { - tcg_gen_ext32s_i64(sv, sv); - } - gen_helper_tsv(tcg_env, sv); + gen_tsv(ctx, &sv, d); } } @@ -1281,10 +1289,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, if (is_tsv || cond_need_sv(c)) { sv = do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { - if (!d) { - tcg_gen_ext32s_i64(sv, sv); - } - gen_helper_tsv(tcg_env, sv); + gen_tsv(ctx, &sv, d); } } From patchwork Mon May 13 07:47:03 2024 Content-Type: text/plain; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 31/45] linux-user/hppa: Force all code addresses to PRIV_USER Date: Mon, 13 May 2024 09:47:03 +0200 Message-Id: <20240513074717.130949-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The kernel does this along the return path to user mode. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- linux-user/hppa/target_cpu.h | 4 ++-- target/hppa/cpu.h | 3 +++ linux-user/elfload.c | 4 ++-- linux-user/hppa/cpu_loop.c | 14 +++++++------- linux-user/hppa/signal.c | 6 ++++-- target/hppa/cpu.c | 7 +++++-- target/hppa/gdbstub.c | 6 ++++++ target/hppa/translate.c | 4 ++-- 8 files changed, 31 insertions(+), 17 deletions(-) diff --git a/linux-user/hppa/target_cpu.h b/linux-user/hppa/target_cpu.h index aacf3e9e02..4b84422a90 100644 --- a/linux-user/hppa/target_cpu.h +++ b/linux-user/hppa/target_cpu.h @@ -28,8 +28,8 @@ static inline void cpu_clone_regs_child(CPUHPPAState *env, target_ulong newsp, /* Indicate child in return value. */ env->gr[28] = 0; /* Return from the syscall. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; } static inline void cpu_clone_regs_parent(CPUHPPAState *env, unsigned flags) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c37b4e12fb..5a1e720bb6 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -42,6 +42,9 @@ #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) +#define PRIV_KERNEL 0 +#define PRIV_USER 3 + #define TARGET_INSN_START_EXTRA_WORDS 2 /* No need to flush MMU_ABS*_IDX */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b473cda6b4..c1e1511ff2 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1887,8 +1887,8 @@ static inline void init_thread(struct target_pt_regs *regs, static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) { - regs->iaoq[0] = infop->entry; - regs->iaoq[1] = infop->entry + 4; + regs->iaoq[0] = infop->entry | PRIV_USER; + regs->iaoq[1] = regs->iaoq[0] + 4; regs->gr[23] = 0; regs->gr[24] = infop->argv; regs->gr[25] = infop->argc; diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index d5232f37fe..bc093b8fe8 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -129,8 +129,8 @@ void cpu_loop(CPUHPPAState *env) default: env->gr[28] = ret; /* We arrived here by faking the gateway page. Return. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; break; case -QEMU_ERESTARTSYS: case -QEMU_ESIGRETURN: @@ -140,8 +140,8 @@ void cpu_loop(CPUHPPAState *env) case EXCP_SYSCALL_LWS: env->gr[21] = hppa_lws(env); /* We arrived here by faking the gateway page. Return. */ - env->iaoq_f = env->gr[31]; - env->iaoq_b = env->gr[31] + 4; + env->iaoq_f = env->gr[31] | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; break; case EXCP_IMP: force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR, env->iaoq_f); @@ -152,9 +152,9 @@ void cpu_loop(CPUHPPAState *env) case EXCP_PRIV_OPR: /* check for glibc ABORT_INSTRUCTION "iitlbp %r0,(%sr0, %r0)" */ if (env->cr[CR_IIR] == 0x04000000) { - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->iaoq_f); } else { - force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->iaoq_f); } break; case EXCP_PRIV_REG: @@ -170,7 +170,7 @@ void cpu_loop(CPUHPPAState *env) force_sig_fault(TARGET_SIGFPE, 0, env->iaoq_f); break; case EXCP_BREAK: - force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f & ~3); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f); break; case EXCP_DEBUG: force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->iaoq_f); diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c index 682ba25922..f6f094c960 100644 --- a/linux-user/hppa/signal.c +++ b/linux-user/hppa/signal.c @@ -101,7 +101,9 @@ static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc) cpu_hppa_loaded_fr0(env); __get_user(env->iaoq_f, &sc->sc_iaoq[0]); + env->iaoq_f |= PRIV_USER; __get_user(env->iaoq_b, &sc->sc_iaoq[1]); + env->iaoq_b |= PRIV_USER; __get_user(env->cr[CR_SAR], &sc->sc_sar); } @@ -162,8 +164,8 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, unlock_user(fdesc, haddr, 0); haddr = dest; } - env->iaoq_f = haddr; - env->iaoq_b = haddr + 4; + env->iaoq_f = haddr | PRIV_USER; + env->iaoq_b = env->iaoq_f + 4; env->psw_n = 0; return; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index be8c558014..a007de5521 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -32,6 +32,9 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu = HPPA_CPU(cs); +#ifdef CONFIG_USER_ONLY + value |= PRIV_USER; +#endif cpu->env.iaoq_f = value; cpu->env.iaoq_b = value + 4; } @@ -93,8 +96,8 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); #ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f = tb->pc; - cpu->env.iaoq_b = tb->cs_base; + cpu->env.iaoq_f = tb->pc | PRIV_USER; + cpu->env.iaoq_b = tb->cs_base | PRIV_USER; #else /* Recover the IAOQ values from the GVA + PRIV. */ uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 4a965b38d7..0daa52f7af 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -163,12 +163,18 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31); break; case 33: +#ifdef CONFIG_USER_ONLY + val |= PRIV_USER; +#endif env->iaoq_f = val; break; case 34: env->iasq_f = (uint64_t)val << 32; break; case 35: +#ifdef CONFIG_USER_ONLY + val |= PRIV_USER; +#endif env->iaoq_b = val; break; case 36: diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d061b30191..aad5323a53 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2053,7 +2053,7 @@ static void do_page_zero(DisasContext *ctx) tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])); - tcg_gen_ori_i64(next.base, cpu_gr[31], 3); + tcg_gen_ori_i64(next.base, cpu_gr[31], PRIV_USER); install_iaq_entries(ctx, &next, NULL); ctx->base.is_jmp = DISAS_IAQ_N_UPDATED; } @@ -4582,7 +4582,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); #ifdef CONFIG_USER_ONLY - ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); + ctx->privilege = PRIV_USER; ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; From patchwork Mon May 13 07:47:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796515 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1883628wra; Mon, 13 May 2024 00:50:17 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXxMvcVOFhq67PmtCAvJCWuNhTrutgWnUF3wXhrYn6+GwX2ElWpTqCCs4SXnoYZZaU0SX7yWxr2MkDf72Sro+C3 X-Google-Smtp-Source: AGHT+IEh+IQkV67imWBZY0KCxABsHFc/JP74NKY31jHP9gy/CfEQin+EjBR6tWJi/pValXr5/7lQ X-Received: by 2002:a05:620a:15a8:b0:792:c13a:1a80 with SMTP id af79cd13be357-792c75b2e88mr943921885a.44.1715586617176; Mon, 13 May 2024 00:50:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586617; cv=none; d=google.com; s=arc-20160816; b=OwuuanKyBPF1Tq+MykPxLbx0OU0jISVDrARO3viB1INZsj5/zLs4j6z7sSwuBxfFSS JDMzDligLlzRiqcclqjYxhVZlZMiFBTyN2sh7Rx6EPF0LJr0QT1ENfuK2gGbzzpwmlx7 bAAkbBRE9KXEHyX5QIGQc1SHq413u/U7RD56Q/Qu/3HJkej0dwHMUlJCtKifuLP16bNG sh97UzCO3ecT67RH32AjTYm+uvofn6jW0epv9kMIcoEHQeNpvrWnbqMYhRzTtxoH+vgj zKsm6OmBI8S2der6nf0Yk0D/NkiWeCssVumpGcdixsx9BPxSyUhNWxvvjKOEEHPFPhvy 6H2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=p6q1brGiaM7JKUk74R+0kS4pUgiSskJRKzJ4QnaV9A0=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=H5mrp4MYY+4N6irh7t+kpgvkKD4wN2OLmXI+e5/k/aIniTfBrKXsFrDynH3KyYM+2o sFMIJQKfFn8seD9K/IdngRMcgrCwycmqeK7re+Tve4X2mb+dbD7BWZ7rD11AU5ICwWH1 shEEpEExKuD/hLPMCdCys+d+LUj9pnQQrTkDy2+zYdiRIT8iEy9IH1X+z+gT7Y0GkpqK xt0LCETRHwYQsN4MMs8YFdnYB5hqUODqrTUpyAQPCOEgCRPbehUArSa/0d+Eu611mDmS oLd0gZ/kun0YCeK4OG5t3FhvqLziHe8VlJoFJMs/3KYMqQY3VeNx8w6G1G26aVzwODA9 wLOQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AXHlXLpr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 32/45] target/hppa: Store full iaoq_f and page offset of iaoq_b in TB Date: Mon, 13 May 2024 09:47:04 +0200 Message-Id: <20240513074717.130949-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for CF_PCREL. store the iaoq_f in 3 parts: high bits in cs_base, middle bits in pc, and low bits in priv. For iaoq_b, set a bit for either of space or page differing, else the page offset. Install iaq entries before goto_tb. The change to not record the full direct branch difference in TB means that we have to store at least iaoq_b before goto_tb. But we since we'll need both updated before goto_tb for CF_PCREL, do that now. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 2 ++ target/hppa/cpu.c | 72 ++++++++++++++++++----------------------- target/hppa/translate.c | 29 +++++++++-------- 3 files changed, 48 insertions(+), 55 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 5a1e720bb6..1232a4cef2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -341,6 +341,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 +#define CS_BASE_DIFFPAGE (1 << 12) +#define CS_BASE_DIFFSPACE (1 << 13) void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index a007de5521..003af63e20 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -48,36 +48,43 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) } void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) + uint64_t *pcsbase, uint32_t *pflags) { uint32_t flags = env->psw_n * PSW_N; + uint64_t cs_base = 0; + + /* + * TB lookup assumes that PC contains the complete virtual address. + * If we leave space+offset separate, we'll get ITLB misses to an + * incomplete virtual address. This also means that we must separate + * out current cpu privilege from the low bits of IAOQ_F. + */ + *pc = hppa_cpu_get_pc(env_cpu(env)); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + if (hppa_is_pa20(env)) { + cs_base = env->iaoq_f & MAKE_64BIT_MASK(32, 32); + } + + /* + * The only really interesting case is if IAQ_Back is on the same page + * as IAQ_Front, so that we can use goto_tb between the blocks. In all + * other cases, we'll be ending the TranslationBlock with one insn and + * not linking between them. + */ + if (env->iasq_f != env->iasq_b) { + cs_base |= CS_BASE_DIFFSPACE; + } else if ((env->iaoq_f ^ env->iaoq_b) & TARGET_PAGE_MASK) { + cs_base |= CS_BASE_DIFFPAGE; + } else { + cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; + } - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ #ifdef CONFIG_USER_ONLY - *pc = env->iaoq_f & -4; - *cs_base = env->iaoq_b & -4; flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else /* ??? E, T, H, L, B bits need to be here, when implemented. */ flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); - flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc = hppa_cpu_get_pc(env_cpu(env)); - *cs_base = env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a page. - Failure is indicated by a zero difference. */ - if (env->iasq_f == env->iasq_b) { - target_long diff = env->iaoq_b - env->iaoq_f; - if (diff == (int32_t)diff) { - *cs_base |= (uint32_t)diff; - } - } if ((env->sr[4] == env->sr[5]) & (env->sr[4] == env->sr[6]) & (env->sr[4] == env->sr[7])) { @@ -85,6 +92,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, } #endif + *pcsbase = cs_base; *pflags = flags; } @@ -93,25 +101,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, { HPPACPU *cpu = HPPA_CPU(cs); - tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); - -#ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f = tb->pc | PRIV_USER; - cpu->env.iaoq_b = tb->cs_base | PRIV_USER; -#else - /* Recover the IAOQ values from the GVA + PRIV. */ - uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; - target_ulong cs_base = tb->cs_base; - target_ulong iasq_f = cs_base & ~0xffffffffull; - int32_t diff = cs_base; - - cpu->env.iasq_f = iasq_f; - cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; - if (diff) { - cpu->env.iaoq_b = cpu->env.iaoq_f + diff; - } -#endif - + /* IAQ is always up-to-date before goto_tb. */ cpu->env.psw_n = (tb->flags & PSW_N) != 0; } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index aad5323a53..67197e98b3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -769,12 +769,11 @@ static bool use_nullify_skip(DisasContext *ctx) static void gen_goto_tb(DisasContext *ctx, int which, const DisasIAQE *f, const DisasIAQE *b) { + install_iaq_entries(ctx, f, b); if (use_goto_tb(ctx, f, b)) { tcg_gen_goto_tb(which); - install_iaq_entries(ctx, f, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { - install_iaq_entries(ctx, f, b); tcg_gen_lookup_and_goto_ptr(); } } @@ -4575,6 +4574,7 @@ static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + uint64_t cs_base, iaoq_f, iaoq_b; int bound; ctx->cs = cs; @@ -4584,29 +4584,30 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER; ctx->mmu_idx = MMU_USER_IDX; - ctx->iaoq_first = ctx->base.pc_first | ctx->privilege; - ctx->iaq_b.disp = ctx->base.tb->cs_base - ctx->base.pc_first; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; ctx->mmu_idx = (ctx->tb_flags & PSW_D ? PRIV_P_TO_MMU_IDX(ctx->privilege, ctx->tb_flags & PSW_P) : ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); +#endif /* Recover the IAOQ values from the GVA + PRIV. */ - uint64_t cs_base = ctx->base.tb->cs_base; - uint64_t iasq_f = cs_base & ~0xffffffffull; - int32_t diff = cs_base; + cs_base = ctx->base.tb->cs_base; + iaoq_f = cs_base & MAKE_64BIT_MASK(32, 32); + iaoq_f |= ctx->base.pc_first & MAKE_64BIT_MASK(2, 30); + iaoq_f |= ctx->privilege; + ctx->iaoq_first = iaoq_f; - ctx->iaoq_first = (ctx->base.pc_first & ~iasq_f) + ctx->privilege; - - if (diff) { - ctx->iaq_b.disp = diff; - } else { - ctx->iaq_b.base = cpu_iaoq_b; + if (unlikely(cs_base & CS_BASE_DIFFSPACE)) { ctx->iaq_b.space = cpu_iasq_b; + ctx->iaq_b.base = cpu_iaoq_b; + } else if (unlikely(cs_base & CS_BASE_DIFFPAGE)) { + ctx->iaq_b.base = cpu_iaoq_b; + } else { + iaoq_b = (iaoq_f & TARGET_PAGE_MASK) | (cs_base & ~TARGET_PAGE_MASK); + ctx->iaq_b.disp = iaoq_b - iaoq_f; } -#endif ctx->zero = tcg_constant_i64(0); From patchwork Mon May 13 07:47:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796543 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884717wra; Mon, 13 May 2024 00:54:28 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV5DCLbjMYMjcln7ab/jy6moJGoHFak1ELo2opJc857W44htuUhiaV6GJWsrn01vt+dMKM8mLCYAECf2PD/lcC3 X-Google-Smtp-Source: AGHT+IF8xI+LwwOCdBBGUcD9tnQXI0KwfmGz7mMbLNak0PGen3QqXocPty2Mcqk5AP1DeL7tC9pd X-Received: by 2002:a05:620a:269a:b0:792:a77f:fe71 with SMTP id af79cd13be357-792c757440amr1291949085a.2.1715586868271; Mon, 13 May 2024 00:54:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586868; cv=none; d=google.com; s=arc-20160816; b=svyB9GUSqB0Ojvh01LUEgalvPSG4y2SmctLPtlj5umlBj2NdaQ/tFQA4KLpb6uv1/P 1jolyrzApwWQBwF8VGSIlEW/OUANRky+wXx5xe18tkdGzskk8KCtMlmxyVfakot48uxs Wnza9TYYQUxVx+h5H+F7ssGK5yPeXvnHZhddl7zFHQKZJVLuyasQQa8PqU2eci3dXbbe entmJCRNRZZd6M4PSkZBbxRrnEp009ugKPEgVRS6hdiJrttyKCanMSZLZtL4yhDg1vXs fjahEICn5aT1wjPHsXU6oK6mEBr/3fNDDHZB6TBcwG8tyifUr5P+lemx6cpZWWR7UFdJ Mslg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lYICVLRWbF85s9jaYUNXAJVer+rQQT46dzOe8LbGwwQ=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=oFYlaflokN+uThxaklCFeBrbg2mS6oOjyZBUU/1diYCFZB2L9JqNtSG3UxuO8P+S1c hTHnOj6AqhYDKJ72G2PfAYgkTUgARbneG3jXhRw1C8BwdHvQ8uuGerrhLiVdPG8yGLGd w+vbgpU1mGEyoMTCMfo1CocTPGxs+uHJFeR4NDHtkWrBbU+sYNvW7NzJTIsfIpnfig4v cChTMwRE4JooSppmdUdfGWZqh9SfpVrfUjlCK4XBo5JTprlcDaQv6skL74RVNNzjQRTY X4RCfYebUG30vUfoKFdtpdzQmNJS/0D7F4YOvbtkk+DnzGnPJpBaIttjObBljXp+SOzI oRww==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uR+vzGJK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 33/45] target/hppa: Do not mask in copy_iaoq_entry Date: Mon, 13 May 2024 09:47:05 +0200 Message-Id: <20240513074717.130949-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org As with loads and stores, code offsets are kept intact until the full gva is formed. In qemu, this is in cpu_get_tb_cpu_state. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 67197e98b3..abb21b05c8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -637,15 +637,10 @@ static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, const DisasIAQE *src) { - uint64_t mask = gva_offset_mask(ctx->tb_flags); - if (src->base == NULL) { - tcg_gen_movi_i64(dest, (ctx->iaoq_first + src->disp) & mask); - } else if (src->disp == 0) { - tcg_gen_andi_i64(dest, src->base, mask); + tcg_gen_movi_i64(dest, ctx->iaoq_first + src->disp); } else { tcg_gen_addi_i64(dest, src->base, src->disp); - tcg_gen_andi_i64(dest, dest, mask); } } From patchwork Mon May 13 07:47:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796536 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884626wra; Mon, 13 May 2024 00:54:09 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVn2jZ9PrOxXXJQEEoW8YlRJ6GkyQ1Sjs9qHBkC5r5EwuK8YgJxLmdT2KFAI9f79M+ce2u8Gvob+L0M7Co71vkG X-Google-Smtp-Source: AGHT+IFlZ5YyerPYNZV/Ynfm5b34BXyahDCQPdmVVU0mIYrmgDWfwMvnGCM82TOTHvpRBBQ2CLa8 X-Received: by 2002:a05:622a:11d4:b0:43d:f4d3:8990 with SMTP id d75a77b69052e-43dfdaed895mr115853461cf.40.1715586849397; Mon, 13 May 2024 00:54:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586849; cv=none; d=google.com; s=arc-20160816; b=V2JTtkg/8vvSyoXexjjzS44TfunCKp11fCFG30vv9ri8IeV+XXU9tSJI+ACvr7g9Tp pJk7bRwAQY7p2ROmR2FBE3dExPScciKJty+KZbn9P1/gR29GSN9KI56jzMN7tZvFY8h5 q4NOkSX5leJKG+A9Y+5FIMfwEabr9P+WuNHfJ376iwJvADc7zPd8BQbK/EBzAdAt+ZuG 1YvO2/N06E7DsII8EB1ZqoE/VFuELOfN3MdA0kh3dG/T27uyRI6TWSHD6hjkABWzKApb uez4tj/zIDH8R3CvP4HhBW0aEEyK8e8nndwsFZN0LUa2r9aJuw3svE4PACL8S4uB4z8E lYsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5fHOltBHJMUYAs0ifImrgAbY5phtILtBQ88LfAq6uw0=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=hPuPki7HHTDYWYewGoPM5KjD4nKV5mnfmcQNHwwE5xRqI8zuqo4eBGj+UgroEiAI7L X3Gq3oeoXdUqCtu/WVcqJU/fj3fNJe7aYo3C6xRis/wC3SgyqUUszD0CTbwc0K4c/xFy /PrcPhqTXvqDdoBmriVOvAFgxh4gBwaiBl3NoTmtvA8UbLJih1NJUhKGQDpn9TvjaafX fgyHRovRMT4CsFCtrL5cwKGXorhA1df1wT1BstPJ+eZScB8oiXEYOocmdHu8RaLSVKP5 jD2nJ8ksmnt0uKK/u21q9kKTP2DSHxd/0+9Sg+mDd4t47KWzYD5KfSY9t2wZEFES2qpZ GnwQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MjY8TUWc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 34/45] target/hppa: Improve hppa_cpu_dump_state Date: Mon, 13 May 2024 09:47:06 +0200 Message-Id: <20240513074717.130949-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Print both raw IAQ_Front and IAQ_Back as well as the GVAs. Print control registers in system mode. Print floating point register if CPU_DUMP_FPU. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/helper.c | 60 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 6 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 9d217d051c..7d22c248fb 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -102,6 +102,19 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) { +#ifndef CONFIG_USER_ONLY + static const char cr_name[32][5] = { + "RC", "CR1", "CR2", "CR3", + "CR4", "CR5", "CR6", "CR7", + "PID1", "PID2", "CCR", "SAR", + "PID3", "PID4", "IVA", "EIEM", + "ITMR", "ISQF", "IOQF", "IIR", + "ISR", "IOR", "IPSW", "EIRR", + "TR0", "TR1", "TR2", "TR3", + "TR4", "TR5", "TR6", "TR7", + }; +#endif + CPUHPPAState *env = cpu_env(cs); target_ulong psw = cpu_hppa_get_psw(env); target_ulong psw_cb; @@ -117,11 +130,12 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) m = UINT32_MAX; } - qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx - " IIR %0*" PRIx64 "\n", + qemu_fprintf(f, "IA_F %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n" + "IA_B %08" PRIx64 ":%0*" PRIx64 " (" TARGET_FMT_lx ")\n", + env->iasq_f >> 32, w, m & env->iaoq_f, hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), - hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b), - w, m & env->cr[CR_IIR]); + env->iasq_b >> 32, w, m & env->iaoq_b, + hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b)); psw_c[0] = (psw & PSW_W ? 'W' : '-'); psw_c[1] = (psw & PSW_E ? 'E' : '-'); @@ -154,12 +168,46 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags) (i & 3) == 3 ? '\n' : ' '); } #ifndef CONFIG_USER_ONLY + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "%-4s %0*" PRIx64 "%c", + cr_name[i], w, m & env->cr[i], + (i & 3) == 3 ? '\n' : ' '); + } + qemu_fprintf(f, "ISQB %0*" PRIx64 " IOQB %0*" PRIx64 "\n", + w, m & env->cr_back[0], w, m & env->cr_back[1]); for (i = 0; i < 8; i++) { qemu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32), (i & 3) == 3 ? '\n' : ' '); } #endif - qemu_fprintf(f, "\n"); - /* ??? FR */ + if (flags & CPU_DUMP_FPU) { + static const char rm[4][4] = { "RN", "RZ", "R+", "R-" }; + char flg[6], ena[6]; + uint32_t fpsr = env->fr0_shadow; + + flg[0] = (fpsr & R_FPSR_FLG_V_MASK ? 'V' : '-'); + flg[1] = (fpsr & R_FPSR_FLG_Z_MASK ? 'Z' : '-'); + flg[2] = (fpsr & R_FPSR_FLG_O_MASK ? 'O' : '-'); + flg[3] = (fpsr & R_FPSR_FLG_U_MASK ? 'U' : '-'); + flg[4] = (fpsr & R_FPSR_FLG_I_MASK ? 'I' : '-'); + flg[5] = '\0'; + + ena[0] = (fpsr & R_FPSR_ENA_V_MASK ? 'V' : '-'); + ena[1] = (fpsr & R_FPSR_ENA_Z_MASK ? 'Z' : '-'); + ena[2] = (fpsr & R_FPSR_ENA_O_MASK ? 'O' : '-'); + ena[3] = (fpsr & R_FPSR_ENA_U_MASK ? 'U' : '-'); + ena[4] = (fpsr & R_FPSR_ENA_I_MASK ? 'I' : '-'); + ena[5] = '\0'; + + qemu_fprintf(f, "FPSR %08x flag %s enable %s %s\n", + fpsr, flg, ena, rm[FIELD_EX32(fpsr, FPSR, RM)]); + + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "FR%02d %016" PRIx64 "%c", + i, env->fr[i], (i & 3) == 3 ? '\n' : ' '); + } + } + + qemu_fprintf(f, "\n"); } From patchwork Mon May 13 07:47:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796528 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884463wra; Mon, 13 May 2024 00:53:35 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCUI2J/MQ8Y9ncrfikTvKHC81sJsx4tLGIDhGoIdUGp2c8KMzOz46MorzkCy+9rbEQ2fYrRrqIktzxRi4oWn9p0T X-Google-Smtp-Source: AGHT+IE9scxgVi21EDMt7DLdJshv91Y15olw3Yt5z8amtyT3sZzzMGPWTEEi5JErlsCDdZG54XEt X-Received: by 2002:a05:6122:547:b0:4ca:615e:1b61 with SMTP id 71dfb90a1353d-4df8834b24cmr7036708e0c.10.1715586814624; Mon, 13 May 2024 00:53:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586814; cv=none; d=google.com; s=arc-20160816; b=aOMoBiUG4roF3pAtuUCdEjBHEIgIRYHXbEZ/RTqBkJS0Bz/okT2UmOLKE/aWeNU7WY Aa28wjPEc/jz1bZSblGrMbjtRBSglfAmAHEeb1/d9lcvH5RhBVdmVemWgvzQ0XAxoI06 AHqCbwTA0ze1caFR2mMMb0v+P85QTBTPDNDpn+YpUjYDplf+ULoZkSiOQuPN+OGb3fKN hMrepqQR+cafrm5OLS8+TybKKFjmF9lbDjEeyJgjqTfwScUVhNiRSeascqKH1yg3ekpR Oy3YxN4AcewSxy/cH3sj1yVQFYLjukeTLlQSi6DgEBAMJNQoE6Ew10X0Sz+FvB5YkTOg Is5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=E8/1fo4XxPxuANS4fw7f9IOfFNtGCwACN8n5KfI7MiY=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=c/S6GrocHKb4mvHOKy5PUN6+7OBKAX7ExvkoR1RK2/RawKscU3b6K3wCoPo53L/t1P N8cUmybO5AXizqodnaCUDPR99MebAr1dKSReTCH77Fob/Bh30BrB4EW+R5YON2ITQxir VlhO2wmN87izGXGOfcd1aSRXPB9xBc963jfjNzPEWcaqUOq0h3XF3YaGMNuQUay0/6Vm Zv+XPb9a/Epo7xij0XpIozet6T67xFldjLiKR2iH4STRps3BVN4HoL6MKjD3AjSYLhQy /aynUUOUqccmJuim7UBQ1Lyxx9pyfwJqz1Wp0Wv0BCGS5KLRIP0fbvEuTRLEmgXsBBIt /R0A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZLnZ4lTS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 35/45] target/hppa: Split PSW X and B into their own field Date: Mon, 13 May 2024 09:47:07 +0200 Message-Id: <20240513074717.130949-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Generally, both of these bits are cleared at the end of each instruction. By separating these, we will be able to clear both with a single insn, instead of 2 or 3. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/cpu.h | 3 ++- target/hppa/helper.c | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1232a4cef2..f247ad56d7 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -208,7 +208,8 @@ typedef struct CPUArchState { uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ - target_ulong psw; /* All psw bits except the following: */ + uint32_t psw; /* All psw bits except the following: */ + uint32_t psw_xb; /* X and B, in their normal positions */ target_ulong psw_n; /* boolean */ target_long psw_v; /* in most significant bit */ diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 7d22c248fb..b79ddd8184 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -54,7 +54,7 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) psw |= env->psw_n * PSW_N; psw |= (env->psw_v < 0) * PSW_V; - psw |= env->psw; + psw |= env->psw | env->psw_xb; return psw; } @@ -76,8 +76,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) } psw &= ~reserved; - env->psw = psw & (uint32_t)~(PSW_N | PSW_V | PSW_CB); - + env->psw = psw & (uint32_t)~(PSW_B | PSW_N | PSW_V | PSW_X | PSW_CB); + env->psw_xb = psw & (PSW_X | PSW_B); env->psw_n = (psw / PSW_N) & 1; env->psw_v = -((psw / PSW_V) & 1); From patchwork Mon May 13 07:47:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796522 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884204wra; Mon, 13 May 2024 00:52:29 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCU70s/fi1MAjTBBuPjVdz5iadpuyy+bK9uP2dcs2NOrtEU0uzKB3a6W5jf34tkLvOjP+NBfSOgXkI+ebELijVz8 X-Google-Smtp-Source: AGHT+IH5wEC+xW6OqC4A0Jgg8fXRHa6JZMkIoZvB75n6p7vk1pfDUu/CxN7kK04At6LOObG08Xyv X-Received: by 2002:a05:6214:5bc5:b0:6a0:d22f:b668 with SMTP id 6a1803df08f44-6a16816c50fmr114829586d6.26.1715586749628; Mon, 13 May 2024 00:52:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586749; cv=none; d=google.com; s=arc-20160816; b=SnTBmPWA5u9fWSngBPV64/JUg2LLNjjx4A5IhWe5YihtOx9IYcyoJyIO04AxzSCEYW 2SDIUXGKZ5JP+IrW+xtTozYITFEIyc5agwRaPgMXPXFIbE2bEb5XKmxkF3qTNyjEr8AK zgzCNjk8l/lLI72mXPhSAdDfGKagIHKdkqC2c6fLVV9lexrF1nsTHyM4sTuKhyNXDLZV /SgAcAf+I6EcZ71nps5NOcYvRhcEb3O0tboNqZNEMCkYatQ4KeCqibEDhVPWEfgVGXXe fsYEntR/3CHqmJmxoxVhQsiF9jJBfycFnl4gOKNwo+Ksq6pD5QrEhryP8k/3VHIp0Fjo k29g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TlXJccalJ3CeZTGsUdbhgiIr1TQBFsVdUQlxtQmyKbI=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=ZlOzcmltGbWfWEQnlS+24rEUTtjiL23T+fmStzfZkW38Ri1C/pHNwmbMdCpSlFOlaL DNSRcdUdFC52RxoJ91nyLS+FvfpwLL9enaQ428tp7ZklT++c15wjTsJsrnJokBXCrA7r FhJYrjgj9JkGIeUNfADciJHRIfTtoawFkNByOi4P1++BDbMMAbW9k3E0jjqxFr37+hB2 h1fLqd+MMbVXgkIlrhr0AN1Mc6mcmMaQywR1ZAdVuEk7rVF8vWN8+nkamg0QCfUdZPBR BjxFe9/ejpIWdi/OfBWyyEyU8GgWunnV5JlXJ2C5DNfJaBNLcPB5pnv4iyqb+Q/MughR t95A==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KkXgO7y4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 36/45] target/hppa: Manage PSW_X and PSW_B in translator Date: Mon, 13 May 2024 09:47:08 +0200 Message-Id: <20240513074717.130949-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PSW_X is cleared after every instruction, and only set by RFI. PSW_B is cleared after every non-branch, or branch not taken, and only set by taken branches. We can clear both bits with a single store, at most once per TB. Taken branches set PSW_B, at most once per TB. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.c | 10 ++++++--- target/hppa/translate.c | 50 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 003af63e20..5f0df0697a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -50,7 +50,7 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, uint64_t *pcsbase, uint32_t *pflags) { - uint32_t flags = env->psw_n * PSW_N; + uint32_t flags = 0; uint64_t cs_base = 0; /* @@ -80,11 +80,14 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; } + /* ??? E, T, H, L bits need to be here, when implemented. */ + flags |= env->psw_n * PSW_N; + flags |= env->psw_xb; + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + #ifdef CONFIG_USER_ONLY flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; #else - /* ??? E, T, H, L, B bits need to be here, when implemented. */ - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); if ((env->sr[4] == env->sr[5]) & (env->sr[4] == env->sr[6]) & (env->sr[4] == env->sr[7])) { @@ -103,6 +106,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, /* IAQ is always up-to-date before goto_tb. */ cpu->env.psw_n = (tb->flags & PSW_N) != 0; + cpu->env.psw_xb = tb->flags & (PSW_X | PSW_B); } static void hppa_restore_state_to_opc(CPUState *cs, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index abb21b05c8..1a6a140d6f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -84,7 +84,9 @@ typedef struct DisasContext { uint32_t tb_flags; int mmu_idx; int privilege; + uint32_t psw_xb; bool psw_n_nonzero; + bool psw_b_next; bool is_pa20; bool insn_start_updated; @@ -263,6 +265,7 @@ static TCGv_i64 cpu_psw_n; static TCGv_i64 cpu_psw_v; static TCGv_i64 cpu_psw_cb; static TCGv_i64 cpu_psw_cb_msb; +static TCGv_i32 cpu_psw_xb; void hppa_translate_init(void) { @@ -315,6 +318,9 @@ void hppa_translate_init(void) *v->var = tcg_global_mem_new(tcg_env, v->ofs, v->name); } + cpu_psw_xb = tcg_global_mem_new_i32(tcg_env, + offsetof(CPUHPPAState, psw_xb), + "psw_xb"); cpu_iasq_f = tcg_global_mem_new_i64(tcg_env, offsetof(CPUHPPAState, iasq_f), "iasq_f"); @@ -509,6 +515,25 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) #endif } +/* + * Write a value to psw_xb, bearing in mind the known value. + * To be used just before exiting the TB, so do not update the known value. + */ +static void store_psw_xb(DisasContext *ctx, uint32_t xb) +{ + tcg_debug_assert(xb == 0 || xb == PSW_B); + if (ctx->psw_xb != xb) { + tcg_gen_movi_i32(cpu_psw_xb, xb); + } +} + +/* Write a value to psw_xb, and update the known value. */ +static void set_psw_xb(DisasContext *ctx, uint32_t xb) +{ + store_psw_xb(ctx, xb); + ctx->psw_xb = xb; +} + /* Skip over the implementation of an insn that has been nullified. Use this when the insn is too complex for a conditional move. */ static void nullify_over(DisasContext *ctx) @@ -576,6 +601,8 @@ static bool nullify_end(DisasContext *ctx) /* For NEXT, NORETURN, STALE, we can easily continue (or exit). For UPDATED, we cannot update on the nullified path. */ assert(status != DISAS_IAQ_N_UPDATED); + /* Taken branches are handled manually. */ + assert(!ctx->psw_b_next); if (likely(null_lab == NULL)) { /* The current insn wasn't conditional or handled the condition @@ -1842,6 +1869,7 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); ctx->base.is_jmp = DISAS_NORETURN; return true; @@ -1849,20 +1877,24 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, ctx->null_cond.c = TCG_COND_ALWAYS; } ctx->iaq_n = &ctx->iaq_j; + ctx->psw_b_next = true; } else { nullify_over(ctx); install_link(ctx, link, false); if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); } else { nullify_set(ctx, is_n); + store_psw_xb(ctx, PSW_B); gen_goto_tb(ctx, 0, &ctx->iaq_b, &ctx->iaq_j); } nullify_end(ctx); nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 1, &ctx->iaq_b, NULL); ctx->base.is_jmp = DISAS_NORETURN; } @@ -1893,6 +1925,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, n = is_n && disp < 0; if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); next = iaqe_incr(&ctx->iaq_b, 4); gen_goto_tb(ctx, 0, &next, NULL); } else { @@ -1901,6 +1934,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, ctx->null_lab = NULL; } nullify_set(ctx, n); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_b, NULL); } @@ -1912,9 +1946,11 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, next = iaqe_branchi(ctx, disp); if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); + store_psw_xb(ctx, 0); gen_goto_tb(ctx, 1, &next, NULL); } else { nullify_set(ctx, n); + store_psw_xb(ctx, PSW_B); gen_goto_tb(ctx, 1, &ctx->iaq_b, &next); } @@ -1948,6 +1984,7 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, ctx->null_cond.c = TCG_COND_ALWAYS; } ctx->iaq_n = &ctx->iaq_j; + ctx->psw_b_next = true; return true; } @@ -1957,9 +1994,11 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, if (is_n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, &ctx->iaq_j, NULL); nullify_set(ctx, 0); + store_psw_xb(ctx, 0); } else { install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); nullify_set(ctx, is_n); + store_psw_xb(ctx, PSW_B); } tcg_gen_lookup_and_goto_ptr(); @@ -2386,6 +2425,7 @@ static bool trans_halt(DisasContext *ctx, arg_halt *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY + set_psw_xb(ctx, 0); nullify_over(ctx); gen_helper_halt(tcg_env); ctx->base.is_jmp = DISAS_NORETURN; @@ -2397,6 +2437,7 @@ static bool trans_reset(DisasContext *ctx, arg_reset *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY + set_psw_xb(ctx, 0); nullify_over(ctx); gen_helper_reset(tcg_env); ctx->base.is_jmp = DISAS_NORETURN; @@ -2791,6 +2832,9 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ /* No need to check for supervisor, as userland can only pause until the next timer interrupt. */ + + set_psw_xb(ctx, 0); + nullify_over(ctx); /* Advance the instruction queue. */ @@ -4575,6 +4619,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; ctx->tb_flags = ctx->base.tb->flags; ctx->is_pa20 = hppa_is_pa20(cpu_env(cs)); + ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B); #ifdef CONFIG_USER_ONLY ctx->privilege = PRIV_USER; @@ -4661,6 +4706,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) */ ctx->iaq_n = NULL; memset(&ctx->iaq_j, 0, sizeof(ctx->iaq_j)); + ctx->psw_b_next = false; if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) { ctx->null_cond.c = TCG_COND_NEVER; @@ -4673,6 +4719,10 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ret = ctx->base.is_jmp; assert(ctx->null_lab == NULL); } + + if (ret != DISAS_NORETURN) { + set_psw_xb(ctx, ctx->psw_b_next ? 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 37/45] target/hppa: Implement PSW_B Date: Mon, 13 May 2024 09:47:09 +0200 Message-Id: <20240513074717.130949-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PSW_B causes B,GATE to trap as an illegal instruction, removing the sequential execution test that was merely an approximation. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/translate.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1a6a140d6f..2d8410b8ea 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2061,11 +2061,8 @@ static void do_page_zero(DisasContext *ctx) g_assert_not_reached(); } - /* Check that we didn't arrive here via some means that allowed - non-sequential instruction execution. Normally the PSW[B] bit - detects this by disallowing the B,GATE instruction to execute - under such conditions. */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != 4) { + /* If PSW[B] is set, the B,GATE insn would trap. */ + if (ctx->psw_xb & PSW_B) { goto do_sigill; } @@ -3964,23 +3961,13 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { int64_t disp = a->disp; - nullify_over(ctx); - - /* Make sure the caller hasn't done something weird with the queue. - * ??? This is not quite the same as the PSW[B] bit, which would be - * expensive to track. Real hardware will trap for - * b gateway - * b gateway+4 (in delay slot of first branch) - * However, checking for a non-sequential instruction queue *will* - * diagnose the security hole - * b gateway - * b evil - * in which instructions at evil would run with increased privs. - */ - if (iaqe_variable(&ctx->iaq_b) || ctx->iaq_b.disp != ctx->iaq_f.disp + 4) { + /* Trap if PSW[B] is set. */ + if (ctx->psw_xb & PSW_B) { return gen_illegal(ctx); } + nullify_over(ctx); + #ifndef CONFIG_USER_ONLY if (ctx->tb_flags & PSW_C) { int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next); From patchwork Mon May 13 07:47:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796526 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884459wra; Mon, 13 May 2024 00:53:33 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV05tmLOTjlnyVASYb5P5tjekxlbJB6imBP7Gk3Whh2BNaQ/J4/d/3CmvnZBB4+lwvEWc1RvCBKJgcNP0TuybXF X-Google-Smtp-Source: AGHT+IGqQkyqBdEmhCbuv0DiOL2Yo5mI8LgV1EVHjktzSv8dHi0DUR44W/4QFmlJzPtzW09btGyD X-Received: by 2002:a05:620a:45a3:b0:790:ef5d:25ae with SMTP id af79cd13be357-792c75f4541mr1329830585a.56.1715586813635; Mon, 13 May 2024 00:53:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586813; cv=none; d=google.com; s=arc-20160816; b=ltRhJYUc8tf2IkliOtsFpa44By+yVk8L3pTjKJCp7wyhJIoIzThtMzrN8vYaAG9mvt wgCtljqNQI334CAH0JhZNlNfqs2ynAeE7N81qKCQlPPy9J/sNs0Oq8wXlmZuK/XYmgnU X7upk9j02dfZy4eo7vOVoo9BUfXzQikdn+d9Pky2JgtP1wLExLX6njYSbaHMSbzxwoQq l3xUKYW1sSKQP+P4wXZ34Ek3HwliFe/oeYm/9rJSTkymlr0W/BRheph0DHy/qrniEq3b kwCZlWcSgrgv14d02RH35OeUbsF9MwR/BTnHX3S6UVS9/gMgZeR5LWlwj4oc+bZpWQjl I6UQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IqZwbuhaC0QOpVi9GDZS/pvS08Z41AQGVLa7yPdeApE=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=jNqMYyxzkeN9r6kmv+mSvpLJ3j/vptDzzVwzn3dp2X8tK8T+kIkqof82W31xUtGbTm tTMWE2xrqJmhZBvqbnhUMb1LE7hsQtFoI00I6l3UiToCTsTboeMvFfOUGUAO3t8kQOwd 0PDxO+f86OC3+cwcGmJjQtvX07lD3MYgRAMxjmkPOfui8KOnpsfHoQRzQLvemGHYMs0N eLtCK4+Vvmr4vowO8EJ3MY6jbXhdXuEFSJQ0HvsYHZDAEolqFZw+Jy+K7EnuTnAGKnKg KyEGEwKePsiLyn8SCzJyOuZiUJ/BWSO/9IaVJRdiFlVPOcoB7WfsrMQqB8oBvKPrh6D3 q+AQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="W/yVSJkd"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 38/45] target/hppa: Implement PSW_X Date: Mon, 13 May 2024 09:47:10 +0200 Message-Id: <20240513074717.130949-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use PAGE_WRITE_INV to temporarily enable write permission on for a given page, driven by PSW_X being set. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/mem_helper.c | 46 +++++++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index d09877afd7..ca7bbe0a7c 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -296,30 +296,38 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } - /* In reverse priority order, check for conditions which raise faults. - As we go, remove PROT bits that cover the condition we want to check. - In this way, the resulting PROT will force a re-check of the - architectural TLB entry for the next access. */ - if (unlikely(!ent->d)) { - if (type & PAGE_WRITE) { - /* The D bit is not set -- TLB Dirty Bit Fault. */ - ret = EXCP_TLB_DIRTY; - } - prot &= PAGE_READ | PAGE_EXEC; - } - if (unlikely(ent->b)) { - if (type & PAGE_WRITE) { - /* The B bit is set -- Data Memory Break Fault. */ - ret = EXCP_DMB; - } - prot &= PAGE_READ | PAGE_EXEC; - } + /* + * In priority order, check for conditions which raise faults. + * Remove PROT bits that cover the condition we want to check, + * so that the resulting PROT will force a re-check of the + * architectural TLB entry for the next access. + */ if (unlikely(ent->t)) { + prot &= PAGE_EXEC; if (!(type & PAGE_EXEC)) { /* The T bit is set -- Page Reference Fault. */ ret = EXCP_PAGE_REF; } - prot &= PAGE_EXEC; + } else if (!ent->d) { + prot &= PAGE_READ | PAGE_EXEC; + if (type & PAGE_WRITE) { + /* The D bit is not set -- TLB Dirty Bit Fault. */ + ret = EXCP_TLB_DIRTY; + } + } else if (unlikely(ent->b)) { + prot &= PAGE_READ | PAGE_EXEC; + if (type & PAGE_WRITE) { + /* + * The B bit is set -- Data Memory Break Fault. + * Except when PSW_X is set, allow this single access to succeed. + * The write bit will be invalidated for subsequent accesses. + */ + if (env->psw_xb & PSW_X) { + prot |= PAGE_WRITE_INV; + } else { + ret = EXCP_DMB; + } + } } egress: From patchwork Mon May 13 07:47:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796531 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884524wra; Mon, 13 May 2024 00:53:46 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXhC3hPkXjRX2EoWhw7dDFGBCxu3AFQPQyTOkeAun8dCL++OmiWworh/6ipMaLvWjjcV3V5ee5Bxpufg5Kczteg X-Google-Smtp-Source: AGHT+IG9Yzgdrn935BITFM7ATSfsnp93D8tsmxg15AHS/QqvVSyyP6exhRZQn2aGTBO3QFAZCT/1 X-Received: by 2002:a05:622a:1825:b0:43a:4882:861f with SMTP id d75a77b69052e-43dfdac2e45mr93471681cf.3.1715586826248; Mon, 13 May 2024 00:53:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586826; cv=none; d=google.com; s=arc-20160816; b=tmTiR8YfJFrVqExaH3mFKjlRDppqRXtEw7pWI7VIglk1D/NxAmNzSl8amZIIFan4cb FgXgYi6RowZYCOoAhYDWDHLHeEknyeC2zZn1wom9osgJiAIhFRQ9OLwyj52AukCdUTt8 EXqLVE7upeWpWPMhS/J3TWcUN7eCz+lsWw7mfHEkvkSIJEtSV5Bgc5+As6cDyM//HhoZ uBBOHYzLcQNbUF0GxcxNN4OuGzB+bXUGvIOqLsBJwtg1U8NLdI7lnNnFUUMTtzNL1U9C f20qlXDQi4kYABl3uLHXc9AN5L/6QVb6AGYc4lsjS8n/tjBaPsTVPtszl78QRE0cCpdD ClOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=K+T+i0JeoH/+z/Q00QyoJ5KqjEw3NPpVieDyHAHvdI0=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=Ce33mK452uQWqCs7wRDSh0zvfwA5JyXWNskwlyevbP4hd4xwVMZpp8CscE5s8Z82SC SY05jHeBPBeYNc1QB6RhSbel5ydJKPyLpapqQv5p80Jim7l+d4B8uwwTcWX7ftcbeJzw sR/T6Il/y95mluuCpDbv71QT0qDSLamH9WY2rtvksFpZtsvHZgP3YIFyR7cxS9IMU2Jg y5xWbBVCtlmo5TdC/NY0sJLZ3pFRlP/aPw9AiI8QGFr0v1Gxe9jdXWAyXxJPrSeu5xY4 97tDsvL50qw+OtVgK+ybw7+dZBFeKMjHv09bpNJjQ73slnpLdqHv4s3tnLg0T0RuBK1M Mskg==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RJ5JCPR1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41fccee9318sm148204765e9.30.2024.05.13.00.47.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:47:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 39/45] target/hppa: Drop tlb_entry return from hppa_get_physical_address Date: Mon, 13 May 2024 09:47:11 +0200 Message-Id: <20240513074717.130949-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The return-by-reference is never used. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Helge Deller --- target/hppa/cpu.h | 3 +-- target/hppa/int_helper.c | 2 +- target/hppa/mem_helper.c | 19 ++++--------------- target/hppa/op_helper.c | 3 +-- 4 files changed, 7 insertions(+), 20 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f247ad56d7..78ab0adcd0 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -371,8 +371,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void hppa_cpu_do_interrupt(CPUState *cpu); bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot, - HPPATLBEntry **tlb_entry); + int type, hwaddr *pphys, int *pprot); void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 97e5f0b9a7..b82f32fd12 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -167,7 +167,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr); t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX, - 0, &paddr, &prot, NULL); + 0, &paddr, &prot); if (t >= 0) { /* We can't re-load the instruction. */ env->cr[CR_IIR] = 0; diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index ca7bbe0a7c..2929226874 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -197,18 +197,13 @@ static int match_prot_id64(CPUHPPAState *env, uint32_t access_id) } int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, - int type, hwaddr *pphys, int *pprot, - HPPATLBEntry **tlb_entry) + int type, hwaddr *pphys, int *pprot) { hwaddr phys; int prot, r_prot, w_prot, x_prot, priv; HPPATLBEntry *ent; int ret = -1; - if (tlb_entry) { - *tlb_entry = NULL; - } - /* Virtual translation disabled. Map absolute to physical. */ if (MMU_IDX_MMU_DISABLED(mmu_idx)) { switch (mmu_idx) { @@ -238,10 +233,6 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, goto egress; } - if (tlb_entry) { - *tlb_entry = ent; - } - /* We now know the physical address. */ phys = ent->pa + (addr - ent->itree.start); @@ -350,7 +341,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) cpu->env.psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); excp = hppa_get_physical_address(&cpu->env, addr, mmu_idx, 0, - &phys, &prot, NULL); + &phys, &prot); /* Since we're translating for debugging, the only error that is a hard error is no translation at all. Otherwise, while a real cpu @@ -432,7 +423,6 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, { HPPACPU *cpu = HPPA_CPU(cs); CPUHPPAState *env = &cpu->env; - HPPATLBEntry *ent; int prot, excp, a_prot; hwaddr phys; @@ -448,8 +438,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, break; } - excp = hppa_get_physical_address(env, addr, mmu_idx, - a_prot, &phys, &prot, &ent); + excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, &phys, &prot); if (unlikely(excp >= 0)) { if (probe) { return false; @@ -690,7 +679,7 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) int prot, excp; excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0, - &phys, &prot, NULL); + &phys, &prot); if (excp >= 0) { if (excp == EXCP_DTLB_MISS) { excp = EXCP_NA_DTLB_MISS; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 66cad78a57..7f79196fff 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -334,8 +334,7 @@ target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, } mmu_idx = PRIV_P_TO_MMU_IDX(level, env->psw & PSW_P); - excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, - &prot, NULL); + excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, &prot); if (excp >= 0) { cpu_restore_state(env_cpu(env), GETPC()); hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); From patchwork Mon May 13 07:47:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796533 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884577wra; Mon, 13 May 2024 00:53:55 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCV5fTdO5X2v9GI4fRQNwwQxZ9GBYNSElRkxYa9ZwcAd+KtLi+KLJyXt0gAKc3yWqfJ+giV7yCBz3QUrbkALvL9y X-Google-Smtp-Source: AGHT+IHDy5nuiyZfctM20cUSeptdvCWiDCvgroquMEEVOO6yu4srO3aJnPCH5vFxsBwz5Vtc20Hn X-Received: by 2002:a05:6214:3218:b0:6a0:cb53:a78 with SMTP id 6a1803df08f44-6a1681f36fcmr113269696d6.8.1715586835331; Mon, 13 May 2024 00:53:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586835; cv=none; d=google.com; s=arc-20160816; b=SbW8culbXS0lIfF8ogACUIotqbUp6wGki927+V7yg+jsgauHhh4WXXUihMtMe5oTy9 WaJ/v468egiFA0KRO+R1HkaWSE0cohzJaMoLh0tbX9cbqTq/zAuKe3Pcskp5TYJO2WOx 6LQrhz4xdlOO79FrmCmppXyhB1OopXBaGagXdZIaqSWx/Dc1xpmQtI4Yu3JH35k+0hkX 1hIOVUId+KhxDuwL+VX6BWEqWJAmcFfdrk6GbHCooyQPKDhVQDSfJ6ftpSnEIBDTpqOV 20+VwtH5K0P5Z7nocoNAl8sz/vPhFIL/M9Xn3cNv6tFQs5xu0PJpANgtEtXFVwyKSSNZ K2hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3FDffdEHv+AM3yGjV7Jyc3t/YLBxETSVfvDP/Ffczzk=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=00ZyB9bPUBl4l90gnTt0eWD+3Rz9TaIxgZwMPZ6L9D2QNgoXttJEyitmfKP0B5Azre 8s4drVIrmdzy/HFPg5aDUu4zL/JwCAKOLfA9IgOgXQnvz2NWdywafZkoRwzdHdxeTpjz QBIclJn6rRcw1jMKzFUkk8YpB6xpaKCncppwUF9npiWQh09WA3aqLO7xt+/CBIQDgmJL d/MIuO/tHtp8QjOrbpzvQbXNVz5nT/TmZiNAHIlR4QKhqXc17r76yIDYcmOedz+Xhqea 4wA/C3pSrlS3GGOihEpHsf9tt44dtKyYd8VBYhqAbAgrbXXWqgmZiV6P4iQyvAK4POz4 cV2w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QK8wlain; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 40/45] target/hppa: Adjust priv for B,GATE at runtime Date: Mon, 13 May 2024 09:47:12 +0200 Message-Id: <20240513074717.130949-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Do not compile in the priv change based on the first translation; look up the PTE at execution time. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 1 - target/hppa/helper.h | 1 + target/hppa/mem_helper.c | 34 +++++++++++++++++++++++++++------- target/hppa/translate.c | 36 +++++++++++++++++++----------------- 4 files changed, 47 insertions(+), 25 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 78ab0adcd0..2bcb3b602b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -380,7 +380,6 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, extern const MemoryRegionOps hppa_io_eir_ops; extern const VMStateDescription vmstate_hppa_cpu; void hppa_cpu_alarm_timer(void *); -int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); #endif G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); diff --git a/target/hppa/helper.h b/target/hppa/helper.h index c12b48a04a..de411923d9 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -86,6 +86,7 @@ DEF_HELPER_1(halt, noreturn, env) DEF_HELPER_1(reset, noreturn, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) +DEF_HELPER_FLAGS_2(b_gate_priv, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tl, env, tl) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 2929226874..b984f730aa 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -691,13 +691,6 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) return phys; } -/* Return the ar_type of the TLB at VADDR, or -1. */ -int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr) -{ - HPPATLBEntry *ent = hppa_find_tlb(env, vaddr); - return ent ? ent->ar_type : -1; -} - /* * diag_btlb() emulates the PDC PDC_BLOCK_TLB firmware call to * allow operating systems to modify the Block TLB (BTLB) entries. @@ -793,3 +786,30 @@ void HELPER(diag_btlb)(CPUHPPAState *env) break; } } + +uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f) +{ + uint64_t gva = hppa_form_gva(env, env->iasq_f, iaoq_f); + HPPATLBEntry *ent = hppa_find_tlb(env, gva); + + if (ent == NULL) { + raise_exception_with_ior(env, EXCP_ITLB_MISS, GETPC(), gva, false); + } + + /* + * There should be no need to check page permissions, as that will + * already have been done by tb_lookup via get_page_addr_code. + * All we need at this point is to check the ar_type. + * + * No change for non-gateway pages or for priv decrease. + */ + if (ent->ar_type & 4) { + int old_priv = iaoq_f & 3; + int new_priv = ent->ar_type & 3; + + if (new_priv < old_priv) { + iaoq_f = (iaoq_f & -4) | new_priv; + } + } + return iaoq_f; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2d8410b8ea..fa79116d5b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3960,6 +3960,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { int64_t disp = a->disp; + bool indirect = false; /* Trap if PSW[B] is set. */ if (ctx->psw_xb & PSW_B) { @@ -3969,24 +3970,22 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) nullify_over(ctx); #ifndef CONFIG_USER_ONLY - if (ctx->tb_flags & PSW_C) { - int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next); - /* If we could not find a TLB entry, then we need to generate an - ITLB miss exception so the kernel will provide it. - The resulting TLB fill operation will invalidate this TB and - we will re-translate, at which point we *will* be able to find - the TLB entry and determine if this is in fact a gateway page. */ - if (type < 0) { - gen_excp(ctx, EXCP_ITLB_MISS); - return true; - } - /* No change for non-gateway pages or for priv decrease. */ - if (type >= 4 && type - 4 < ctx->privilege) { - disp -= ctx->privilege; - disp += type - 4; - } + if (ctx->privilege == 0) { + /* Privilege cannot decrease. */ + } else if (!(ctx->tb_flags & PSW_C)) { + /* With paging disabled, priv becomes 0. */ + disp -= ctx->privilege; } else { - disp -= ctx->privilege; /* priv = 0 */ + /* Adjust the dest offset for the privilege change from the PTE. */ + TCGv_i64 off = tcg_temp_new_i64(); + + gen_helper_b_gate_priv(off, tcg_env, + tcg_constant_i64(ctx->iaoq_first + + ctx->iaq_f.disp)); + + ctx->iaq_j.base = off; + ctx->iaq_j.disp = disp + 8; + indirect = true; } #endif @@ -3999,6 +3998,9 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) save_gpr(ctx, a->l, tmp); } + if (indirect) { + return do_ibranch(ctx, 0, false, a->n); + } return do_dbranch(ctx, disp, 0, a->n); } From patchwork Mon May 13 07:47:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796530 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884472wra; 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 41/45] target/hppa: Implement CF_PCREL Date: Mon, 13 May 2024 09:47:13 +0200 Message-Id: <20240513074717.130949-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that the groundwork has been laid, enabling CF_PCREL within the translator proper is a simple matter of updating copy_iaoq_entry and install_iaq_entries. We also need to modify the unwind info, since we no longer have absolute addresses to install. As expected, this reduces the runtime overhead of compilation when running a Linux kernel with address space randomization enabled. Signed-off-by: Richard Henderson Reviewed-by: Helge Deller --- target/hppa/cpu.c | 19 ++++++------ target/hppa/translate.c | 68 ++++++++++++++++++++++++++++------------- 2 files changed, 55 insertions(+), 32 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5f0df0697a..f0507874ce 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -62,10 +62,6 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, *pc = hppa_cpu_get_pc(env_cpu(env)); flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - if (hppa_is_pa20(env)) { - cs_base = env->iaoq_f & MAKE_64BIT_MASK(32, 32); - } - /* * The only really interesting case is if IAQ_Back is on the same page * as IAQ_Front, so that we can use goto_tb between the blocks. In all @@ -113,19 +109,19 @@ static void hppa_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - HPPACPU *cpu = HPPA_CPU(cs); + CPUHPPAState *env = cpu_env(cs); - cpu->env.iaoq_f = data[0]; - if (data[1] != (target_ulong)-1) { - cpu->env.iaoq_b = data[1]; + env->iaoq_f = (env->iaoq_f & TARGET_PAGE_MASK) | data[0]; + if (data[1] != INT32_MIN) { + env->iaoq_b = env->iaoq_f + data[1]; } - cpu->env.unwind_breg = data[2]; + env->unwind_breg = data[2]; /* * Since we were executing the instruction at IAOQ_F, and took some * sort of action that provoked the cpu_restore_state, we can infer * that the instruction was not nullified. */ - cpu->env.psw_n = 0; + env->psw_n = 0; } static bool hppa_cpu_has_work(CPUState *cs) @@ -191,6 +187,9 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) hppa_ptlbe(&cpu->env); } #endif + + /* Use pc-relative instructions always to simplify the translator. */ + tcg_cflags_set(cs, CF_PCREL); } static void hppa_cpu_initfn(Object *obj) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index fa79116d5b..79e29d722f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -47,7 +47,7 @@ typedef struct DisasIAQE { TCGv_i64 space; /* IAOQ base; may be null for relative address. */ TCGv_i64 base; - /* IAOQ addend; if base is null, relative to ctx->iaoq_first. */ + /* IAOQ addend; if base is null, relative to cpu_iaoq_f. */ int64_t disp; } DisasIAQE; @@ -664,11 +664,7 @@ static DisasIAQE iaqe_next_absv(DisasContext *ctx, TCGv_i64 var) static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, const DisasIAQE *src) { - if (src->base == NULL) { - tcg_gen_movi_i64(dest, ctx->iaoq_first + src->disp); - } else { - tcg_gen_addi_i64(dest, src->base, src->disp); - } + tcg_gen_addi_i64(dest, src->base ? : cpu_iaoq_f, src->disp); } static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, @@ -680,8 +676,28 @@ static void install_iaq_entries(DisasContext *ctx, const DisasIAQE *f, b_next = iaqe_incr(f, 4); b = &b_next; } - copy_iaoq_entry(ctx, cpu_iaoq_f, f); - copy_iaoq_entry(ctx, cpu_iaoq_b, b); + + /* + * There is an edge case + * bv r0(rN) + * b,l disp,r0 + * for which F will use cpu_iaoq_b (from the indirect branch), + * and B will use cpu_iaoq_f (from the direct branch). + * In this case we need an extra temporary. + */ + if (f->base != cpu_iaoq_b) { + copy_iaoq_entry(ctx, cpu_iaoq_b, b); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + } else if (f->base == b->base) { + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, b->disp - f->disp); + } else { + TCGv_i64 tmp = tcg_temp_new_i64(); + copy_iaoq_entry(ctx, tmp, b); + copy_iaoq_entry(ctx, cpu_iaoq_f, f); + tcg_gen_mov_i64(cpu_iaoq_b, tmp); + } + if (f->space) { tcg_gen_mov_i64(cpu_iasq_f, f->space); } @@ -3979,9 +3995,8 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) /* Adjust the dest offset for the privilege change from the PTE. */ TCGv_i64 off = tcg_temp_new_i64(); - gen_helper_b_gate_priv(off, tcg_env, - tcg_constant_i64(ctx->iaoq_first - + ctx->iaq_f.disp)); + copy_iaoq_entry(ctx, off, &ctx->iaq_f); + gen_helper_b_gate_priv(off, tcg_env, off); ctx->iaq_j.base = off; ctx->iaq_j.disp = disp + 8; @@ -4602,7 +4617,7 @@ static bool trans_diag_unimp(DisasContext *ctx, arg_diag_unimp *a) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); - uint64_t cs_base, iaoq_f, iaoq_b; + uint64_t cs_base; int bound; ctx->cs = cs; @@ -4621,12 +4636,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) : ctx->tb_flags & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX); #endif - /* Recover the IAOQ values from the GVA + PRIV. */ cs_base = ctx->base.tb->cs_base; - iaoq_f = cs_base & MAKE_64BIT_MASK(32, 32); - iaoq_f |= ctx->base.pc_first & MAKE_64BIT_MASK(2, 30); - iaoq_f |= ctx->privilege; - ctx->iaoq_first = iaoq_f; + ctx->iaoq_first = ctx->base.pc_first + ctx->privilege; if (unlikely(cs_base & CS_BASE_DIFFSPACE)) { ctx->iaq_b.space = cpu_iasq_b; @@ -4634,8 +4645,9 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) } else if (unlikely(cs_base & CS_BASE_DIFFPAGE)) { ctx->iaq_b.base = cpu_iaoq_b; } else { - iaoq_b = (iaoq_f & TARGET_PAGE_MASK) | (cs_base & ~TARGET_PAGE_MASK); - ctx->iaq_b.disp = iaoq_b - iaoq_f; + uint64_t iaoq_f_pgofs = ctx->iaoq_first & ~TARGET_PAGE_MASK; + uint64_t iaoq_b_pgofs = cs_base & ~TARGET_PAGE_MASK; + ctx->iaq_b.disp = iaoq_b_pgofs - iaoq_f_pgofs; } ctx->zero = tcg_constant_i64(0); @@ -4662,11 +4674,23 @@ static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + uint64_t iaoq_f, iaoq_b; + int64_t diff; tcg_debug_assert(!iaqe_variable(&ctx->iaq_f)); - tcg_gen_insn_start(ctx->iaoq_first + ctx->iaq_f.disp, - (iaqe_variable(&ctx->iaq_b) ? -1 : - ctx->iaoq_first + ctx->iaq_b.disp), 0); + + iaoq_f = ctx->iaoq_first + ctx->iaq_f.disp; + if (iaqe_variable(&ctx->iaq_b)) { + diff = INT32_MIN; + } else { + iaoq_b = ctx->iaoq_first + ctx->iaq_b.disp; + diff = iaoq_b - iaoq_f; + /* Direct branches can only produce a 24-bit displacement. */ + tcg_debug_assert(diff == (int32_t)diff); + tcg_debug_assert(diff != INT32_MIN); + } + + tcg_gen_insn_start(iaoq_f & ~TARGET_PAGE_MASK, diff, 0); ctx->insn_start_updated = false; } From patchwork Mon May 13 07:47:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796539 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884660wra; Mon, 13 May 2024 00:54:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCW8l+ZiWQSO+YYcJBgy5zuojFbcRne9N3aLIZ7pC39r7CYio72NfmFpFrKpxOZVvBcrAnUdTlQPcL3zvLuuTehN X-Google-Smtp-Source: AGHT+IFPWOakp4tCuKBLhsU9q6JMJM0IqipbeXLZLa+0LFwZiz+fhn32VoXr4eab9ZgKbT2nkf2Y X-Received: by 2002:a05:6122:4691:b0:4c9:2540:8520 with SMTP id 71dfb90a1353d-4df88285a74mr6476924e0c.1.1715586855126; Mon, 13 May 2024 00:54:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586855; cv=none; d=google.com; s=arc-20160816; b=UOr+ymK9Z5PNNjfpUoEAs80LzkLpuBupkMvKUYKeruhLkeO38xxzmW7xB02bAUKBCT CWz58oQaiYT/ihv7VXQJT/kdLajvC5EOp1URSlA0/USvnRFR4044Cfv7I+sI7lLHgXZC ARWDmMoOD8BfTWrbsgVg0NnP86BExlZXa+DnZF342r2hq0CNZYGFJrDJhwc/hR8CEhz+ 7EF6/q0UeicJFUH//tlvTspPxOzRG9GZsPxCHdllraSkdAjPOnD/kfaHCwMP2tnUsJ7I agfJel+1dllRpU//WHxsNLNNpqyeaVoRBYUCKyEfS6VtyFIQ7oCfAbuJ6RIA1Swy49Pu s74g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OXJrXEo5lvj8nKkiVWwei0sGVNNJi1pj05AdZLYlOuA=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=u4ONilL/Wtlwo268M90eSGyKpw8C/+h4iW9jfYtLbIq6Udzr7Vs+3Xvm35hq6xn3dC 3F2QbCn8alHVZLckTkeRlfBeT0FKCPeoqRT/46FMWln0h1o+FZREvef0gEADeXIJH18u gUNeE6XrrzOtjTXzVxQ3HFNw2KgCkguZRWTVOzgEABqfdZd9zbfqHJ7vLyXsqF0EyZ3t uvfg/EP6n+ELU3HAx3kpzz3fJxJjTaKgSuQcMXxck7qbRy8OBGncLX1M4+iaYEVUMTnY QmBT29oAwKxvbjHxDcFjxSZbp1LGOrHmLrVDC1g/aSAPDCqalZ9vRVc67sJJq8EkpHen k2ig==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Knr9wDdZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 42/45] target/hppa: Implement PSW_T Date: Mon, 13 May 2024 09:47:14 +0200 Message-Id: <20240513074717.130949-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PSW_T enables a trap on taken branches, at the very end of the execution of the branch instruction. Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 4 +-- target/hppa/translate.c | 55 +++++++++++++++++++++++++++++++---------- 2 files changed, 44 insertions(+), 15 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index f0507874ce..2a3b5fc498 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -76,10 +76,10 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; } - /* ??? E, T, H, L bits need to be here, when implemented. */ + /* ??? E, H, L bits need to be here, when implemented. */ flags |= env->psw_n * PSW_N; flags |= env->psw_xb; - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P | PSW_T); #ifdef CONFIG_USER_ONLY flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 79e29d722f..2290dc8533 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1873,6 +1873,23 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, return nullify_end(ctx); } +static bool do_taken_branch_trap(DisasContext *ctx, DisasIAQE *next, bool n) +{ + if (unlikely(ctx->tb_flags & PSW_T)) { + /* + * The X, B and N bits are updated, and the instruction queue + * is advanced before the trap is recognized. + */ + nullify_set(ctx, n); + store_psw_xb(ctx, PSW_B); + install_iaq_entries(ctx, &ctx->iaq_b, next); + gen_excp_1(EXCP_TB); + ctx->base.is_jmp = DISAS_NORETURN; + return true; + } + return false; +} + /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ static bool do_dbranch(DisasContext *ctx, int64_t disp, @@ -1882,6 +1899,9 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, false); + if (do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { + return true; + } if (is_n) { if (use_nullify_skip(ctx)) { nullify_set(ctx, 0); @@ -1898,7 +1918,9 @@ static bool do_dbranch(DisasContext *ctx, int64_t disp, nullify_over(ctx); install_link(ctx, link, false); - if (is_n && use_nullify_skip(ctx)) { + if (do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { + /* done */ + } else if (is_n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); store_psw_xb(ctx, 0); gen_goto_tb(ctx, 0, &ctx->iaq_j, NULL); @@ -1960,7 +1982,9 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, n = is_n && disp >= 0; next = iaqe_branchi(ctx, disp); - if (n && use_nullify_skip(ctx)) { + if (do_taken_branch_trap(ctx, &next, is_n)) { + /* done */ + } else if (n && use_nullify_skip(ctx)) { nullify_set(ctx, 0); store_psw_xb(ctx, 0); gen_goto_tb(ctx, 1, &next, NULL); @@ -1990,6 +2014,9 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, { if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, with_sr0); + if (do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { + return true; + } if (is_n) { if (use_nullify_skip(ctx)) { install_iaq_entries(ctx, &ctx->iaq_j, NULL); @@ -2005,20 +2032,22 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, } nullify_over(ctx); - install_link(ctx, link, with_sr0); - if (is_n && use_nullify_skip(ctx)) { - install_iaq_entries(ctx, &ctx->iaq_j, NULL); - nullify_set(ctx, 0); - store_psw_xb(ctx, 0); - } else { - install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); - nullify_set(ctx, is_n); - store_psw_xb(ctx, PSW_B); + + if (!do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { + if (is_n && use_nullify_skip(ctx)) { + install_iaq_entries(ctx, &ctx->iaq_j, NULL); + nullify_set(ctx, 0); + store_psw_xb(ctx, 0); + } else { + install_iaq_entries(ctx, &ctx->iaq_b, &ctx->iaq_j); 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 43/45] target/hppa: Implement PSW_H, PSW_L Date: Mon, 13 May 2024 09:47:15 +0200 Message-Id: <20240513074717.130949-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/hppa/cpu.c | 4 +-- target/hppa/translate.c | 68 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 64 insertions(+), 8 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2a3b5fc498..f53e5a2788 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -76,10 +76,10 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, cs_base |= env->iaoq_b & ~TARGET_PAGE_MASK; } - /* ??? E, H, L bits need to be here, when implemented. */ + /* ??? E bits need to be here, when implemented. */ flags |= env->psw_n * PSW_N; flags |= env->psw_xb; - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P | PSW_T); + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_H | PSW_L | PSW_P | PSW_T); #ifdef CONFIG_USER_ONLY flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2290dc8533..3ccec023af 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -56,6 +56,7 @@ typedef struct DisasDelayException { TCGLabel *lab; uint32_t insn; bool set_iir; + bool set_b; int8_t set_n; uint8_t excp; /* Saved state at parent insn. */ @@ -745,6 +746,7 @@ static DisasDelayException *delay_excp(DisasContext *ctx, uint8_t excp) e->insn = ctx->insn; e->set_iir = true; e->set_n = ctx->psw_n_nonzero ? 0 : -1; + e->set_b = false; e->excp = excp; e->iaq_f = ctx->iaq_f; e->iaq_b = ctx->iaq_b; @@ -1873,6 +1875,54 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt, return nullify_end(ctx); } +/* + * Since B,GATE can only increase priv, and other indirect branches can + * only decrease priv, we only need to test in one direction. + * If maybe_priv == 0, no priv is possible with the current insn; + * if maybe_priv < 0, priv might increase, otherwise priv might decrease. + */ +static void do_priv_branch_trap(DisasContext *ctx, int maybe_priv, + DisasIAQE *next, bool n) +{ + DisasDelayException *e; + uint32_t psw_bit, excp; + TCGv_i64 new_priv; + TCGCond cond; + + if (likely(maybe_priv == 0)) { + return; + } + if (maybe_priv < 0) { + psw_bit = PSW_H; + excp = EXCP_HPT; + cond = TCG_COND_LTU; + } else { + psw_bit = PSW_L; + excp = EXCP_LPT; + cond = TCG_COND_GTU; + } + if (likely(!(ctx->tb_flags & psw_bit))) { + return; + } + + e = tcg_malloc(sizeof(DisasDelayException)); + memset(e, 0, sizeof(*e)); + e->next = ctx->delay_excp_list; + ctx->delay_excp_list = e; + + e->lab = gen_new_label(); + e->set_n = n ? 1 : ctx->psw_n_nonzero ? 0 : -1; + e->set_b = ctx->psw_xb != PSW_B; + e->excp = excp; + e->iaq_f = ctx->iaq_b; + e->iaq_b = *next; + + new_priv = tcg_temp_new_i64(); + copy_iaoq_entry(ctx, new_priv, next); + tcg_gen_andi_i64(new_priv, new_priv, 3); + tcg_gen_brcondi_i64(cond, new_priv, ctx->privilege, e->lab); +} + static bool do_taken_branch_trap(DisasContext *ctx, DisasIAQE *next, bool n) { if (unlikely(ctx->tb_flags & PSW_T)) { @@ -2010,10 +2060,12 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, * This handles nullification of the branch itself. */ static bool do_ibranch(DisasContext *ctx, unsigned link, - bool with_sr0, bool is_n) + bool with_sr0, bool is_n, int maybe_priv) { if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) { install_link(ctx, link, with_sr0); + + do_priv_branch_trap(ctx, maybe_priv, &ctx->iaq_j, is_n); if (do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { return true; } @@ -2034,6 +2086,7 @@ static bool do_ibranch(DisasContext *ctx, unsigned link, nullify_over(ctx); install_link(ctx, link, with_sr0); + do_priv_branch_trap(ctx, maybe_priv, &ctx->iaq_j, is_n); if (!do_taken_branch_trap(ctx, &ctx->iaq_j, is_n)) { if (is_n && use_nullify_skip(ctx)) { install_iaq_entries(ctx, &ctx->iaq_j, NULL); @@ -3994,7 +4047,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) tcg_gen_addi_i64(ctx->iaq_j.base, load_gpr(ctx, a->b), a->disp); ctx->iaq_j.base = do_ibranch_priv(ctx, ctx->iaq_j.base); - return do_ibranch(ctx, a->l, true, a->n); + return do_ibranch(ctx, a->l, true, a->n, ctx->privilege == 3 ? 0 : 1); } static bool trans_bl(DisasContext *ctx, arg_bl *a) @@ -4043,7 +4096,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) } if (indirect) { - return do_ibranch(ctx, 0, false, a->n); + return do_ibranch(ctx, 0, false, a->n, -1); } return do_dbranch(ctx, disp, 0, a->n); } @@ -4061,7 +4114,7 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) tcg_gen_add_i64(t0, t0, t1); ctx->iaq_j = iaqe_next_absv(ctx, t0); - return do_ibranch(ctx, a->l, false, a->n); + return do_ibranch(ctx, a->l, false, a->n, 0); } else { /* BLR R0,RX is a good way to load PC+8 into RX. */ return do_dbranch(ctx, 0, a->l, a->n); @@ -4082,7 +4135,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) dest = do_ibranch_priv(ctx, dest); ctx->iaq_j = iaqe_next_absv(ctx, dest); - return do_ibranch(ctx, 0, false, a->n); + return do_ibranch(ctx, 0, false, a->n, ctx->privilege == 3 ? 0 : 1); } static bool trans_bve(DisasContext *ctx, arg_bve *a) @@ -4095,7 +4148,7 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) ctx->iaq_j.base = do_ibranch_priv(ctx, b); ctx->iaq_j.disp = 0; - return do_ibranch(ctx, a->l, false, a->n); + return do_ibranch(ctx, a->l, false, a->n, ctx->privilege == 3 ? 0 : 1); } static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) @@ -4853,6 +4906,9 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) if (e->set_n >= 0) { tcg_gen_movi_i64(cpu_psw_n, e->set_n); } + if (e->set_b) { + tcg_gen_movi_i32(cpu_psw_xb, PSW_B); + } if (e->set_iir) { tcg_gen_st_i64(tcg_constant_i64(e->insn), tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); From patchwork Mon May 13 07:47:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796535 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884605wra; Mon, 13 May 2024 00:54:03 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXeD+dOmtax7M8/oh8Za/nTlwX0FVzna0jO9xNx9cUVGQT7RBHMW1OouydliK1xDIP5XYlv0XHWcpO8AO6raSvc X-Google-Smtp-Source: AGHT+IEzTkOVzpgai1IKgHOWS+jbjNQ3l+IrLAPGh4J1H4yc+7VHP6IxrZpE6aMgtbmyXGfdxfwM X-Received: by 2002:a05:6214:5681:b0:6a0:cd45:2588 with SMTP id 6a1803df08f44-6a16825931emr115736616d6.58.1715586842823; Mon, 13 May 2024 00:54:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586842; cv=none; d=google.com; s=arc-20160816; b=z5UxanIq0bbB0XAKRfSIUVD81SJE07Lu2Nsm/XrGXaqGj9DDf/T1MJ3+MtRV7LZd+U lv+Kn+S6mD7lo3Np0cJI6ToPIR99HQdaccB98dF79A6JIH23g7wf8GN9Eo/jIC159TJu ew6zZBYu3MJyNiBlHUjwqnvNp67a8r5kxu5SgTJF/WaAHsyvpZSUYDmIh9naNmesxHIG hIUc0+LX1VGb4SIfpVJbabQv8LGaWEokky0N0eAPej/ETO06FMrnnR/5aaiHZg00XFhG cw8XahUrkJLMrB28Gx5xylFp0h+0kknXnu5KeBVWDOs9AKlW46i4TTnYZO83mQhfAkO+ CTQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=420RbZAGJjbzrfJsdBQyYhnJyXLQSLvrDO7PgYHuwLQ=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=RDGKpL24m9lZIeMUH4U3s7PBWF2zVBqwhIYf+YwC+0qLQBlXmyyu/s+nJQVnqJ2j0J U2JYl+EP/5dNBYazo54pkNb0hadRboCwZlW/PDCKYGseynXzR7xUy6+e6vuG7xhuAKmi uU7I+xzusZ1X/OhueZ5WJZh+cnm52gKjUDiALMaiakPgGLW/4XhkMAe5YgCpJkMrK7mF KiZowoFDPnU44q/wxGsziWzsFkDEXBoSw9WSS2FG1ZH9Hr0Jnb1VMkeHeyQ6InDeR3yx ZSIBXDwV8Iql1jTveoxX9ZPLPYF70Uenzr3qHTCRAo4mZ2Ou3lBwa3q6gIT7N+3niqwy au+w==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bwSD3Ugs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 44/45] target/hppa: Log cpu state at interrupt Date: Mon, 13 May 2024 09:47:16 +0200 Message-Id: <20240513074717.130949-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x129.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This contains all of the information logged before, plus more. Signed-off-by: Richard Henderson --- target/hppa/int_helper.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index b82f32fd12..391f32f27d 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -241,21 +241,22 @@ void hppa_cpu_do_interrupt(CPUState *cs) [EXCP_SYSCALL_LWS] = "syscall-lws", [EXCP_TOC] = "TOC (transfer of control)", }; - static int count; - const char *name = NULL; - char unknown[16]; - if (i >= 0 && i < ARRAY_SIZE(names)) { - name = names[i]; + FILE *logfile = qemu_log_trylock(); + if (logfile) { + const char *name = NULL; + + if (i >= 0 && i < ARRAY_SIZE(names)) { + name = names[i]; + } + if (name) { + fprintf(logfile, "INT: cpu %d %s\n", cs->cpu_index, name); + } else { + fprintf(logfile, "INT: cpu %d unknown %d\n", cs->cpu_index, i); + } + hppa_cpu_dump_state(cs, logfile, 0); + qemu_log_unlock(logfile); } - if (!name) { - snprintf(unknown, sizeof(unknown), "unknown %d", i); - name = unknown; - } - qemu_log("INT %6d: %s @ " TARGET_FMT_lx ":" TARGET_FMT_lx - " for " TARGET_FMT_lx ":" TARGET_FMT_lx "\n", - ++count, name, env->cr[CR_IIASQ], env->cr[CR_IIAOQ], - env->cr[CR_ISR], env->cr[CR_IOR]); } cs->exception_index = -1; } From patchwork Mon May 13 07:47:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 796520 Delivered-To: patch@linaro.org Received: by 2002:a5d:452e:0:b0:34e:ceec:bfcd with SMTP id j14csp1884173wra; Mon, 13 May 2024 00:52:24 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVaKcCI93hHsjCXUbCoavwiWxomU2oF21WDW5zgt93Ivg56qOkoHyNjrSR2t3cb59MGy0rUwzcJoZahmxQy+N3j X-Google-Smtp-Source: AGHT+IHs3puE0tTgRKJdKsMgF+7K4FOaAOxsklvtW6AVw4dC4Hv3EAC3aRG25GXWdGbUUR/LpW4W X-Received: by 2002:a05:622a:19a2:b0:43a:bda4:dd62 with SMTP id d75a77b69052e-43dfdac28f7mr119775481cf.8.1715586744017; Mon, 13 May 2024 00:52:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1715586744; cv=none; d=google.com; s=arc-20160816; b=PWkShBg9CpDpUFYqH3HB9xXvsr/wSXJ9QcJMs3Zz9bh+inYOn7vnzrcMttzwPJvkgo 4bE2Un1NRqd97/2DQb2Wt2lcPmEQV+YJz9leGhiOjU0GvpbdeGqiQwDMdO2QO6xcfWUX odYf9sPAjed/VMLTe9JH0MlwMJAH6ew2lrUjE+x7uziAmw6LRKyK6UZhmZzs7/jpKXvc JCmp7fYUDwzTYC3bbgapRiHWFq8AnH0GJEEK3QQX0xCzGg+7aNWboX4C3dRIr/xW4i5o yDz68hhOZ7x/GmWQLVIayJPI3iERuDiHUtU6QFTtIA5xzBHRc58xvMeYVeoQi39DpD7x b3NQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IL2hAokqpmQr3sSx0rCsqvvhI5ki9eqOu02SaoXaEMQ=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=RdZEEtR3DuaKarz8eZdXxKwgaSqTE6ZNwyyE7PKqrq8WuC2dW1Nx/dR6zWvMdwWm8D q2Uv3QMTHk35FG2FH4AL/4btb5Hip6najoPz3ggtE7MWU4od+F4RKxE8S0ZxPC9mIwcr /OoKybwb5Dh/fbko+52wniLcXIdOG2Ph7WaLcDFqdntyXoAlDj5ggUq+Z1lmOz+NQOEK D8zGlJL6bMcS6yS72Zg2ajQuSnB+YuWuDjeSRUKTigtnkoxldPc+EqYhOLPTZqEdo1KS eiRQWSXukbdQIbGnlpdzgE7MzILF9Nnq43uLYi9sA5P8egvTAmvvwD3uMwrk0KOIBahI Ewag==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wqDvvEL6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[213.97.13.12]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3502b896a50sm10374262f8f.30.2024.05.13.00.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 00:50:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 45/45] target/hppa: Log cpu state on return-from-interrupt Date: Mon, 13 May 2024 09:47:17 +0200 Message-Id: <20240513074717.130949-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240513074717.130949-1-richard.henderson@linaro.org> References: <20240513074717.130949-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Inverse of the logging on taking an interrupt. Signed-off-by: Richard Henderson --- target/hppa/sys_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 22d6c89964..9b43b556fd 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -93,6 +94,17 @@ void HELPER(rfi)(CPUHPPAState *env) env->iaoq_b = env->cr_back[1]; env->iasq_f = (env->cr[CR_IIASQ] << 32) & ~(env->iaoq_f & mask); env->iasq_b = (env->cr_back[0] << 32) & ~(env->iaoq_b & mask); + + if (qemu_loglevel_mask(CPU_LOG_INT)) { + FILE *logfile = qemu_log_trylock(); + if (logfile) { + CPUState *cs = env_cpu(env); + + fprintf(logfile, "RFI: cpu %d\n", cs->cpu_index); + hppa_cpu_dump_state(cs, logfile, 0); + qemu_log_unlock(logfile); + } + } } static void getshadowregs(CPUHPPAState *env)