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Add a new 'snps,p2p3tranok-quirk' DT quirk to dwc3 core for enable the controller transitions directly from phy power state P2 to P3 or from state P3 to P2. Note that this can only be set if the USB3 PHY supports direct p3 to p2 or p2 to p3 conversion. Signed-off-by: joswang --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 1cd0ca90127d..721927495887 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -242,6 +242,13 @@ properties: When set, all HighSpeed bus instances in park mode are disabled. type: boolean + snps,p2p3tranok-quirk: + description: + When set, the controller transitions directly from phy power state + P2 to P3 or from state P3 to P2. Note that this can only be set + if the USB3 PHY supports direct p3 to p2 or p2 to p3 conversion. + type: boolean + snps,dis_metastability_quirk: description: When set, disable metastability workaround. CAUTION! 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This workaround solution disable Clock Gating, sacrificing power consumption for normal operation. Signed-off-by: joswang --- drivers/usb/dwc3/core.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 3a8fbc2d6b99..1df85c505c9e 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -978,11 +978,22 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) * * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based * SOF/ITP Mode Used + * + * WORKAROUND: DWC31 version 2.00a have an issue that would + * cause a CSR read timeout When CSR read coincides with RAM + * Clock Gating Entry. + * + * This workaround solution disable Clock Gating, sacrificing + * power consumption for normal operation. */ if ((dwc->dr_mode == USB_DR_MODE_HOST || dwc->dr_mode == USB_DR_MODE_OTG) && DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; + else if ((dwc->dr_mode == USB_DR_MODE_HOST || + dwc->dr_mode == USB_DR_MODE_OTG) && + DWC3_VER_IS(DWC31, 200A)) + reg |= DWC3_GCTL_DSBLCLKGTNG; else reg &= ~DWC3_GCTL_DSBLCLKGTNG; break; @@ -992,6 +1003,18 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) * will work. Device-mode hibernation is not yet implemented. */ reg |= DWC3_GCTL_GBLHIBERNATIONEN; + + /* + * WORKAROUND: DWC31 version 2.00a have an issue that would + * cause a CSR read timeout When CSR read coincides with RAM + * Clock Gating Entry. + * + * This workaround solution disable Clock Gating, sacrificing + * power consumption for normal operation. + */ + if ((dwc->dr_mode == USB_DR_MODE_HOST || + dwc->dr_mode == USB_DR_MODE_OTG) && DWC3_VER_IS(DWC31, 200A)) + reg |= DWC3_GCTL_DSBLCLKGTNG; break; default: /* nothing */ From patchwork Mon Jun 3 13:02:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: joswang X-Patchwork-Id: 802276 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FB1B1EEE0; Mon, 3 Jun 2024 13:02:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 03 Jun 2024 06:02:28 -0700 (PDT) Received: from localhost ([36.45.244.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f681a8b8c1sm14211685ad.253.2024.06.03.06.02.26 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Jun 2024 06:02:28 -0700 (PDT) From: joswang To: Thinh.Nguyen@synopsys.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, balbi@kernel.org, devicetree@vger.kernel.org, joswang Subject: [PATCH v2, 3/3] usb: dwc3: core: Workaround for CSR read timeout Date: Mon, 3 Jun 2024 21:02:19 +0800 Message-Id: <20240603130219.25825-1-joswang1221@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240601092646.52139-1-joswang1221@gmail.com> References: <20240601092646.52139-1-joswang1221@gmail.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: joswang DWC31 version 2.00a have an issue that would cause a CSR read timeout When CSR read coincides with RAM Clock Gating Entry. This workaround solution disable Clock Gating, sacrificing power consumption for normal operation. Signed-off-by: joswang --- drivers/usb/dwc3/core.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 3a8fbc2d6b99..1df85c505c9e 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -978,11 +978,22 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) * * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based * SOF/ITP Mode Used + * + * WORKAROUND: DWC31 version 2.00a have an issue that would + * cause a CSR read timeout When CSR read coincides with RAM + * Clock Gating Entry. + * + * This workaround solution disable Clock Gating, sacrificing + * power consumption for normal operation. */ if ((dwc->dr_mode == USB_DR_MODE_HOST || dwc->dr_mode == USB_DR_MODE_OTG) && DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; + else if ((dwc->dr_mode == USB_DR_MODE_HOST || + dwc->dr_mode == USB_DR_MODE_OTG) && + DWC3_VER_IS(DWC31, 200A)) + reg |= DWC3_GCTL_DSBLCLKGTNG; else reg &= ~DWC3_GCTL_DSBLCLKGTNG; break; @@ -992,6 +1003,18 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) * will work. Device-mode hibernation is not yet implemented. */ reg |= DWC3_GCTL_GBLHIBERNATIONEN; + + /* + * WORKAROUND: DWC31 version 2.00a have an issue that would + * cause a CSR read timeout When CSR read coincides with RAM + * Clock Gating Entry. + * + * This workaround solution disable Clock Gating, sacrificing + * power consumption for normal operation. + */ + if ((dwc->dr_mode == USB_DR_MODE_HOST || + dwc->dr_mode == USB_DR_MODE_OTG) && DWC3_VER_IS(DWC31, 200A)) + reg |= DWC3_GCTL_DSBLCLKGTNG; break; default: /* nothing */