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Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- v4->v5 - no change v3->v4 - no change v2->v3 - no change --- .../bindings/serial/renesas,scif.yaml | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index f3a3eb2831e9..54f885f720f0 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -9,9 +9,6 @@ title: Renesas Serial Communication Interface with FIFO (SCIF) maintainers: - Geert Uytterhoeven -allOf: - - $ref: serial.yaml# - properties: compatible: oneOf: @@ -161,18 +158,21 @@ required: - clock-names - power-domains -if: - properties: - compatible: - contains: - enum: - - renesas,rcar-gen2-scif - - renesas,rcar-gen3-scif - - renesas,rcar-gen4-scif - - renesas,scif-r9a07g044 -then: - required: - - resets +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-scif + - renesas,rcar-gen3-scif + - renesas,rcar-gen4-scif + - renesas,scif-r9a07g044 + then: + required: + - resets unevaluatedProperties: false From patchwork Tue Jun 4 17:05:10 2024 Content-Type: text/plain; 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This ensures proper handling and configuration of interrupt-related properties across supported platforms. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Conor Dooley --- v4->v5 - Included RB tag from Geert and Conor v3->v4 - Reverted back to v2 version of the patch. - Used suggestion from Krzysztof for interrupts - Restored RB tag from Geert v2->v3 - Listed interrupts and interrupt-names for every SoC in if check --- .../bindings/serial/renesas,scif.yaml | 73 ++++++++++++++----- 1 file changed, 55 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 54f885f720f0..a750676064cf 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -87,11 +87,6 @@ properties: oneOf: - items: - description: A combined interrupt - - items: - - description: Error interrupt - - description: Receive buffer full interrupt - - description: Transmit buffer empty interrupt - - description: Break interrupt - items: - description: Error interrupt - description: Receive buffer full interrupt @@ -99,21 +94,17 @@ properties: - description: Break interrupt - description: Data Ready interrupt - description: Transmit End interrupt + minItems: 4 interrupt-names: - oneOf: - - items: - - const: eri - - const: rxi - - const: txi - - const: bri - - items: - - const: eri - - const: rxi - - const: txi - - const: bri - - const: dri - - const: tei + minItems: 4 + items: + - const: eri + - const: rxi + - const: txi + - const: bri + - const: dri + - const: tei clocks: minItems: 1 @@ -174,6 +165,52 @@ allOf: required: - resets + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen1-scif + - renesas,rcar-gen2-scif + - renesas,rcar-gen3-scif + - renesas,rcar-gen4-scif + then: + properties: + interrupts: + maxItems: 1 + + interrupt-names: false + + - if: + properties: + compatible: + contains: + enum: + - renesas,scif-r7s72100 + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + + interrupt-names: + maxItems: 4 + + - if: + properties: + compatible: + contains: + enum: + - renesas,scif-r7s9210 + - renesas,scif-r9a07g044 + then: + properties: + interrupts: + minItems: 6 + + interrupt-names: + minItems: 6 + unevaluatedProperties: false examples: From patchwork Tue Jun 4 17:05:11 2024 Content-Type: text/plain; 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Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v4->v5 - Included Ack from Conor - Included RB tag from Geert v3->v4 - New patch --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index a750676064cf..fcead2150874 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -180,6 +180,9 @@ allOf: maxItems: 1 interrupt-names: false + else: + required: + - interrupt-names - if: properties: From patchwork Tue Jun 4 17:05:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 801560 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDF59149C7E; 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Tue, 04 Jun 2024 10:05:46 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:2595:4364:d152:dff3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd04c0f2asm12244077f8f.3.2024.06.04.10.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 10:05:45 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Greg Kroah-Hartman , Jiri Slaby , Geert Uytterhoeven Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar , Conor Dooley Subject: [PATCH v5 4/5] dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF support Date: Tue, 4 Jun 2024 18:05:12 +0100 Message-Id: <20240604170513.522631-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604170513.522631-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240604170513.522631-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Document support for the Serial Communication Interface with FIFO (SCIF) available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L (R9A07G044) SoC, with the following differences: - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready and two for Rx and Tx buffer full, all of which are edge-triggered. - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both synchronous and asynchronous modes. - There are differences in the configuration of certain registers such as SCSMR, SCFCR, and SCSPTR between the two SoCs. To handle these differences in the driver, a new SoC-specific compatible string is added, ensuring proper handling of the unique features and register configurations of the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v4->v5 - Included RB tag from Geert and Conor v3->v4 - Appended the interrupts instead of adding SoC specific - Added restriction for clocks and reset v2->v3 - Added SoC specific compat string --- .../bindings/serial/renesas,scif.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index fcead2150874..afc7c05898a1 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -80,6 +80,8 @@ properties: - renesas,scif-r9a08g045 # RZ/G3S - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback + - const: renesas,scif-r9a09g057 # RZ/V2H(P) + reg: maxItems: 1 @@ -94,6 +96,9 @@ properties: - description: Break interrupt - description: Data Ready interrupt - description: Transmit End interrupt + - description: Transmit End/Data Ready interrupt + - description: Receive buffer full interrupt (EDGE trigger) + - description: Transmit buffer empty interrupt (EDGE trigger) minItems: 4 interrupt-names: @@ -105,6 +110,9 @@ properties: - const: bri - const: dri - const: tei + - const: tei-dri + - const: rxi-edge + - const: txi-edge clocks: minItems: 1 @@ -161,6 +169,7 @@ allOf: - renesas,rcar-gen3-scif - renesas,rcar-gen4-scif - renesas,scif-r9a07g044 + - renesas,scif-r9a09g057 then: required: - resets @@ -210,9 +219,30 @@ allOf: properties: interrupts: minItems: 6 + maxItems: 6 interrupt-names: minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + const: renesas,scif-r9a09g057 + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + interrupts: + minItems: 9 + + interrupt-names: + minItems: 9 unevaluatedProperties: false From patchwork Tue Jun 4 17:05:13 2024 Content-Type: text/plain; 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The SCIF interface in the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L (R9A07G044) SoC, with the following differences: - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready and two for Rx and Tx buffer full, all of which are edge-triggered. - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both synchronous and asynchronous modes. - There are differences in the configuration of certain registers such as SCSMR, SCFCR, and SCSPTR between the two SoCs. To handle these differences on RZ/V2H(P) SoC SCIx_RZV2H_SCIF_REGTYPE is added. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- Hi Geert, Ive restored your RB tag after rebase (as the changes were trival) hope that's OK. Cheers, Prabhakar v4 -> v5 - Rebased changes on top of v6.10-rc2 - Included RB tag from Geert v3 -> v4 - Added SCIx_RZV2H_SCIF_REGTYPE to handle the differences on the RZ/V2H(P) SoC v2 -> v3 - new patch --- drivers/tty/serial/sh-sci.c | 55 +++++++++++++++++++++++++++++++++---- include/linux/serial_sci.h | 1 + 2 files changed, 51 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index f738980a8b2c..b80e9a528e17 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -317,6 +317,37 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { .error_clear = SCIF_ERROR_CLEAR, }, + /* + * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC + * with below differences, + * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI, + * TEI-DRI, RXI-EDGE and TXI-EDGE. + * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode. + * - SCFCR register does not have SCFCR_MCE bit. + * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO. + */ + [SCIx_RZV2H_SCIF_REGTYPE] = { + .regs = { + [SCSMR] = { 0x00, 16 }, + [SCBRR] = { 0x02, 8 }, + [SCSCR] = { 0x04, 16 }, + [SCxTDR] = { 0x06, 8 }, + [SCxSR] = { 0x08, 16 }, + [SCxRDR] = { 0x0a, 8 }, + [SCFCR] = { 0x0c, 16 }, + [SCFDR] = { 0x0e, 16 }, + [SCSPTR] = { 0x10, 16 }, + [SCLSR] = { 0x12, 16 }, + [SEMR] = { 0x14, 8 }, + }, + .fifosize = 16, + .overrun_reg = SCLSR, + .overrun_mask = SCLSR_ORER, + .sampling_rate_mask = SCI_SR(32), + .error_mask = SCIF_DEFAULT_ERROR_MASK, + .error_clear = SCIF_ERROR_CLEAR, + }, + /* * Common SH-3 SCIF definitions. */ @@ -757,7 +788,7 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag) } sci_serial_out(port, SCPDR, data); sci_serial_out(port, SCPCR, ctrl); - } else if (sci_getreg(port, SCSPTR)->size) { + } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) { u16 status = sci_serial_in(port, SCSPTR); /* RTS# is always output; and active low, unless autorts */ @@ -2124,8 +2155,9 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) if (!(mctrl & TIOCM_RTS)) { /* Disable Auto RTS */ - sci_serial_out(port, SCFCR, - sci_serial_in(port, SCFCR) & ~SCFCR_MCE); + if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) + sci_serial_out(port, SCFCR, + sci_serial_in(port, SCFCR) & ~SCFCR_MCE); /* Clear RTS */ sci_set_rts(port, 0); @@ -2137,8 +2169,9 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) } /* Enable Auto RTS */ - sci_serial_out(port, SCFCR, - sci_serial_in(port, SCFCR) | SCFCR_MCE); + if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) + sci_serial_out(port, SCFCR, + sci_serial_in(port, SCFCR) | SCFCR_MCE); } else { /* Set RTS */ sci_set_rts(port, 1); @@ -3225,6 +3258,10 @@ static const struct of_device_id of_sci_match[] __maybe_unused = { .compatible = "renesas,scif-r9a07g044", .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), }, + { + .compatible = "renesas,scif-r9a09g057", + .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE), + }, /* Family-specific types */ { .compatible = "renesas,rcar-gen1-scif", @@ -3533,6 +3570,13 @@ static int __init rzscifa_early_console_setup(struct earlycon_device *device, return early_console_setup(device, PORT_SCIF); } +static int __init rzv2hscif_early_console_setup(struct earlycon_device *device, + const char *opt) +{ + port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE; + return early_console_setup(device, PORT_SCIF); +} + static int __init scifa_early_console_setup(struct earlycon_device *device, const char *opt) { @@ -3553,6 +3597,7 @@ OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); +OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup); OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h index 1c89611e0e06..0f2f50b8d28e 100644 --- a/include/linux/serial_sci.h +++ b/include/linux/serial_sci.h @@ -37,6 +37,7 @@ enum { SCIx_SH7705_SCIF_REGTYPE, SCIx_HSCIF_REGTYPE, SCIx_RZ_SCIFA_REGTYPE, + SCIx_RZV2H_SCIF_REGTYPE, SCIx_NR_REGTYPES, };