From patchwork Thu Jun 6 12:57:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang-Huang Bao X-Patchwork-Id: 802134 Received: from mail.eh5.me (mail.eh5.me [45.76.111.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 534061953BE; Thu, 6 Jun 2024 12:58:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.76.111.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717678686; cv=none; b=Nmc7NN+K6O/pqxxLjol3JQMZD2VAVP7tEMIirc1l6+FuFekfJrmw8QFkH7K91w9REJkdVylUrDprf22MkWn8Yc7Ypt7UWuKUm5DMk8g8cpzBGHHTXE1YBizRBUxQ9M6KjctTQ8PfwJwCQdxlT7wM0FBciMoBU5da9YYGOP8/3SQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717678686; c=relaxed/simple; bh=EJeN2WVimoZPUq49zQhU43cbcGY9Zd4lUjWK+/7V8qY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vFYaWaZgwIcgtAUJgvxqts9A/V6IuFQKvVzPjVD7yo1skofnH/7DsqeJVfcl7KohCJx/lxYOi0MH7AB9g6qECSzaf0qUOzfYZnmXY5RCS1xqqJLQFMi8ADsrvXoXU497GROBXSZO/2FilN6oH67DWQuSmyCtyYf2mrbVWBk4FoM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me; spf=pass smtp.mailfrom=eh5.me; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b=JzPFRzXl; arc=none smtp.client-ip=45.76.111.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eh5.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b="JzPFRzXl" From: Huang-Huang Bao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=eh5.me; s=dkim; t=1717678683; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9aGbCJYC5tQIh+V38eaRg/TEw5yXNqXj9kU8kT92Cps=; b=JzPFRzXlwauoFclfUckhLzsumIZFUHKZTz3F69hs/aFkkPnv9lsJWxZHzxunf6gpRYqSYg i5sHtPROQDiqXANTLzVLz5cFSCDpFXLP2kR9qBsdAnAf6Mcn+TWfnLq+w37aIJVDPrbKKD qtVzbUzb7Q/MaW/Z/uPKof6+UmsGH50= To: Heiko Stuebner , Linus Walleij Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Huang-Huang Bao Subject: [PATCH v2 1/4] pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins Date: Thu, 6 Jun 2024 20:57:52 +0800 Message-ID: <20240606125755.53778-2-i@eh5.me> In-Reply-To: <20240606125755.53778-1-i@eh5.me> References: <20240606125755.53778-1-i@eh5.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width, correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is recalculated so it remain unchanged. The pinmux bits for those pins are not explicitly specified in RK3328 TRM, however we can get hint from pad name and its correspinding IOMUX setting for pins in interface descriptions. The correspinding IOMIX settings for GPIO2-B0 to GPIO2-B6 can be found in the same row next to occurrences of following pad names in RK3328 TRM. GPIO2-B0: IO_SPIclkm0_GPIO2B0vccio5 GPIO2-B1: IO_SPItxdm0_GPIO2B1vccio5 GPIO2-B2: IO_SPIrxdm0_GPIO2B2vccio5 GPIO2-B3: IO_SPIcsn0m0_GPIO2B3vccio5 GPIO2-B4: IO_SPIcsn1m0_FLASHvol_sel_GPIO2B4vccio5 GPIO2-B5: IO_ I2C2sda_TSADCshut_GPIO2B5vccio5 GPIO2-B6: IO_ I2C2scl_GPIO2B6vccio5 This fix has been tested on NanoPi R2S for fixing confliting pinmux bits between GPIO2-B7 with GPIO2-B5. Signed-off-by: Huang-Huang Bao Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 3bedf36a0019..78dcf4daccde 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -634,12 +634,6 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { .num = 2, .pin = 15, .reg = 0x28, @@ -3763,7 +3757,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + 0, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", From patchwork Thu Jun 6 12:57:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang-Huang Bao X-Patchwork-Id: 802431 Received: from mail.eh5.me (mail.eh5.me [45.76.111.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EFBF195F25; Thu, 6 Jun 2024 12:58:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.76.111.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717678689; cv=none; b=sdn9CLJct3R7R0JUroE7ZHAWg9HIMe+DjXTK3Q6SxogCU1lSCISSQzjNyHmPdeVln+df8SRedTOKVh5yAnLVPI9k6CDKy25HAfq94APwwwycMI4jbJuk2AuDjSfw/n9SryqG4tZ4jvoxpEEQ/2rhOpW7xamO+1tgZFZra/mysSY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717678689; c=relaxed/simple; bh=nSDtWUoOkviqVSjwlwmEMKZsU1Ck6duiWVcABLyMnJM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sx2nZEO/It5nCrDGrmPLtRUbI2mp7r2CuQNKykmfPuJl/dIU2mb8f2n/n8CUmvh2F0apmj6Xr65lJRBr2Z6spnljEID/NqcjjS08IEmORfCLyO5KmPYGs9j6bsadAnw00xo8piidyliBcgVEEGwB5vTEg2eXWKPVTHqlOD5/nMs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me; spf=pass smtp.mailfrom=eh5.me; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b=DNoHLgh4; arc=none smtp.client-ip=45.76.111.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eh5.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b="DNoHLgh4" From: Huang-Huang Bao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=eh5.me; s=dkim; t=1717678686; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=b8CYQm7j2t9ji5vfaVStrG16PgJM6FurWlwvn6RUIGE=; b=DNoHLgh4pe/QTs9HyXQ6YPCBn543xR6rpfWDLp8gu/DvCGfAyS6x3B3f+BI3hI+RlUV5oc +7nUgn6K3jUGsIEcn4gMP1hRKe//KhWins1M1VDvmXbpbxQa/wCnln9aKyFXMD+fan7uyE Hc7iNN20OPN4TBFYlHDmxJ45jkr0upw= To: Heiko Stuebner , Linus Walleij Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Huang-Huang Bao Subject: [PATCH v2 2/4] pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins Date: Thu, 6 Jun 2024 20:57:53 +0800 Message-ID: <20240606125755.53778-3-i@eh5.me> In-Reply-To: <20240606125755.53778-1-i@eh5.me> References: <20240606125755.53778-1-i@eh5.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly specified in RK3328 TRM, however we can get hint from pad name and its correspinding IOMUX setting for pins in interface descriptions. The correspinding IOMIX settings for these pins can be found in the same row next to occurrences of following pad names in RK3328 TRM. GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6 GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6 GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6 GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6 GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6 GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6 Add pinmux data to rk3328_mux_recalced_data as mux register offset for these pins does not follow rockchip convention. Signed-off-by: Huang-Huang Bao --- drivers/pinctrl/pinctrl-rockchip.c | 51 ++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 78dcf4daccde..23531ea0d088 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -634,17 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, }; From patchwork Thu Jun 6 12:57:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang-Huang Bao X-Patchwork-Id: 802133 Received: from mail.eh5.me (mail.eh5.me [45.76.111.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66B06195FC8; Thu, 6 Jun 2024 12:58:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.76.111.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717678690; cv=none; b=GUgltOg2NDaOuvGFnX5opquYEAeciIaq2m5TZ0FRkOMpcGL8oGVh2yOn+8wxG320DAM/0ZyiZmubf5pG1TSrr7X1srjM1ld/qUT7lPwq3r/KF43bBInCI3VQ8NHB0USLER/xwuMRVwDfc1d6O4io6oDaLQX8i3nOOcoUQeTmzAQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717678690; c=relaxed/simple; bh=eRAmA1xukNt03LAQeiuqd/VkcILzMl+M41PJu15VMOI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MuPCbQj5mn17EZy8bxHsVGfbyiB1kpXY8bszUXfTMPLhYbeYe5vC1jGsC1Qji1PTzsubPoyDtUdVG3Hcqirv1HP9T+GVcg1tVd+eQFaMs/gO4WH+1Oc3AluM6p0B+U9xslqjgvV7r5SfMo+pK269dW0bXmtKYzhvYPSkbRWxR4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me; spf=pass smtp.mailfrom=eh5.me; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b=JueeEJFo; arc=none smtp.client-ip=45.76.111.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eh5.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b="JueeEJFo" From: Huang-Huang Bao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=eh5.me; s=dkim; t=1717678688; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cm1zLLD1IROmIjzUh2BRQWDXRgYGVGkaOuwh/RAhEW0=; b=JueeEJFoMz+PsZHsFTWzGzuRK8H7prwNEdYjoGe+6bajQPC+Hq+ACE0bEOkBV05EJmtcdE 5KRQF03Z3DpsdxPjn0CQM9Atv+7y7bPOrDm4GEEgCh6jgJMtWsHtBS/O7/lWJdLTFCP4Xz 00Rxqeu5q8SDzkCm58J79CugqQJ2XGA= To: Heiko Stuebner , Linus Walleij Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Huang-Huang Bao Subject: [PATCH v2 3/4] pinctrl: rockchip: use dedicated pinctrl type for RK3328 Date: Thu, 6 Jun 2024 20:57:54 +0800 Message-ID: <20240606125755.53778-4-i@eh5.me> In-Reply-To: <20240606125755.53778-1-i@eh5.me> References: <20240606125755.53778-1-i@eh5.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 rk3328_pin_ctrl uses type of RK3288 which has a hack in rockchip_pinctrl_suspend and rockchip_pinctrl_resume to restore GPIO6-C6 at assume, the hack is not applicable to RK3328 as GPIO6 is not even exist in it. So use a dedicated pinctrl type to skip this hack. Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support") Reviewed-by: Heiko Stuebner Signed-off-by: Huang-Huang Bao --- drivers/pinctrl/pinctrl-rockchip.c | 5 ++++- drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 23531ea0d088..24ee88863ce3 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2478,6 +2478,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) case RK3188: case RK3288: case RK3308: + case RK3328: case RK3368: case RK3399: case RK3568: @@ -2536,6 +2537,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, case RK3188: case RK3288: case RK3308: + case RK3328: case RK3368: case RK3399: case RK3568: @@ -2798,6 +2800,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, case RK3188: case RK3288: case RK3308: + case RK3328: case RK3368: case RK3399: case RK3568: @@ -3822,7 +3825,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), .label = "RK3328-GPIO", - .type = RK3288, + .type = RK3328, .grf_mux_offset = 0x0, .iomux_recalced = rk3328_mux_recalced_data, .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 4759f336941e..849266f8b191 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -193,6 +193,7 @@ enum rockchip_pinctrl_type { RK3188, RK3288, RK3308, + RK3328, RK3368, RK3399, RK3568, From patchwork Thu Jun 6 12:57:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang-Huang Bao X-Patchwork-Id: 802430 Received: from mail.eh5.me (mail.eh5.me [45.76.111.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 449D3195FF7; Thu, 6 Jun 2024 12:58:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.76.111.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717678692; cv=none; b=Of1X3OOJjkZ11d5CejirB3q+8hzlrPxLfSMllC91VbI6S8WfUQJg6us5mh0aBN002J5rqP/OX/Xm5Rn9TPaQ3IKb1YOGd1MQ4vXGDfPHgm15XmDUdwYorc7S6kK5914iHh29CrgKUoxNclHJ45VYrDnE3K4v+Vfxqwky8Cm9vpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717678692; c=relaxed/simple; bh=ujEPMM4MA25Q1mRmU9a/DJCxnW6ZZ2vURpgcPeEvVIQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G7mxalNwQWy9B6a04VbH/92eJaAqRugEs2oMSbTx0FiD0ZsucaxwaAUtrYWvSerwH3vhij2ZajUSUxUFJVuHZkTIg5fJeBTX/nrPPHVp0/m4hq19JTwIjYBYZDGM7biQzFqwvaO8Qw8y4wEDNyrl007xJkVRj718vKGLiCZ6tXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me; spf=pass smtp.mailfrom=eh5.me; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b=ybEJeoSA; arc=none smtp.client-ip=45.76.111.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=eh5.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eh5.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=eh5.me header.i=@eh5.me header.b="ybEJeoSA" From: Huang-Huang Bao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=eh5.me; s=dkim; t=1717678689; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aHzfbCHuap4cxwq/iZevfqON/k/0kct/7NXKtBKj9d4=; b=ybEJeoSAIAuQTp3QZIKYIgmz0J3/KIgn15jDFz/ErksFABXunAGcm8rVMNNZUZ9AEIzcwH D0ONwIX9BIEZtQ873j+zrFf46vaOCQ20+q5ZQdm1hV7uDlLCgyxvns+bYgdP5IAE/0UNoV YbVaE3NPqJq1FTPd6C4R0Dynk3A7WRU= To: Heiko Stuebner , Linus Walleij Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Huang-Huang Bao Subject: [PATCH v2 4/4] pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set Date: Thu, 6 Jun 2024 20:57:55 +0800 Message-ID: <20240606125755.53778-5-i@eh5.me> In-Reply-To: <20240606125755.53778-1-i@eh5.me> References: <20240606125755.53778-1-i@eh5.me> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 rockchip_pmx_set reset all pinmuxs in group to 0 in the case of error, add missing bank data retrieval in that code to avoid setting mux on unexpected pins. Fixes: 14797189b35e ("pinctrl: rockchip: add return value to rockchip_set_mux") Reviewed-by: Heiko Stuebner Signed-off-by: Huang-Huang Bao --- drivers/pinctrl/pinctrl-rockchip.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 24ee88863ce3..3f56991f5b89 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2751,8 +2751,10 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, if (ret) { /* revert the already done pin settings */ - for (cnt--; cnt >= 0; cnt--) + for (cnt--; cnt >= 0; cnt--) { + bank = pin_to_bank(info, pins[cnt]); rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); + } return ret; }