From patchwork Thu Jun 6 12:09:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 803161 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF3791667E3; Thu, 6 Jun 2024 12:09:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675792; cv=none; b=uAKFdex2Hf/iteIZaQILLjOnTvq7mKWlplpDqaKAN6aN2JVGYra0GvTvF9Qgmw67EKSCR6IDlwVXhtav52ictGBRIWqDh0lYePED9XaKsqjCv+bgMKgb1NondLoa4G7Egar40HD55gl+mc/pF6gv317bTMcrS99cFkZY7rN03Uc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675792; c=relaxed/simple; bh=RmTgHweKgAssG7twV/Fz0Qm6DPv1stk6E+o3xHnyxto=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XWGZuedxw3rgsIW4OteBGZJw9vYYvhz7vjbpUeLx/DPnIp0ISouGohRb8GhmDn191tpvHMN1Liolbvzf+Rd6xT1itk+qyMyssnTJLsgO3SXZfV5HsHB2mUdUWioLQ9xQQJGBbKMeGDZjedkHuQ2NV8kJjKTZcRC42E5UsOjSuu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rSLU2ohz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rSLU2ohz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3ADECC4AF48; Thu, 6 Jun 2024 12:09:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717675792; bh=RmTgHweKgAssG7twV/Fz0Qm6DPv1stk6E+o3xHnyxto=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=rSLU2ohzRM7DbD8PU7VSAObnB8QbVQjDRrBTZ17SWzSpIezqup8aguOYv4LksEPiW ME/7l0aTPUfLFMQ0iZ0vY7IxRinX86osixDIhT3UA4W3zH8NqhOW3DRnIsIjb3o9oJ pavrsnWhYeCTAUSYtcGsLghhMnXoYJe7gLkutT4b8RyKjJ/9sDJc2+Af3GLko86bDn ScF+7pzVLd+glsKLfFKsxbtQ5G2FIMHyxMeG6KANQJVLiIiJJlh1KobFE6UV3+uZSQ qYFpb75t/ZJ1Mq4ERL345afKvmgbGgBJIFqtsjBQz3hFk75bnHIX8S9p2RxHk0/bm7 lyikvEe+BhCdw== From: Roger Quadros Date: Thu, 06 Jun 2024 15:09:17 +0300 Subject: [PATCH RFC net-next 1/7] net: ethernet: ti: am65-cpsw: Introduce multi queue Rx Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-am65-cpsw-multi-rx-v1-1-0704b0cb6fdc@kernel.org> References: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> In-Reply-To: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=17660; i=rogerq@kernel.org; h=from:subject:message-id; bh=RmTgHweKgAssG7twV/Fz0Qm6DPv1stk6E+o3xHnyxto=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmYacBa0JW22jJ+B7l0y0IFIPUgVEvglczUaDG/ vhi4yUsMV+JAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZmGnAQAKCRDSWmvTvnYw k7AaD/9cKt9txjx2F+Q4TOgEKTCZYJb8nODxF/P/QqyP5h35lUsidflzf/5WEuzReF8IsEZWuZH iXIdHDhI7fAGGtfPnTcrf/FNmC+JIoPhL+J7oVDOopIFmpr8mg6OYskpYyOjNYjwngUxNlaVLCk Bi5t/fzbDPVrr98lxCrLjjIy6dvTipY4ulYCr2VAawJUx6inIXwfCLpx/54sCGojNlKFQKd3Ow0 nLLVCJvwHGAeqIgcss43BD7Oo/ZKCXjxu7ab5Bu9n2Lno2egI44O9B+db8aPB/DvN8yLjdZ4K1O NsL7E5N+BQni9xcK8I/DrUHfUaOzAeoed344TpmjlRTXFHWmh7ckb6L2m3hxFZPJJ0f1YwBav61 AqgUIYYOH1tx/NFIJhnaYGxOtyZUfrzWGLG9g7heScQDG7CtPY+aceDbAQrsIB0iT3VsFSw0frG m7qSKoQKpASe0tdBmzXoOYbyPcT17uDQ5k9A4HdKTQ4owB2lEYgGijkkpY3fpMxzVUzagtGokwl vXpnCPZFT/2WLBUKecds9bWQALkkXiUBICxP5aRxqUuchR9h9WU1rVgByeY6YR+Xlo7J8eopCQl LiWX4sYpi/YWnlYUB5rPq94fkIoBP0Tc8RnkwC6ZpsEnFHUHDxcCdiNF8q/pGzJi4rMISDt36KS hJTPt1HQML2rtBw== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 am65-cpsw can support up to 8 queues at Rx. Use a macro AM65_CPSW_MAX_RX_QUEUES to indicate that. As there is only one DMA channel for RX traffic, the 8 queues come as 8 flows in that channel. By default, we will start with 1 flow as defined by the macro AM65_CPSW_DEFAULT_RX_CHN_FLOWS. User can change the number of flows by ethtool like so 'ethtool ethx -L rx ' All traffic will still come on flow 0. To get traffic on different flows the Classifiers will need to be setup. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-ethtool.c | 5 +- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 194 +++++++++++++++------------- drivers/net/ethernet/ti/am65-cpsw-nuss.h | 25 ++-- 3 files changed, 126 insertions(+), 98 deletions(-) diff --git a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c index 01fd13649cc1..d76056696e69 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-ethtool.c +++ b/drivers/net/ethernet/ti/am65-cpsw-ethtool.c @@ -429,7 +429,7 @@ static void am65_cpsw_get_channels(struct net_device *ndev, ch->max_rx = AM65_CPSW_MAX_RX_QUEUES; ch->max_tx = AM65_CPSW_MAX_TX_QUEUES; - ch->rx_count = AM65_CPSW_MAX_RX_QUEUES; + ch->rx_count = common->rx_ch_num_flows; ch->tx_count = common->tx_ch_num; } @@ -448,8 +448,9 @@ static int am65_cpsw_set_channels(struct net_device *ndev, return -EBUSY; am65_cpsw_nuss_remove_tx_chns(common); + am65_cpsw_nuss_remove_rx_chns(common); - return am65_cpsw_nuss_update_tx_chns(common, chs->tx_count); + return am65_cpsw_nuss_update_tx_rx_chns(common, chs->tx_count, chs->rx_count); } static void diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 5ca1d0b687a7..1e718d4671c9 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -125,7 +125,7 @@ AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 -/* Number of TX/RX descriptors */ +/* Number of TX/RX descriptors per channel/flow */ #define AM65_CPSW_MAX_TX_DESC 500 #define AM65_CPSW_MAX_RX_DESC 500 @@ -137,6 +137,7 @@ NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) #define AM65_CPSW_DEFAULT_TX_CHNS 8 +#define AM65_CPSW_DEFAULT_RX_CHN_FLOWS 1 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, const u8 *dev_addr) @@ -305,7 +306,7 @@ static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, } static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, - struct sk_buff *skb) + struct sk_buff *skb, u32 flow_idx) { struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; struct cppi5_host_desc_t *desc_rx; @@ -337,7 +338,8 @@ static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, swdata = cppi5_hdesc_get_swdata(desc_rx); *((void **)swdata) = skb; - return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); + return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, flow_idx, + desc_rx, desc_dma); } void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) @@ -443,7 +445,7 @@ static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) { struct am65_cpsw_host *host_p = am65_common_get_host(common); - int port_idx, i, ret, tx; + int port_idx, i, ret, tx, flow_idx; struct sk_buff *skb; u32 val, port_mask; @@ -505,29 +507,31 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) am65_cpsw_qos_tx_p0_rate_init(common); - for (i = 0; i < common->rx_chns.descs_num; i++) { - skb = __netdev_alloc_skb_ip_align(NULL, - AM65_CPSW_MAX_PACKET_SIZE, - GFP_KERNEL); - if (!skb) { - ret = -ENOMEM; - dev_err(common->dev, "cannot allocate skb\n"); - if (i) - goto fail_rx; + for (flow_idx = 0; flow_idx < common->rx_ch_num_flows; flow_idx++) { + for (i = 0; i < common->rx_chns.descs_num / common->rx_ch_num_flows; i++) { + skb = __netdev_alloc_skb_ip_align(NULL, + AM65_CPSW_MAX_PACKET_SIZE, + GFP_KERNEL); + if (!skb) { + ret = -ENOMEM; + dev_err(common->dev, "cannot allocate skb\n"); + if (i) + goto fail_rx; - return ret; - } + return ret; + } - ret = am65_cpsw_nuss_rx_push(common, skb); - if (ret < 0) { - dev_err(common->dev, - "cannot submit skb to channel rx, error %d\n", - ret); - kfree_skb(skb); - if (i) - goto fail_rx; + ret = am65_cpsw_nuss_rx_push(common, skb, flow_idx); + if (ret < 0) { + dev_err(common->dev, + "cannot submit skb to channel rx, error %d\n", + ret); + kfree_skb(skb); + if (i) + goto fail_rx; - return ret; + return ret; + } } } @@ -537,6 +541,14 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) goto fail_rx; } + for (i = 0; i < common->rx_ch_num_flows ; i++) { + napi_enable(&common->rx_chns.flows[i].napi_rx); + if (common->rx_chns.flows[i].irq_disabled) { + common->rx_chns.flows[i].irq_disabled = false; + enable_irq(common->rx_chns.flows[i].irq); + } + } + for (tx = 0; tx < common->tx_ch_num; tx++) { ret = k3_udma_glue_enable_tx_chn(common->tx_chns[tx].tx_chn); if (ret) { @@ -548,16 +560,13 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) napi_enable(&common->tx_chns[tx].napi_tx); } - napi_enable(&common->napi_rx); - if (common->rx_irq_disabled) { - common->rx_irq_disabled = false; - enable_irq(common->rx_chns.irq); - } - dev_dbg(common->dev, "cpsw_nuss started\n"); return 0; fail_tx: + for (i = 0; i < common->rx_ch_num_flows; i++) + napi_disable(&common->rx_chns.flows[i].napi_rx); + while (tx >= 0) { napi_disable(&common->tx_chns[tx].napi_tx); k3_udma_glue_disable_tx_chn(common->tx_chns[tx].tx_chn); @@ -615,12 +624,12 @@ static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) dev_err(common->dev, "rx teardown timeout\n"); } - napi_disable(&common->napi_rx); - - for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) + for (i = 0; i < common->rx_ch_num_flows; i++) { + napi_disable(&common->rx_chns.flows[i].napi_rx); k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, &common->rx_chns, am65_cpsw_nuss_rx_cleanup, !!i); + } k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); @@ -697,7 +706,7 @@ static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) goto runtime_put; } - ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); + ret = netif_set_real_num_rx_queues(ndev, common->rx_ch_num_flows); if (ret) { dev_err(common->dev, "cannot set real number of rx queues\n"); goto runtime_put; @@ -791,11 +800,11 @@ static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) } } -static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, - u32 flow_idx) +static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_rx_flow *flow) { - struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; + struct am65_cpsw_rx_chn *rx_chn = &flow->common->rx_chns; u32 buf_dma_len, pkt_len, port_id = 0, csum_info; + struct am65_cpsw_common *common = flow->common; struct am65_cpsw_ndev_priv *ndev_priv; struct am65_cpsw_ndev_stats *stats; struct cppi5_host_desc_t *desc_rx; @@ -804,6 +813,7 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, dma_addr_t desc_dma, buf_dma; struct am65_cpsw_port *port; struct net_device *ndev; + u32 flow_idx = flow->id; void **swdata; u32 *psdata; int ret = 0; @@ -855,7 +865,7 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, skb_put(skb, pkt_len); skb->protocol = eth_type_trans(skb, ndev); am65_cpsw_nuss_rx_csum(skb, csum_info); - napi_gro_receive(&common->napi_rx, skb); + napi_gro_receive(&flow->napi_rx, skb); stats = this_cpu_ptr(ndev_priv->stats); @@ -875,7 +885,7 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, return 0; } - ret = am65_cpsw_nuss_rx_push(common, new_skb); + ret = am65_cpsw_nuss_rx_push(common, new_skb, flow_idx); if (WARN_ON(ret < 0)) { dev_kfree_skb_any(new_skb); ndev->stats.rx_errors++; @@ -887,32 +897,25 @@ static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) { - struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); - int flow = AM65_CPSW_MAX_RX_FLOWS; - int cur_budget, ret; - int num_rx = 0; - - /* process every flow */ - while (flow--) { - cur_budget = budget - num_rx; - - while (cur_budget--) { - ret = am65_cpsw_nuss_rx_packets(common, flow); - if (ret) - break; - num_rx++; - } + struct am65_cpsw_rx_flow *flow = am65_cpsw_napi_to_rx_flow(napi_rx); + struct am65_cpsw_common *common = flow->common; + int num_rx = 0, ret; - if (num_rx >= budget) + /* process only this flow */ + while (budget--) { + ret = am65_cpsw_nuss_rx_packets(flow); + if (ret) break; + + num_rx++; } dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { - if (common->rx_irq_disabled) { - common->rx_irq_disabled = false; - enable_irq(common->rx_chns.irq); + if (flow->irq_disabled) { + flow->irq_disabled = false; + enable_irq(flow->irq); } } @@ -1080,11 +1083,11 @@ static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) { - struct am65_cpsw_common *common = dev_id; + struct am65_cpsw_rx_flow *flow = dev_id; - common->rx_irq_disabled = true; + flow->irq_disabled = true; disable_irq_nosync(irq); - napi_schedule(&common->napi_rx); + napi_schedule(&flow->napi_rx); return IRQ_HANDLED; } @@ -1818,19 +1821,23 @@ static void am65_cpsw_nuss_free_rx_chns(void *data) k3_udma_glue_release_rx_chn(rx_chn->rx_chn); } -static void am65_cpsw_nuss_remove_rx_chns(void *data) +void am65_cpsw_nuss_remove_rx_chns(void *data) { struct am65_cpsw_common *common = data; struct am65_cpsw_rx_chn *rx_chn; struct device *dev = common->dev; + struct am65_cpsw_rx_flow *flows; + int i; rx_chn = &common->rx_chns; + flows = rx_chn->flows; devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); - if (!(rx_chn->irq < 0)) - devm_free_irq(dev, rx_chn->irq, common); - - netif_napi_del(&common->napi_rx); + for (i = 0; i < common->rx_ch_num_flows; i++) { + if (!(flows[i].irq < 0)) + devm_free_irq(dev, flows[i].irq, &flows[i]); + netif_napi_del(&flows[i].napi_rx); + } if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) k3_cppi_desc_pool_destroy(rx_chn->desc_pool); @@ -1845,6 +1852,7 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) { struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; + struct am65_cpsw_rx_flow *flows = rx_chn->flows; u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; struct device *dev = common->dev; u32 hdesc_size; @@ -1855,12 +1863,12 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) AM65_CPSW_NAV_SW_DATA_SIZE); rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; - rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; + rx_cfg.flow_id_num = common->rx_ch_num_flows; rx_cfg.flow_id_base = common->rx_flow_id_base; /* init all flows */ rx_chn->dev = dev; - rx_chn->descs_num = max_desc_num; + rx_chn->descs_num = max_desc_num * rx_cfg.flow_id_num; rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); if (IS_ERR(rx_chn->rx_chn)) { @@ -1902,6 +1910,8 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, }; + flows[i].id = i; + flows[i].common = common; rx_flow_cfg.ring_rxfdq0_id = fdqring_id; rx_flow_cfg.rx_cfg.size = max_desc_num; rx_flow_cfg.rxfdq_cfg.size = max_desc_num; @@ -1918,26 +1928,28 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, i); - rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); - - if (rx_chn->irq <= 0) { + flows[i].irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); + if (flows[i].irq <= 0) { dev_err(dev, "Failed to get rx dma irq %d\n", - rx_chn->irq); + flows[i].irq); ret = -ENXIO; goto err; } - } - netif_napi_add(common->dma_ndev, &common->napi_rx, - am65_cpsw_nuss_rx_poll); - - ret = devm_request_irq(dev, rx_chn->irq, - am65_cpsw_nuss_rx_irq, - IRQF_TRIGGER_HIGH, dev_name(dev), common); - if (ret) { - dev_err(dev, "failure requesting rx irq %u, %d\n", - rx_chn->irq, ret); - goto err; + snprintf(flows[i].name, + sizeof(flows[i].name), "%s-rx%d", + dev_name(dev), i); + netif_napi_add(common->dma_ndev, &flows[i].napi_rx, + am65_cpsw_nuss_rx_poll); + ret = devm_request_irq(dev, flows[i].irq, + am65_cpsw_nuss_rx_irq, + IRQF_TRIGGER_HIGH, + flows[i].name, &flows[i]); + if (ret) { + dev_err(dev, "failure requesting rx %d irq %u, %d\n", + i, flows[i].irq, ret); + goto err; + } } err: @@ -2774,7 +2786,7 @@ static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); } - for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) + for (i = 0; i < common->rx_ch_num_flows; i++) k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, rx_chan, am65_cpsw_nuss_rx_cleanup, !!i); @@ -2817,12 +2829,17 @@ static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) return ret; } -int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) +int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, int num_tx, int num_rx) { int ret; common->tx_ch_num = num_tx; + common->rx_ch_num_flows = num_rx; ret = am65_cpsw_nuss_init_tx_chns(common); + if (ret) + return ret; + + ret = am65_cpsw_nuss_init_rx_chns(common); return ret; } @@ -2951,6 +2968,7 @@ static int am65_cpsw_nuss_probe(struct platform_device *pdev) common->rx_flow_id_base = -1; init_completion(&common->tdown_complete); common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; + common->rx_ch_num_flows = AM65_CPSW_DEFAULT_RX_CHN_FLOWS; common->pf_p0_rx_ptype_rrobin = false; common->default_vlan = 1; @@ -3142,8 +3160,10 @@ static int am65_cpsw_nuss_resume(struct device *dev) return ret; /* If RX IRQ was disabled before suspend, keep it disabled */ - if (common->rx_irq_disabled) - disable_irq(common->rx_chns.irq); + for (i = 0; i < common->rx_ch_num_flows; i++) { + if (common->rx_chns.flows[i].irq_disabled) + disable_irq(common->rx_chns.flows[i].irq); + } am65_cpts_resume(common->cpts); diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h index 1e4a045057fc..ecc38a36e9a7 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h @@ -21,8 +21,7 @@ struct am65_cpts; #define HOST_PORT_NUM 0 #define AM65_CPSW_MAX_TX_QUEUES 8 -#define AM65_CPSW_MAX_RX_QUEUES 1 -#define AM65_CPSW_MAX_RX_FLOWS 1 +#define AM65_CPSW_MAX_RX_QUEUES 8 #define AM65_CPSW_PORT_VLAN_REG_OFFSET 0x014 @@ -82,13 +81,22 @@ struct am65_cpsw_tx_chn { u32 rate_mbps; }; +struct am65_cpsw_rx_flow { + u32 id; + struct napi_struct napi_rx; + struct am65_cpsw_common *common; + int irq; + bool irq_disabled; + char name[32]; +}; + struct am65_cpsw_rx_chn { struct device *dev; struct device *dma_dev; struct k3_cppi_desc_pool *desc_pool; struct k3_udma_glue_rx_channel *rx_chn; u32 descs_num; - int irq; + struct am65_cpsw_rx_flow flows[AM65_CPSW_MAX_RX_QUEUES]; }; #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0) @@ -134,10 +142,8 @@ struct am65_cpsw_common { struct completion tdown_complete; atomic_t tdown_cnt; + int rx_ch_num_flows; struct am65_cpsw_rx_chn rx_chns; - struct napi_struct napi_rx; - - bool rx_irq_disabled; u32 nuss_ver; u32 cpsw_ver; @@ -186,8 +192,8 @@ struct am65_cpsw_ndev_priv { #define am65_common_get_host(common) (&(common)->host) #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1]) -#define am65_cpsw_napi_to_common(pnapi) \ - container_of(pnapi, struct am65_cpsw_common, napi_rx) +#define am65_cpsw_napi_to_rx_flow(pnapi) \ + container_of(pnapi, struct am65_cpsw_rx_flow, napi_rx) #define am65_cpsw_napi_to_tx_chn(pnapi) \ container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx) @@ -199,7 +205,8 @@ extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave; void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common); void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common); -int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx); +void am65_cpsw_nuss_remove_rx_chns(void *data); +int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, int num_tx, int num_rx); bool am65_cpsw_port_dev_check(const struct net_device *dev); From patchwork Thu Jun 6 12:09:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 802212 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D365195F10; Thu, 6 Jun 2024 12:09:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675796; cv=none; b=RysrBCkUOrXYY0T/B4Z6yRzteKExG9UPHEJrs2P4PQfn+SLH7Tc8ZVx4zgc0WUauweswYL978r1XUQPjNABLAlBfI1UlthGhNM5gMhNUE3MflwyTUrrPjFFwHM0J/1QgqZQy5z4DZv6z0yI8bCVlXYrdK9SCd5r91Ud94DpTMgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675796; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=7430; i=rogerq@kernel.org; h=from:subject:message-id; bh=CbIB5qO2jhGkVedTF0ZhVMpobXs6Dehu/8Fb+mwzfxw=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmYacCU8WFXXVkMRc9j72TteaqBz2TuRAmJcyW7 wWVf/9wLyKJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZmGnAgAKCRDSWmvTvnYw k41wEADLvGiBFPh39dfCEzqza/g7kl/wsMAbmDHZfhQneCk5n/QXqsYZNeQ9+yPml0Du62WslFT mcIjFxKXBiJV3YAYcBt+VFWKRXEtJdE3A+BB5g5USg2SUFlsZMr7wYG9U92UnGczxwm6WkmLtSZ b0yb2uaQsEqhspzN8czI8/oY23XkV0llMbPRncCFcH7edUfkAB/dgaCOvgrcZliJA0N8bKIs/SG T5KGhVbRlUSxngLsqtkeWFlXydRdspCJV8WuGEQtmmzp0eOMPUbIq1bDWw8M4RQocLP5bNi6a1R VuWpPI0fsYSOb+BTLJ3/VB9aKrvEl3TG8AxxCeLmVTbC1KaWTY0lEho6Nx9akv4S+z97IY7jHq1 JiyvTK6nH7P0ixf5ZY6r+9DYkWEVbgeHTgIhfXPMf/eIsiwm1fCaRlesKuyTWxcEYq68WP3HGsR NBkhJmyU+OQTB0ZZcKUmJtNdxvPDmd/9HbeiYQT+YWofxO+rSAdXjDt+/YD8nM7dGmb/dkcxi24 pa4LFV7R//OIVhebqvDQYxw/IUX5tvo4w2OsjsI7Bl8kBErWDR9LOxNbHKh5rp1x5VKnLi+EV5I UEuJEeIziQaRe7A4UOEHo/mJDhjc1sIKTcUy4M9CMvJmoULewCccH00xoRVexre/4zsUbBY46YV vYsKAAYmwmp+gkg== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Map the entire ALE registerspace using regmap. Add regfields for Major and Minor Version fields. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 83 +++++++++++++++++++++++++++++--------- drivers/net/ethernet/ti/cpsw_ale.h | 17 ++++++-- 2 files changed, 78 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 64bf22cd860c..5afe9fdd6402 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -76,7 +77,7 @@ enum { * @dev_id: ALE version/SoC id * @features: features supported by ALE * @tbl_entries: number of ALE entries - * @major_ver_mask: mask of ALE Major Version Value in ALE_IDVER reg. + * @reg_fields: pointer to array of register field configuration * @nu_switch_ale: NU Switch ALE * @vlan_entry_tbl: ALE vlan entry fields description tbl */ @@ -84,7 +85,7 @@ struct cpsw_ale_dev_id { const char *dev_id; u32 features; u32 tbl_entries; - u32 major_ver_mask; + const struct reg_field *reg_fields; bool nu_switch_ale; const struct ale_entry_fld *vlan_entry_tbl; }; @@ -1292,25 +1293,37 @@ void cpsw_ale_stop(struct cpsw_ale *ale) cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); } +static const struct reg_field ale_fields_cpsw[] = { + /* CPSW_ALE_IDVER_REG */ + [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), + [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 15), +}; + +static const struct reg_field ale_fields_cpsw_nu[] = { + /* CPSW_ALE_IDVER_REG */ + [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), + [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10), +}; + static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { { /* am3/4/5, dra7. dm814x, 66ak2hk-gbe */ .dev_id = "cpsw", .tbl_entries = 1024, - .major_ver_mask = 0xff, + .reg_fields = ale_fields_cpsw, .vlan_entry_tbl = vlan_entry_cpsw, }, { /* 66ak2h_xgbe */ .dev_id = "66ak2h-xgbe", .tbl_entries = 2048, - .major_ver_mask = 0xff, + .reg_fields = ale_fields_cpsw, .vlan_entry_tbl = vlan_entry_cpsw, }, { .dev_id = "66ak2el", .features = CPSW_ALE_F_STATUS_REG, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .nu_switch_ale = true, .vlan_entry_tbl = vlan_entry_nu, }, @@ -1318,7 +1331,7 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .dev_id = "66ak2g", .features = CPSW_ALE_F_STATUS_REG, .tbl_entries = 64, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .nu_switch_ale = true, .vlan_entry_tbl = vlan_entry_nu, }, @@ -1326,20 +1339,20 @@ static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { .dev_id = "am65x-cpsw2g", .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, .tbl_entries = 64, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .nu_switch_ale = true, .vlan_entry_tbl = vlan_entry_nu, }, { .dev_id = "j721e-cpswxg", .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .vlan_entry_tbl = vlan_entry_k3_cpswxg, }, { .dev_id = "am64-cpswxg", .features = CPSW_ALE_F_STATUS_REG | CPSW_ALE_F_HW_AUTOAGING, - .major_ver_mask = 0x7, + .reg_fields = ale_fields_cpsw_nu, .vlan_entry_tbl = vlan_entry_k3_cpswxg, .tbl_entries = 512, }, @@ -1361,41 +1374,75 @@ cpsw_ale_dev_id *cpsw_ale_match_id(const struct cpsw_ale_dev_id *id, return NULL; } +static const struct regmap_config ale_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .name = "cpsw-ale", +}; + +static int cpsw_ale_regfield_init(struct cpsw_ale *ale) +{ + struct regmap *regmap = ale->regmap; + struct device *dev = ale->params.dev; + const struct reg_field *reg_fields = ale->params.reg_fields; + int i; + + for (i = 0; i < ALE_FIELDS_MAX; i++) { + ale->fields[i] = devm_regmap_field_alloc(dev, regmap, + reg_fields[i]); + if (IS_ERR(ale->fields[i])) { + dev_err(dev, "Unable to allocate regmap field %d\n", i); + return PTR_ERR(ale->fields[i]); + } + } + + return 0; +} + struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) { const struct cpsw_ale_dev_id *ale_dev_id; struct cpsw_ale *ale; - u32 rev, ale_entries; + u32 ale_entries, rev_major, rev_minor; + int ret; ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); if (!ale_dev_id) return ERR_PTR(-EINVAL); params->ale_entries = ale_dev_id->tbl_entries; - params->major_ver_mask = ale_dev_id->major_ver_mask; params->nu_switch_ale = ale_dev_id->nu_switch_ale; + params->reg_fields = ale_dev_id->reg_fields; ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); if (!ale) return ERR_PTR(-ENOMEM); + ale->regmap = devm_regmap_init_mmio(params->dev, params->ale_regs, &ale_regmap_cfg); + if (IS_ERR(ale->regmap)) { + dev_err(params->dev, "Couldn't create CPSW ALE regmap\n"); + return ERR_PTR(-ENOMEM); + } + + ale->params = *params; + ret = cpsw_ale_regfield_init(ale); + if (ret) + return ERR_PTR(ret); ale->p0_untag_vid_mask = devm_bitmap_zalloc(params->dev, VLAN_N_VID, GFP_KERNEL); if (!ale->p0_untag_vid_mask) return ERR_PTR(-ENOMEM); - ale->params = *params; ale->ageout = ale->params.ale_ageout * HZ; ale->features = ale_dev_id->features; ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl; - rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER); - ale->version = - (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) | - ALE_VERSION_MINOR(rev); + regmap_field_read(ale->fields[MINOR_VER], &rev_minor); + regmap_field_read(ale->fields[MAJOR_VER], &rev_major); + ale->version = rev_major << 8 | rev_minor; dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n", - ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask), - ALE_VERSION_MINOR(rev)); + rev_major, rev_minor); if (ale->features & CPSW_ALE_F_STATUS_REG && !ale->params.ale_entries) { diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 6779ee111d57..58d377dd7496 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -8,6 +8,8 @@ #ifndef __TI_CPSW_ALE_H__ #define __TI_CPSW_ALE_H__ +struct reg_fields; + struct cpsw_ale_params { struct device *dev; void __iomem *ale_regs; @@ -20,19 +22,26 @@ struct cpsw_ale_params { * to identify this hardware. */ bool nu_switch_ale; - /* mask bit used in NU Switch ALE is 3 bits instead of 8 bits. So - * pass it from caller. - */ - u32 major_ver_mask; + const struct reg_field *reg_fields; const char *dev_id; unsigned long bus_freq; }; struct ale_entry_fld; +struct regmap; + +enum ale_fields { + MINOR_VER, + MAJOR_VER, + /* terminator */ + ALE_FIELDS_MAX, +}; struct cpsw_ale { struct cpsw_ale_params params; struct timer_list timer; + struct regmap *regmap; + struct regmap_field *fields[ALE_FIELDS_MAX]; unsigned long ageout; u32 version; u32 features; From patchwork Thu Jun 6 12:09:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 803160 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E27BC195FCF; Thu, 6 Jun 2024 12:09:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675800; cv=none; b=K+3VcUk+qzAH7L1PcKROJST3D0l35nQ9VyEjcuGxNEgllILNMArfJMq1D3NmSWR9WUAeYiOyVUKXGqL4i//QkwD4sJgXWkjpRoeP5WxVFc9liAxPlVN5U7nwOPRoi8El2YjozH3bGnSvsOrJrxFmS6uWO3RIGxSvbXq+g+VjdVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675800; c=relaxed/simple; bh=E3unqPthK3jtIV9iITSd5L7XKv4kRv1ZvHzNZ1sC+Ng=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Rb9ldp/TKmVfbP0fZZTJGNnILKuQtALNxoSdn6oiM5kw+xn6VtFSum1Umq+fdvHQHxUUedx36D7S8qEIojjFwYO1xWR47ApO/Rkh15yFmks/Rg0DSm/I7xmucs+rUmHZCS3XZeMsnYdJ8gc7s54DY7VKNjNLTblVTIQsHGPquNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SIf/KnQE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SIf/KnQE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67EB5C4AF16; Thu, 6 Jun 2024 12:09:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717675799; bh=E3unqPthK3jtIV9iITSd5L7XKv4kRv1ZvHzNZ1sC+Ng=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SIf/KnQEJcVlVL1FRG8paql8m5y2cME5Uv5oU+Lik4enoe0pmuzL3/pBE6ajRavG+ M6T7h9mzZ3Ku4sM0dhthKgfMVCiKkDNMJdqvhsgrw5Fcfr8c7OBI8hx4heajcgiL5a g5Omg1FNXfO1yp/C3gNq1jjquUooBiIBL2MuCHGZSjo/8juUWHa6Uf9a9IDpYa5SRy mrsCvIfIPJjnUTKTRaWxX7e4L5VRMd5/Qj1lZP/VS+Uo1BSSSpYkDRbgF2o6JLwfF9 48rSyJFG6EXogPzyVYWiIGOBEg/3HLG8ocJZerAxvjDEO/QnkkucyMhe78Dub0ZArX EnEwOGvdW6sIg== From: Roger Quadros Date: Thu, 06 Jun 2024 15:09:19 +0300 Subject: [PATCH RFC net-next 3/7] net: ethernet: ti: cpsw_ale: use regfields for number of Entries and Policers Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-am65-cpsw-multi-rx-v1-3-0704b0cb6fdc@kernel.org> References: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> In-Reply-To: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3680; i=rogerq@kernel.org; h=from:subject:message-id; bh=E3unqPthK3jtIV9iITSd5L7XKv4kRv1ZvHzNZ1sC+Ng=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmYacDyh2d1fZPYMIVc3TmIklqBw/bT/XR4IBrJ 56U7ijKBWCJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZmGnAwAKCRDSWmvTvnYw k8XND/9edNzIVwICrDZttSUphRRyNSk8wG/iQNa6tSR30nOQJAbpKRS0xne9aaH/HBFPdRSA8UC h6CE03w7cr9RE2jCEgGUAq4pi3gTWm54GAlvl4zrcxHihCR2Qym61I3mwJ90eJAn9PvB+rfPXBh 4XjLQrr57z2saTuNZlvTqJ+pwM7DoZ09qRf0w34fojpdi5y6llVXszuR4yddjj/AO0NhSVJXUj2 /CmakUcqwwx8phgAG3xfBbPWMvgrxu5wt92MS+ncFUy3hBXOq+ayUftIffwp29JRmQIt43tg3qo n27wDYsprWWQfNbmByLU59gpGeHcYY4DU35tg7JPBdzT/q2UHvzmunG9xS5KO32+QRB0G7RRbyd 9fsOjHBuwq+Yt/+BimBewRQOos2zDDjnAmEsgQbe9uOL2DJv++xiSvONsTr8+CxYtEHze+fWqnt SImqXBN5ZgmO62IA/YyzJCQ5XrqTnxcYYtr1xiIdm5jbeFAnbxXpQLiU9D3ypd7o6tkiNDXRmCO kGg53X60Zm8TiS46DXodpvwzxAhQI57ER66gJeAbM0gLpBQyvKCzUxfUvML7/L2Jy1LzWio3jMc IgfHQt0VgDLM7iObx6hMsGAdI9VAX8agCa1MF2r1falhbXDcP0iFsXE7o8ZyI4/ZDWeRHpq/YaX wDhzkB+wk3qngPQ== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Use regfields for number of ALE Entries and Policers. The variants that support Policers/Classifiers have the number of policers encoded in the ALE_STATUS register. Use that and show the number of Policers in the ALE info message. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 25 +++++++++++++++++++------ drivers/net/ethernet/ti/cpsw_ale.h | 3 +++ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 5afe9fdd6402..07a60e9eafbd 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -103,7 +103,7 @@ struct cpsw_ale_dev_id { #define ALE_UCAST_TOUCHED 3 #define ALE_TABLE_SIZE_MULTIPLIER 1024 -#define ALE_STATUS_SIZE_MASK 0x1f +#define ALE_POLICER_SIZE_MULTIPLIER 8 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) { @@ -1303,6 +1303,9 @@ static const struct reg_field ale_fields_cpsw_nu[] = { /* CPSW_ALE_IDVER_REG */ [MINOR_VER] = REG_FIELD(ALE_IDVER, 0, 7), [MAJOR_VER] = REG_FIELD(ALE_IDVER, 8, 10), + /* CPSW_ALE_STATUS_REG */ + [ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7), + [POLICERS] = REG_FIELD(ALE_STATUS, 8, 15), }; static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { @@ -1404,7 +1407,7 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) { const struct cpsw_ale_dev_id *ale_dev_id; struct cpsw_ale *ale; - u32 ale_entries, rev_major, rev_minor; + u32 ale_entries, rev_major, rev_minor, policers; int ret; ale_dev_id = cpsw_ale_match_id(cpsw_ale_id_match, params->dev_id); @@ -1446,9 +1449,7 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) if (ale->features & CPSW_ALE_F_STATUS_REG && !ale->params.ale_entries) { - ale_entries = - readl_relaxed(ale->params.ale_regs + ALE_STATUS) & - ALE_STATUS_SIZE_MASK; + regmap_field_read(ale->fields[ENTRIES], &ale_entries); /* ALE available on newer NetCP switches has introduced * a register, ALE_STATUS, to indicate the size of ALE * table which shows the size as a multiple of 1024 entries. @@ -1462,8 +1463,20 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; ale->params.ale_entries = ale_entries; } + + if (ale->features & CPSW_ALE_F_STATUS_REG && + !ale->params.num_policers) { + regmap_field_read(ale->fields[POLICERS], &policers); + if (!policers) + return ERR_PTR(-EINVAL); + + policers *= ALE_POLICER_SIZE_MULTIPLIER; + ale->params.num_policers = policers; + } + dev_info(ale->params.dev, - "ALE Table size %ld\n", ale->params.ale_entries); + "ALE Table size %ld, Policers %ld\n", ale->params.ale_entries, + ale->params.num_policers); /* set default bits for existing h/w */ ale->port_mask_bits = ale->params.ale_ports; diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 58d377dd7496..bcbaaa7a1bca 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -15,6 +15,7 @@ struct cpsw_ale_params { void __iomem *ale_regs; unsigned long ale_ageout; /* in secs */ unsigned long ale_entries; + unsigned long num_policers; unsigned long ale_ports; /* NU Switch has specific handling as number of bits in ALE entries * are different than other versions of ALE. Also there are specific @@ -33,6 +34,8 @@ struct regmap; enum ale_fields { MINOR_VER, MAJOR_VER, + ENTRIES, + POLICERS, /* terminator */ ALE_FIELDS_MAX, }; From patchwork Thu Jun 6 12:09:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 802211 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49603196428; Thu, 6 Jun 2024 12:10:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675803; cv=none; b=kVMXPLZJXAj19OCJP5Ec5MgdNYqsJlXWosZFYxABhDZ3/QS3ys6OAFqqomGP4AaMTSeJpmxOjf0ZnH8jCYjptU5vHRJBTn2A9jgn5U/INPNHNT1D62xBtikm2OwS1dRm+QQ9kcb1eVXsc8UZ1SXcBIpSSed4hWQE8kQDMgb5BvM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675803; c=relaxed/simple; bh=BvmwkuZlIp7KUqJlCXytZF18sbrRcmVkgruLanmMgJk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uLDTTx31vbj6BLSdVPE7dahLeDaFeXK3P5I/jVnjx1qEz6h0cJFGE9KoPPeetkSxp5x+2puDEOg7+9XFPxQgmkd+4QYYxIHJRk+TZvyQ/M0Qkl2GyB5647jjB7AcCYhYSPzq6DT/ZRxVPxAQoyrdSJEb+5Dme0ZQfIVt7n5KCe0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jqiio6u7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jqiio6u7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DA23DC4AF1A; Thu, 6 Jun 2024 12:09:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717675802; bh=BvmwkuZlIp7KUqJlCXytZF18sbrRcmVkgruLanmMgJk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jqiio6u72wsLy3pro0uvsZwcNMY3iJ8piktCzDCwKPYFhdGHKZK/yEIPEjO/c0+Sf VTAdMTYqfClfWvuVWcOeJvZg8wTUcsmB9tbVsGMKbV8WB50B6AiT7Q2AKALV1RSgZN L8EVxWU4/1pJG3zlSnli0nCGpc7t2Ka+QIYB/dm3YggU55RjMC6aDVgtCrG6lSAz5X FnS6ZMKyac/OBI51UFy+xo+rm6yo2CUEsyOwii9I8/dwdWxRxeRVtKb411kcO2KfOD OZKcFpBOzYNxj9PhXIS6KTSqWcetdXZxaORp8lOgWugixlO0I2u+csGrnMYT2lLtv/ L1WU+mzMYJH1Q== From: Roger Quadros Date: Thu, 06 Jun 2024 15:09:20 +0300 Subject: [PATCH RFC net-next 4/7] net: ethernet: ti: cpsw_ale: add Policer and Thread control register fields Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-am65-cpsw-multi-rx-v1-4-0704b0cb6fdc@kernel.org> References: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> In-Reply-To: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5916; i=rogerq@kernel.org; h=from:subject:message-id; bh=BvmwkuZlIp7KUqJlCXytZF18sbrRcmVkgruLanmMgJk=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmYacEajKD5vy3GGpysv1klZ8AcEVPU6aFeecur r2UKo7N5DaJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZmGnBAAKCRDSWmvTvnYw k0rkEAC3F1IwLBwhlB4sNGCR3k1d5SaHYVuuddYz7QVFX2wBXiY7O+GUb622/YUes4uYyNkAgz/ Lv9CeENCGgbQzk4YAvZaBhMprjkK6r0xy5CKkVJvWq1QPHlvUxU496BH6igJSPxp4Twul830HTF TztXWt/l8lmb9Mov+ItkBZ6z4iJkPFpPtQKBAV6mgTFV7gfx6SIPyKa4bWSTzks54LhvSeMAiei MI0st1BbtTpgbo8PU7+OfBuoGcrnvn1zOINH9mBV7eiARCDqZnoao7EdiJDrPfLWU1V9CtWOg12 JnfQDhN9NR7JtDwzxyzfY00aPcOWXaGej/SnPOsB02ZmnPzG22zvmLQqsEC+yXC1vCkNF+OZea5 CprA2gsjNafRvrIE5p8iSJYdJ9eC0JsP228RCs1FQ3ibvBMhoQQZHw0NaJssdJ4UGdjg50X6bsN e63AGsKJb8g5fFAjVzAV5TP36kFZi9flDMJfonsLF+XrwJ4KjubdBCjPSET3PG29a21D2dkghS7 SP1bBakEjBiaeU5Wk3A58g1y0Q4XWNEnJbcfmApENN/q8M2flgyu4FaGrxVnEOAFrx1QIntylAd 3QZGERPH/Aiuzj+cfDd+Q8rFUYxEW4K+lrJQUpGupVwYLCDIdCgpAk7Iyxcg9otm810VVOzbNGL +QpGc+Ejac9bTyw== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Adds regfileds for Policer registers and Thread mapping/control registers. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 86 ++++++++++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 41 ++++++++++++++++++ 2 files changed, 127 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 07a60e9eafbd..cbcc6573d7f3 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -46,6 +46,24 @@ #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) +#define ALE_POLICER_PORT_OUI 0x100 +#define ALE_POLICER_DA_SA 0x104 +#define ALE_POLICER_VLAN 0x108 +#define ALE_POLICER_ETHERTYPE_IPSA 0x10c +#define ALE_POLICER_IPDA 0x110 +#define ALE_POLICER_PIR 0x118 +#define ALE_POLICER_CIR 0x11c +#define ALE_POLICER_TBL_CTL 0x120 +#define ALE_POLICER_CTL 0x124 +#define ALE_POLICER_TEST_CTL 0x128 +#define ALE_POLICER_HIT_STATUS 0x12c +#define ALE_THREAD_DEF 0x134 +#define ALE_THREAD_CTL 0x138 +#define ALE_THREAD_VAL 0x13c + +#define ALE_POLICER_TBL_WRITE_ENABLE BIT(31) +#define ALE_POLICER_TBL_INDEX_MASK GENMASK(4, 0) + #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 /* ALE_AGING_TIMER */ @@ -1306,6 +1324,74 @@ static const struct reg_field ale_fields_cpsw_nu[] = { /* CPSW_ALE_STATUS_REG */ [ENTRIES] = REG_FIELD(ALE_STATUS, 0, 7), [POLICERS] = REG_FIELD(ALE_STATUS, 8, 15), + /* CPSW_ALE_POLICER_PORT_OUI_REG */ + [POL_PORT_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 31, 31), + [POL_TRUNK_ID] = REG_FIELD(ALE_POLICER_PORT_OUI, 30, 30), + [POL_PORT_NUM] = REG_FIELD(ALE_POLICER_PORT_OUI, 25, 25), + [POL_PRI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 19, 19), + [POL_PRI_VAL] = REG_FIELD(ALE_POLICER_PORT_OUI, 16, 18), + [POL_OUI_MEN] = REG_FIELD(ALE_POLICER_PORT_OUI, 15, 15), + [POL_OUI_INDEX] = REG_FIELD(ALE_POLICER_PORT_OUI, 0, 5), + + /* CPSW_ALE_POLICER_DA_SA_REG */ + [POL_DST_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 31, 31), + [POL_DST_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 16, 21), + [POL_SRC_MEN] = REG_FIELD(ALE_POLICER_DA_SA, 15, 15), + [POL_SRC_INDEX] = REG_FIELD(ALE_POLICER_DA_SA, 0, 5), + + /* CPSW_ALE_POLICER_VLAN_REG */ + [POL_OVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 31, 31), + [POL_OVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 16, 21), + [POL_IVLAN_MEN] = REG_FIELD(ALE_POLICER_VLAN, 15, 15), + [POL_IVLAN_INDEX] = REG_FIELD(ALE_POLICER_VLAN, 0, 5), + + /* CPSW_ALE_POLICER_ETHERTYPE_IPSA_REG */ + [POL_ETHERTYPE_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 31, 31), + [POL_ETHERTYPE_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 16, 21), + [POL_IPSRC_MEN] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 15, 15), + [POL_IPSRC_INDEX] = REG_FIELD(ALE_POLICER_ETHERTYPE_IPSA, 0, 5), + + /* CPSW_ALE_POLICER_IPDA_REG */ + [POL_IPDST_MEN] = REG_FIELD(ALE_POLICER_IPDA, 31, 31), + [POL_IPDST_INDEX] = REG_FIELD(ALE_POLICER_IPDA, 16, 21), + + /* CPSW_ALE_POLICER_TBL_CTL_REG */ + /** + * REG_FIELDS not defined for this as fields cannot be correctly + * used independently + */ + + /* CPSW_ALE_POLICER_CTL_REG */ + [POL_EN] = REG_FIELD(ALE_POLICER_CTL, 31, 31), + [POL_RED_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 29, 29), + [POL_YELLOW_DROP_EN] = REG_FIELD(ALE_POLICER_CTL, 28, 28), + [POL_YELLOW_THRESH] = REG_FIELD(ALE_POLICER_CTL, 24, 26), + [POL_POL_MATCH_MODE] = REG_FIELD(ALE_POLICER_CTL, 22, 23), + [POL_PRIORITY_THREAD_EN] = REG_FIELD(ALE_POLICER_CTL, 21, 21), + [POL_MAC_ONLY_DEF_DIS] = REG_FIELD(ALE_POLICER_CTL, 20, 20), + + /* CPSW_ALE_POLICER_TEST_CTL_REG */ + [POL_TEST_CLR] = REG_FIELD(ALE_POLICER_TEST_CTL, 31, 31), + [POL_TEST_CLR_RED] = REG_FIELD(ALE_POLICER_TEST_CTL, 30, 30), + [POL_TEST_CLR_YELLOW] = REG_FIELD(ALE_POLICER_TEST_CTL, 29, 29), + [POL_TEST_CLR_SELECTED] = REG_FIELD(ALE_POLICER_TEST_CTL, 28, 28), + [POL_TEST_ENTRY] = REG_FIELD(ALE_POLICER_TEST_CTL, 0, 4), + + /* CPSW_ALE_POLICER_HIT_STATUS_REG */ + [POL_STATUS_HIT] = REG_FIELD(ALE_POLICER_HIT_STATUS, 31, 31), + [POL_STATUS_HIT_RED] = REG_FIELD(ALE_POLICER_HIT_STATUS, 30, 30), + [POL_STATUS_HIT_YELLOW] = REG_FIELD(ALE_POLICER_HIT_STATUS, 29, 29), + + /* CPSW_ALE_THREAD_DEF_REG */ + [ALE_DEFAULT_THREAD_EN] = REG_FIELD(ALE_THREAD_DEF, 15, 15), + [ALE_DEFAULT_THREAD_VAL] = REG_FIELD(ALE_THREAD_DEF, 0, 5), + + /* CPSW_ALE_THREAD_CTL_REG */ + [ALE_THREAD_CLASS_INDEX] = REG_FIELD(ALE_THREAD_CTL, 0, 4), + + /* CPSW_ALE_THREAD_VAL_REG */ + [ALE_THREAD_ENABLE] = REG_FIELD(ALE_THREAD_VAL, 15, 15), + [ALE_THREAD_VALUE] = REG_FIELD(ALE_THREAD_VAL, 0, 5), }; static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index bcbaaa7a1bca..c697d2e3e586 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -36,6 +36,47 @@ enum ale_fields { MAJOR_VER, ENTRIES, POLICERS, + POL_PORT_MEN, + POL_TRUNK_ID, + POL_PORT_NUM, + POL_PRI_MEN, + POL_PRI_VAL, + POL_OUI_MEN, + POL_OUI_INDEX, + POL_DST_MEN, + POL_DST_INDEX, + POL_SRC_MEN, + POL_SRC_INDEX, + POL_OVLAN_MEN, + POL_OVLAN_INDEX, + POL_IVLAN_MEN, + POL_IVLAN_INDEX, + POL_ETHERTYPE_MEN, + POL_ETHERTYPE_INDEX, + POL_IPSRC_MEN, + POL_IPSRC_INDEX, + POL_IPDST_MEN, + POL_IPDST_INDEX, + POL_EN, + POL_RED_DROP_EN, + POL_YELLOW_DROP_EN, + POL_YELLOW_THRESH, + POL_POL_MATCH_MODE, + POL_PRIORITY_THREAD_EN, + POL_MAC_ONLY_DEF_DIS, + POL_TEST_CLR, + POL_TEST_CLR_RED, + POL_TEST_CLR_YELLOW, + POL_TEST_CLR_SELECTED, + POL_TEST_ENTRY, + POL_STATUS_HIT, + POL_STATUS_HIT_RED, + POL_STATUS_HIT_YELLOW, + ALE_DEFAULT_THREAD_EN, + ALE_DEFAULT_THREAD_VAL, + ALE_THREAD_CLASS_INDEX, + ALE_THREAD_ENABLE, + ALE_THREAD_VALUE, /* terminator */ ALE_FIELDS_MAX, }; From patchwork Thu Jun 6 12:09:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 803159 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7DA7196450; Thu, 6 Jun 2024 12:10:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675806; cv=none; b=YkAEWusFarkzeHRna/wnepX6HS31XtV0pbxHYMcVDDRFtblicPCdYRVb7LKEJOrQwJ8GuNF8hzwVWPLNgKyvBdFUHl802Uyfjha5JDGCMYSAZ2cGZvvsFVgEbk05M+ClVbgFHpP7YkCFpNMSe7O9pnUgKf/wC5bOQbkf6YvcIMA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675806; c=relaxed/simple; bh=w895/2slqo6enBO8SZknnRcbpa1vLtMNWX/hte4CCD8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KC/B0Kl7m4Swjupdcj/pdxQ824+W673OiRy9Oz3//inf2z0WxVcH72pmzrWbt+dYBnNkA5sj8R65lzxs7SBMLo7c2ujc1IQWEDCHgMPvRzpaTg34g2bPeYuPr0x/hO3qq2D/xtl4pVg+32SvxMt+Ipero1ZNPJB/sV7rH3zFl38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=t7vgTnb9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="t7vgTnb9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59CE3C4AF1D; Thu, 6 Jun 2024 12:10:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717675806; bh=w895/2slqo6enBO8SZknnRcbpa1vLtMNWX/hte4CCD8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=t7vgTnb96JNzQIT4YC7RcRWB2xWs7Fk7CjSHpNB4pQ4OwMLgU9h0mjfs5LCFqt+z+ cCiY/w4gmSRHBd1TpYT72HTCPzW9nQhprOLQBnV3BJZw50n+0yz8kex4wauGWLT4re mRusDznW9OleE5NvRHf/xTKVH9WEcV5bo/TnMqZaMyGODFQj9jt6dBREOPFp/PbFNc 0e6Qb+14OKB1MIjXykn8kbrLxbeNXg9UYaGrwCNgSl37m15atyGUczWypx9FK+c7DO YSIc/ZZqN30AG2EQv70EbmZX6NDP2qjUkBWlNukne8RIj53lWT/waE8HppktJrjspf vgfjmBESUpXKg== From: Roger Quadros Date: Thu, 06 Jun 2024 15:09:21 +0300 Subject: [PATCH RFC net-next 5/7] net: ethernet: ti: cpsw_ale: add policer/classifier helpers Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-am65-cpsw-multi-rx-v1-5-0704b0cb6fdc@kernel.org> References: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> In-Reply-To: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2002; i=rogerq@kernel.org; h=from:subject:message-id; bh=w895/2slqo6enBO8SZknnRcbpa1vLtMNWX/hte4CCD8=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmYacGZ3z57FrkpP6WF4Kraavar3qosuFeGB/lt fagy9mVOkGJAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZmGnBgAKCRDSWmvTvnYw kxJTEACWyUyTbbG806GxItJyS1sMPcilZO0PnCMinaqP6zQl7T6GSaSHMD+mOqMETX5pFnp0i8q YuJqEgdv5mJASKncPKdbuzjXaaAs3Xa+1/4SE8QSDuncqTN4avMi4bQBlNlUCF68G6GqwMnFAQV TApmrGTlUEKV6UooQuicR8OlEB2pTF0UJCu5i28W2mDQv7cbRvkZYwqxQsk3CmluPUMAjyqd89Z fJnTBMwIRqJoHXc4lKRmUMRHvH7pG0kll5f3QJQCvZDH7s6BYYdFtwghrKHsT48Vi2zmz2dAk+U pNR7yY1NwxEA5I8qnZXyvBbxe+UEnoS+wRCTB6+gkSEvXeYvrdQgPe0VG6rxEjAnfFldJ94IcsC S/GyoYYQUZEM1K7mpvkZI5qxjDnFT7i74eSipjuE/gIDdYHECeWut+ssb9B1ImM02miFtKlgPMl pkIXpSsINODvdcLIb7AFaMFAL0H0DC5VGKh80rUXdBQTE/w6S42gFcm1XMTsKvYdcniSP56/4lR Udg35GiBPO4CJKYaOF2Je/jMXz02TJF2XK0r/vZnaJ5q9rqw+13fp6ophFbHpPlYzz/QfDJVFWM j2FAzkeENSIfgwmznrTXVB2i56ogccnsS95TQ7Fwd/L583VrzWeyKrH36CsBvAMxolLRVQG5ThB lS8qVSMqb3pReNw== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 The Policer registers in the ALE register space are just shadow registers and use an index field in the policer table control register to read/write to the actual Polier registers. Add helper functions to Read and Write to Policer registers. Also add a helper function to set the thread value to classifier/policer mapping. Any packet that first matches the classifier will be sent to the thread (flow) that is set in the classifer to thread mapping table. If not set then it goes to the default flow. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index cbcc6573d7f3..9f0a3b960f74 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1626,3 +1626,27 @@ u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale) { return ale ? ale->params.ale_entries : 0; } + +/* Reads the specified policer index into ALE POLICER registers */ +static void cpsw_ale_policer_read_idx(struct cpsw_ale *ale, u32 idx) +{ + idx &= ALE_POLICER_TBL_INDEX_MASK; + writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL); +} + +/* Writes the ALE POLICER registers into the specified policer index */ +static void cpsw_ale_policer_write_idx(struct cpsw_ale *ale, u32 idx) +{ + idx &= ALE_POLICER_TBL_INDEX_MASK; + idx |= ALE_POLICER_TBL_WRITE_ENABLE; + writel_relaxed(idx, ale->params.ale_regs + ALE_POLICER_TBL_CTL); +} + +/* enables/disables the custom thread value for the specified policer index */ +static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx, + u32 thread_id, bool enable) +{ + regmap_field_write(ale->fields[ALE_THREAD_CLASS_INDEX], idx); + regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id); + regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0); +} From patchwork Thu Jun 6 12:09:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 802210 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65702196450; Thu, 6 Jun 2024 12:10:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675810; cv=none; b=MHursesY3IW1Yy9TbzkJnPAttdDVY6hbr1KBrh76lBfhpxl1iU2Q2fn7C3H1sgZj3hUPC0RRvZCx8iyTY4yTXPDzvJunnQsIffUABAwnk8Bbx1CqzzUb76gIEz9RERk1P+2AGlRrfxt8IyjEpKdAuk0+36RR+ARNT9WeOYBf30E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675810; c=relaxed/simple; bh=AzsUjVFmjg0jtjXbWRhvwodxTf4nMYSUuXUeIdNsGxA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SZ8gtzlws4m89wxAD7sUWQx9l/+9P/f0+MY1EYz21L54yPEP2l1SfY3bv8SgND+bZYJ69ZltVFkXwbwQFyS2T5NvO6SLM5+bTkRWtRWJqxfWvhUAfP8wRdsMBsihQzDw2CNr6FPLi1KkyoU0hm/PgsbTgqjSOw0QmtSNtf8U1H4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Tp6b3gF6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Tp6b3gF6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CCB1FC4AF0A; Thu, 6 Jun 2024 12:10:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717675809; bh=AzsUjVFmjg0jtjXbWRhvwodxTf4nMYSUuXUeIdNsGxA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Tp6b3gF6mEA4ur7hK+0YGAbiOAi/t2sZfi7WWGhAd7riSyzYmarHjQZP5ASDwRAwf htxn3DtldJuf8SB77k7npNJ5jxpEzSE/TuZkwQTw3mlu7C5brbcD7yGnz9dcugN0hk bKYPb8W7QlePsb25RpBM1dyoXpBqbi/Mbvz8Y8tJH6/Oq+BP+QJYJP9XlvCN1uD/Fi i4Qx4kyij1y7gXfGO0Ds8NEzzuosveYAJkNMs9Imc43qqlVpA1u4gucwOf5bn93DL3 WNYubJRWRStKugsE5ykzjQVp/wEd/8QIXuppr6yd25YljohgHnrf3GGd3URoEG1//m C2TnDuyJtDWsQ== From: Roger Quadros Date: Thu, 06 Jun 2024 15:09:22 +0300 Subject: [PATCH RFC net-next 6/7] net: ethernet: ti: cpsw_ale: add helper to setup classifier defaults Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-am65-cpsw-multi-rx-v1-6-0704b0cb6fdc@kernel.org> References: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> In-Reply-To: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Siddharth Vadapalli Cc: Andrew Lunn , srk@ti.com, vigneshr@ti.com, danishanwar@ti.com, pekka Varis , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Roger Quadros X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3566; i=rogerq@kernel.org; h=from:subject:message-id; bh=AzsUjVFmjg0jtjXbWRhvwodxTf4nMYSUuXUeIdNsGxA=; b=owEBbQKS/ZANAwAIAdJaa9O+djCTAcsmYgBmYacHiIGD97H8XcRVirr1TwGS3vqSQBNOshk8F IDwFdzdOP+JAjMEAAEIAB0WIQRBIWXUTJ9SeA+rEFjSWmvTvnYwkwUCZmGnBwAKCRDSWmvTvnYw kwj0EACubtUr0bQcWYauEiLmM+z+70MGuPw2XXMH1Iws8q+A0MPIb0YlborDiEAXG7B9yqDcK1Y +/jc2NXB0lmi+bJnfHcIVXPcXQ7WirLxFyCg2IzLeRV1A2po1P/RoRGm/2Z+NpDgBaWJYmTktqs YIOsnmhXOaFHZf2XwxyrBPXQUbDtDVUTlfa9iJCe6LdSGqCwBzANtyTKZyOzjsHbOn4ohYGQzsE oke+M0zOpb2EGe/72LYXs8MaYSAggWqVyEBDiWuc9Zhh7BfZs88rVEIy6TYHva9tLfHzdNfgxvB gYDRYrJoY+tQZVXamfHVvIrjT2dwQFA2/wKBPUJ5krZ8fCsp1yjqU+WXrK2x5lxm1EIUdyBVApK Kh9om9RvoAr+UqU7hzO//kARsFe9VKDnecRkEeOnqkP7KBlc4kgrYNggjXvh1w84J1oFzfT+N3m xRuEU9qL5srbHfWMKC3Jh5RZSwtVkCmxGYhvrLUR8Qs8npvC0iAdT6v4a9d5wVkUkUwpHfEZqKN 9LuSzn83xN7uL8VNsWVjHzvnzTrEZq1NqEu+9XI6I0DxOATZG4zQeRy/e+38bd/wJhbi+JEam/1 qGEn462IEq6EJYL5UILthxsHyYTTAQEZ/FoHu34MgdGsBQG+rehPJDN12nDLDDxdJZuuk3Y/mgN KvJzPwI3h54B3Ew== X-Developer-Key: i=rogerq@kernel.org; a=openpgp; fpr=412165D44C9F52780FAB1058D25A6BD3BE763093 Default behaviour is to have 8 classifiers to map 8 DSCP/PCP priorities to N receive threads (flows). N depends on number of RX channels enabled for the port. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/cpsw_ale.c | 57 ++++++++++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_ale.h | 1 + 2 files changed, 58 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 9f0a3b960f74..675d651bd647 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -1650,3 +1650,60 @@ static void cpsw_ale_policer_thread_idx_enable(struct cpsw_ale *ale, u32 idx, regmap_field_write(ale->fields[ALE_THREAD_VALUE], thread_id); regmap_field_write(ale->fields[ALE_THREAD_ENABLE], enable ? 1 : 0); } + +/* Disable all policer entries and thread mappings */ +static void cpsw_ale_policer_reset(struct cpsw_ale *ale) +{ + int i; + + for (i = 0; i < ale->params.num_policers ; i++) { + cpsw_ale_policer_read_idx(ale, i); + regmap_field_write(ale->fields[POL_PORT_MEN], 0); + regmap_field_write(ale->fields[POL_PRI_MEN], 0); + regmap_field_write(ale->fields[POL_OUI_MEN], 0); + regmap_field_write(ale->fields[POL_DST_MEN], 0); + regmap_field_write(ale->fields[POL_SRC_MEN], 0); + regmap_field_write(ale->fields[POL_OVLAN_MEN], 0); + regmap_field_write(ale->fields[POL_IVLAN_MEN], 0); + regmap_field_write(ale->fields[POL_ETHERTYPE_MEN], 0); + regmap_field_write(ale->fields[POL_IPSRC_MEN], 0); + regmap_field_write(ale->fields[POL_IPDST_MEN], 0); + regmap_field_write(ale->fields[POL_EN], 0); + regmap_field_write(ale->fields[POL_RED_DROP_EN], 0); + regmap_field_write(ale->fields[POL_YELLOW_DROP_EN], 0); + regmap_field_write(ale->fields[POL_PRIORITY_THREAD_EN], 0); + + cpsw_ale_policer_thread_idx_enable(ale, i, 0, 0); + } +} + +/* Default classifer is to map 8 user priorities to N receive channels */ +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch) +{ + int pri, idx; + int pri_thread_map[8][9] = { { 0, 0, 0, 0, 0, 0, 0, 0, }, + { 0, 0, 0, 0, 1, 1, 1, 1, }, + { 0, 0, 0, 0, 1, 1, 2, 2, }, + { 1, 0, 0, 1, 2, 2, 3, 3, }, + { 1, 0, 0, 1, 2, 3, 4, 4, }, + { 1, 0, 0, 2, 3, 4, 5, 5, }, + { 1, 0, 0, 2, 3, 4, 5, 6, }, + { 2, 0, 1, 3, 4, 5, 6, 7, } }; + + cpsw_ale_policer_reset(ale); + + /* use first 8 classifiers to map 8 (DSCP/PCP) priorities to channels */ + for (pri = 0; pri < 8; pri++) { + idx = pri; + + /* Classifier 'idx' match on priority 'pri' */ + cpsw_ale_policer_read_idx(ale, idx); + regmap_field_write(ale->fields[POL_PRI_VAL], pri); + regmap_field_write(ale->fields[POL_PRI_MEN], 1); + cpsw_ale_policer_write_idx(ale, idx); + + /* Map Classifier 'idx' to thread provided by the map */ + cpsw_ale_policer_thread_idx_enable(ale, idx, + pri_thread_map[num_rx_ch - 1][pri], 1); + } +} diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index c697d2e3e586..c3ac6b9e94cf 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -193,5 +193,6 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask); void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, bool add); +void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch); #endif From patchwork Thu Jun 6 12:09:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 803158 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92581195B2F; Thu, 6 Jun 2024 12:10:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675813; cv=none; b=Iva2ZvKIvBtCPWPWTMR9XwK9lfVg9A2Po3LXQ8rs4Y0CbHfsMkxC74EOOfAiwNi53UNxgtVvot5rNF3fpHfiuj+qAZo2QPWcE69kK1tolbW74ZYii5EwWxKlHEIPHolEWqHWqEZWoKtdWrkowByme7N/EQdx5tNV+FgX+TvpLsc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717675813; c=relaxed/simple; bh=9gvRWld+0F7eOJkm5HDn0iZvrcoNruU+wwvFd26mihw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r5cm038rWE48G1AXXM/9n92yw2hQo23g2OxgOGYJUukxG4mVGKL+41rhf0ANUER+SCwzQJeilvaAHyU+yWtYpiB4dYYNFQQPbVOandYc4ItaAD2UkV/uDaPBzHov1IqBXcu6ZVo9uwyuEp9tNAD+1GEvHmsm7hznFNMN9a6nifI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MlynfY2f; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MlynfY2f" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53FF0C2BD10; Thu, 6 Jun 2024 12:10:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717675813; bh=9gvRWld+0F7eOJkm5HDn0iZvrcoNruU+wwvFd26mihw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MlynfY2frYY4bCzmSpFENjNTXNGdiXXaXA7dlcKqKms99ZisDhXgbj9Ecjo5iHM7f Wx0UPnnAbvRu6/gUB8WsNAQ2M1KFHo7JNIuwWASoYIRwmHJJCL7l6HA+G57rJCJSYL E+MolKgcmxNXUujUcTQLYUj1DK8v1gqp0RxPts3jSx7Wh/6oaJonY/72JfMCc/61X/ xDx1UgcQTl46KUhbG3Iv4Qg7P1t0fEV3JG6NZ8h897CkQ+KA4/aRJT+P1sqOt+cOLV M9O8g7u8trPJF8x+nmrMEgrosII9Ki/DW5XyiMDmzsXXJ86CbhCdhyj8Seu0gCM3K0 M5cKGU8Zcrygg== From: Roger Quadros Date: Thu, 06 Jun 2024 15:09:23 +0300 Subject: [PATCH RFC net-next 7/7] net: ethernet: ti: am65-cpsw: setup priority to flow mapping Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240606-am65-cpsw-multi-rx-v1-7-0704b0cb6fdc@kernel.org> References: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> In-Reply-To: <20240606-am65-cpsw-multi-rx-v1-0-0704b0cb6fdc@kernel.org> To: "David S. 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The Classifier checks for PCP/DSCP priority in the packet and routes them to the appropriate flow. Signed-off-by: Roger Quadros --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 1e718d4671c9..7d810b143248 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -1952,6 +1952,9 @@ static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) } } + /* setup classifier to route priorities to flows */ + cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); + err: i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); if (i) {