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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 01/24] target/arm: Split out rebuild_hflags_common Date: Wed, 23 Oct 2019 11:00:34 -0400 Message-Id: <20191023150057.25731-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::843 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_ANY bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 29 ++++++++++++++++++----------- target/arm/helper.c | 26 +++++++++++++++++++------- 2 files changed, 37 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 297ad5e47a..ad79a6153b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -231,6 +231,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3140,15 +3143,18 @@ typedef ARMCPU ArchCPU; #include "exec/cpu-all.h" -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) @@ -3159,13 +3165,14 @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2) /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) -FIELD(TBFLAG_A32, VECLEN, 1, 3) -FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VECLEN, 1, 3) /* Not cached. */ +FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) /* Not cached. */ /* * We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime. This shares the same bits as * VECSTRIDE, which is OK as no XScale CPU has VFP. + * Not cached, because VECLEN+VECSTRIDE are not cached. */ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) /* @@ -3174,15 +3181,15 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ -FIELD(TBFLAG_A32, LSPACT, 18, 1) +FIELD(TBFLAG_A32, LSPACT, 18, 1) /* Not cached. */ /* For M profile only, set if we must create a new FP context */ -FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) +FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) /* Not cached. */ /* For M profile only, set if FPCCR.S does not match current security state */ -FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* Not cached. */ /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ @@ -3194,7 +3201,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) static inline bool bswap_code(bool sctlr_b) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0d9a2d2ab7..8829d91ae1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11054,6 +11054,22 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif +static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); + flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, + arm_to_core_mmu_idx(mmu_idx)); + + if (arm_cpu_data_is_big_endian(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (arm_singlestep_active(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + return flags; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11145,7 +11161,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: @@ -11153,9 +11169,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 0 x Inactive (the TB flag for SS is always 0) * 1 0 Active-pending * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { if (is_a64(env)) { if (env->pstate & PSTATE_SS) { flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); @@ -11166,10 +11182,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } } - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); From patchwork Wed Oct 23 15:00:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177319 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp907711ill; Wed, 23 Oct 2019 08:48:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqyqY1l57JlANBYjDYUZy+LweZNEyTQ8WDRhSM6czZcNa8tMkkV7ib/1sexzbMQVAIhTeop7 X-Received: by 2002:ac8:359d:: with SMTP id k29mr9399678qtb.96.1571845712540; Wed, 23 Oct 2019 08:48:32 -0700 (PDT) ARC-Seal: i=1; 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 02/24] target/arm: Split out rebuild_hflags_a64 Date: Wed, 23 Oct 2019 11:00:35 -0400 Message-Id: <20191023150057.25731-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::842 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A64 bits that will be cached. For now, the env->hflags variable is not used, and the results are fed back to cpu_get_tb_cpu_state. Note that not all BTI related flags are cached, so we have to test the BTI feature twice -- once for those bits moved out to rebuild_hflags_a64 and once for those bits that remain in cpu_get_tb_cpu_state. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 131 +++++++++++++++++++++++--------------------- 1 file changed, 69 insertions(+), 62 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 8829d91ae1..69da04786e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11070,6 +11070,71 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } +static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, + ARMMMUIdx mmu_idx) +{ + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + uint32_t flags = 0; + uint64_t sctlr; + int tbii, tbid; + + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); + tbid = (p1.tbi << 1) | p0.tbi; + tbii = tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid = p0.tbi; + tbii = tbid & !p0.tbid; + } + + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { + int sve_el = sve_exception_el(env, el); + uint32_t zcr_len; + + /* + * If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el != 0 && fp_el == 0) { + zcr_len = 0; + } else { + zcr_len = sve_zcr_len_for_el(env, el); + } + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + } + + sctlr = arm_sctlr(env, el); + + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + } + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { @@ -11079,67 +11144,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, uint32_t flags = 0; if (is_a64(env)) { - ARMCPU *cpu = env_archcpu(env); - uint64_t sctlr; - *pc = env->pc; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); - tbid = (p1.tbi << 1) | p0.tbi; - tbii = tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid = p0.tbi; - tbii = tbid & !p0.tbid; - } - - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el = sve_exception_el(env, current_el); - uint32_t zcr_len; - - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, current_el); - } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } - - sctlr = arm_sctlr(env, current_el); - - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ - if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } + flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } } else { @@ -11159,9 +11166,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - } - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); + flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); + } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: From patchwork Wed Oct 23 15:00:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177310 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp893303ill; Wed, 23 Oct 2019 08:36:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzxIt0Gh7UdYYF7okMnQxNnjOG8ZBTb68UV9M5xFGFDea7AuPy5KeeCGe01I6cOIbJoz+yf X-Received: by 2002:aa7:cc18:: with SMTP id q24mr11142214edt.150.1571845002665; Wed, 23 Oct 2019 08:36:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845002; cv=none; d=google.com; s=arc-20160816; b=NaH3aPKw+M5ImT1LY73PmVAd0EMNhY/s/UWfEtwkYPrXkE4K+BP2yOc2YcczHVyaDd drA7NyPyGnznGDnnspPDpQdlWiWPpjTrAlqCd6vKGyqSy6vcT42yB5MpB4CMvyjMJ5wR s1DC5N80qs53JH6srD3rqCjRf1XcbpHZCk5UDqnqW0QX2tEKwCbqQq8DpIvEp/2B+2vs 8faS8VC1khr0JzRTqyZ6Oxwb04TI5h0Xtn1Wo5m1letOOYEp9i9N7J4SEE+l2IawhSRM 0YiKv0OQXfux2Rs/dmSffmTaPdZC1YBnZHac8+FlvL3mUmJtj1QBeqY1gGZczAdm7YZk h2vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+UgAJ6EhcwGdb7pezBRTrZ79eaC+NjRs0dqrTWfzTFo=; b=lF+qrGWUZMwyNoKMUCZs8OSc3juO6V0AHjgSSQ9oaSGyONv3N9Ncdm1eV5ca3Uye8m vxiOuwLGgTIfppfzPxdhjwVsuAoUXfGw6z9HYmQDWIeGwVfmfdcXDpAiW60IbKYxgJQK t/lcysDl3Fq9FQraMCIzpaket3nJZlyVwmL4acKK0sjOEu8RoeYieWFipNPX7IhJVUYe AWWiXeLT46Whrx9ffIkWZB5U8jQWLCM0nCp2887W+mmF4Az0GP0Ba9T4C8FgMfKlin1T sx+nZxzd1LP3r3PyDTizrcBrdASOXdb1kFKWh/R9Fg8FSrUMfhCG1Bb3jYvcn67V3wjx FLWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PgnrO0uP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 03/24] target/arm: Split out rebuild_hflags_common_32 Date: Wed, 23 Oct 2019 11:00:36 -0400 Message-Id: <20191023150057.25731-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::741 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by all profiles. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 69da04786e..f05d042474 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11070,6 +11070,15 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, return flags; } +static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx, uint32_t flags) +{ + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11141,7 +11150,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags = 0; + uint32_t flags; if (is_a64(env)) { *pc = env->pc; @@ -11151,12 +11160,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { *pc = env->regs[15]; + flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); @@ -11166,8 +11174,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); } - - flags = rebuild_hflags_common(env, fp_el, mmu_idx, flags); } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine From patchwork Wed Oct 23 15:00:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177312 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp895990ill; Wed, 23 Oct 2019 08:38:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqzZgf/JHQzYqQTQHf7DuN8t+EF8ZUzoaXri0gsuqHltDWuWdVYPHLYJx3aMiZlxmUmcGxFo X-Received: by 2002:a17:906:5292:: with SMTP id c18mr33275762ejm.129.1571845129651; Wed, 23 Oct 2019 08:38:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845129; cv=none; d=google.com; s=arc-20160816; b=QMzZXRTkNggPndD7c+GglmKJu56JMjdGCJ1349TSK7KN0EkeDTylkEtpbyFhRes1jS ZSGjhBp7e2HALmZq+vxgylX4G+U1giFGVrsyPufG29AvGDJdi4mtfNnkoPhZBRbNbKUO IABwQKMD4+tJxyiqNnFCd/IqUbJJ/9CSqAucwz/Fg/OSbGkvFRqHNx+5wXihjR5VOw/T v5Fcc9A7Q1OyfMooaspn+BUmpbKu3hOSo1NKaX/F8CadmKt9zYELuhdGfW6lslFNNM55 aLVmbbWv7cKKsG2VQehD+uwpSi8nIN230NS8pbSFIDB2GOQEF0mNInyJx6fhwvnzykH7 1KkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wk2rFtSmeyIzF6QnNFgZDZnR49h41R/PQfqDCLolPT8=; b=Ucesc22k8AkGwh+Ya3QdKc0zcASaTXvOL571/IpPOLp6zE43auv0F1HXqdUEMAJWdR 4RHtX1b8S/4lMakqWWrJTnH3gyWI9rQgrrC8foZDd0xpiWSLtxpz1S8MUuZ7BQ7zTTUi WlcYwZkk7pVjPe54TlYVcBy/mpeDw4YrIiE7bk9gzk8pVd1NLKubCp4q1PIvfikKi4Hf 8x4tBek36c1u+rdy/IRiG2tSiGIYnaoBze3XGCuQPnpvX2rS7n6G7bgCdGWl7i+WV9JW ImERwlTS34TrLFg4NfW1eEDiGjNu42fDQ8BTUxvDlGLt4czIrPiibB460XcML4Dp94G1 9+GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m1Xi4wHU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 04/24] target/arm: Split arm_cpu_data_is_big_endian Date: Wed, 23 Oct 2019 11:00:37 -0400 Message-Id: <20191023150057.25731-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::742 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Set TBFLAG_ANY.BE_DATA in rebuild_hflags_common_32 and rebuild_hflags_a64 instead of rebuild_hflags_common, where we do not need to re-test is_a64() nor re-compute the various inputs. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 49 +++++++++++++++++++++++++++------------------ target/arm/helper.c | 16 +++++++++++---- 2 files changed, 42 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad79a6153b..4d961474ce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3108,33 +3108,44 @@ static inline uint64_t arm_sctlr(CPUARMState *env, int el) } } +static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, + bool sctlr_b) +{ +#ifdef CONFIG_USER_ONLY + /* + * In system mode, BE32 is modelled in line with the + * architecture (as word-invariant big-endianness), where loads + * and stores are done little endian but from addresses which + * are adjusted by XORing with the appropriate constant. So the + * endianness to use for the raw data access is not affected by + * SCTLR.B. + * In user mode, however, we model BE32 as byte-invariant + * big-endianness (because user-only code cannot tell the + * difference), and so we need to use a data access endianness + * that depends on SCTLR.B. + */ + if (sctlr_b) { + return true; + } +#endif + /* In 32bit endianness is determined by looking at CPSR's E bit */ + return env->uncached_cpsr & CPSR_E; +} + +static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) +{ + return sctlr & (el ? SCTLR_EE : SCTLR_E0E); +} /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { - return -#ifdef CONFIG_USER_ONLY - /* In system mode, BE32 is modelled in line with the - * architecture (as word-invariant big-endianness), where loads - * and stores are done little endian but from addresses which - * are adjusted by XORing with the appropriate constant. So the - * endianness to use for the raw data access is not affected by - * SCTLR.B. - * In user mode, however, we model BE32 as byte-invariant - * big-endianness (because user-only code cannot tell the - * difference), and so we need to use a data access endianness - * that depends on SCTLR.B. - */ - arm_sctlr_b(env) || -#endif - ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); } else { int cur_el = arm_current_el(env); uint64_t sctlr = arm_sctlr(env, cur_el); - - return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; + return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index f05d042474..4c65476d93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11061,9 +11061,6 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); - if (arm_cpu_data_is_big_endian(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); - } if (arm_singlestep_active(env)) { flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); } @@ -11073,7 +11070,14 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, uint32_t flags) { - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + bool sctlr_b = arm_sctlr_b(env); + + if (sctlr_b) { + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); + } + if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); return rebuild_hflags_common(env, fp_el, mmu_idx, flags); @@ -11122,6 +11126,10 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sctlr = arm_sctlr(env, el); + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); + } + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { /* * In order to save space in flags, we record only whether From patchwork Wed Oct 23 15:00:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177315 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp897559ill; Wed, 23 Oct 2019 08:40:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqzQYI6Oq+mZqmRPRUoSMf4osbclmG/pWzHSVSsER4sJrzmoK5deUAReu5mHMvynGVcwLHa1 X-Received: by 2002:ac8:2484:: with SMTP id s4mr6281863qts.350.1571845213072; Wed, 23 Oct 2019 08:40:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845213; cv=none; d=google.com; s=arc-20160816; b=wSaf86EpjtnJF4rjAxGVeFjuZOVc8/RsBYVPFBGW8kOMIiwnyig2ICEKvBs2Pki902 J6T5Vp1fuXinl6A1UOYCGn9J3qHKfIZBl97VykQpV6pDv9zKuyoOybbJw5jvYc4A6FLo KCkIat7m8vplrjqXku8ClYN9oB9XZkT2ccP3q87F6fIPx61Jtzt2sER03ASbz1ArAqMD i+IJaREG8RbCY0yOa56gsvIcn4ckgswGPURKFLCZk9vgZvRueXbFl1+V3v1gzos9QHK+ 6u/t1as3BuXPClFpUkSOXIKW2wfamb5ayhhcPd4xboSBW9XzBTIfs57cldflE5vQhS13 mGOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mDaUYtXyoxKyQ6YIW+CzLKUl72EI9Ve9jhEUulKMydM=; b=iS2uFp7P4WNfS6eipQnBszJg+s6tYFEn4Egvo5R0117gcUDl7Elxavt9SedGGfdgTM JzerZDFasuhCkimdjquXetyRJ2Wx+NiIy2EtRhL828OHn2iZb2cGNuCBZk14M5Puucnk yyKUQ3Tpn0svbHgQ8ayf5KI0asr70PaEEE86ApzzGYo7VpVX9vhupOA4XTgaKxgu7NQ7 QAFDhvf3gQvBMrBpGKebksq0abvKFPqUTORh/sG74vmgI/9h2OHKwIuwCP1Ngy9VC9+X K70AC99PFhrx0g9rsVFZbipqJneKIrpXLAebrypqDsHgRM3nJKSJ9luqmN+/HD9gyRNn uSfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gg4OUCU0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 05/24] target/arm: Split out rebuild_hflags_m32 Date: Wed, 23 Oct 2019 11:00:38 -0400 Message-Id: <20191023150057.25731-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::843 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_A32 bits that will be cached, and are used by M-profile. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 45 ++++++++++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4c65476d93..d4303420da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11083,6 +11083,29 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + uint32_t flags = 0; + + if (arm_v7m_is_handler_mode(env)) { + flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); + } + + /* + * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN + * is suppressing them because the requested execution priority + * is less than 0. + */ + if (arm_feature(env, ARM_FEATURE_V8) && + !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { + flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); + } + + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11168,7 +11191,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { *pc = env->regs[15]; - flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + + if (arm_feature(env, ARM_FEATURE_M)) { + flags = rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + } + flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); @@ -11204,20 +11233,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (arm_v7m_is_handler_mode(env)) { - flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); - } - - /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is - * suppressing them because the requested execution priority is less than 0. - */ - if (arm_feature(env, ARM_FEATURE_V8) && - arm_feature(env, ARM_FEATURE_M) && - !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { - flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); - } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); From patchwork Wed Oct 23 15:00:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177311 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp893675ill; Wed, 23 Oct 2019 08:36:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqzvn5zLmHnsPDN37Kc6Vr7/Ms80XWWtWzWYVsdWd9E9ctwo89uoP9u3bxsPWoAk7qgejq0u X-Received: by 2002:a50:8a90:: with SMTP id j16mr38847382edj.283.1571845019102; Wed, 23 Oct 2019 08:36:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845019; cv=none; d=google.com; s=arc-20160816; b=lqreShOQF4PC8hRqEpibm2r3ACNumoW7LRlJqOIxGRO+aTcgrIBanKQAeppHz9yZgU UiEkDY7RW4nz62Jt8kQkWlMkVmkLcn303g+XemUE0ma/fIRkt2xEzE7xsIz/z0Zkbcnv 4KGO6LgW+Vw6qp99XEPRLqbqNwhbG5L6XFkBnSIf8ocB8bKwAk9mifekz8VaIcPb5xuI roKnYAi7oxmeMp8WMf6SW31P11n4EgKmTpQ47LJRCYy4e2DAWF+AO5tZls9Hc14wDS4x FY3kjDpmDx1V3CN6R7Nbqm64ZZnOqh/BHpkFd/AIcxFOTKLwUwghwEnBjJsk7LWZLuju CRtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=O5qTDR4/yunqOnDsae4ZjoUIG4TsLVXzaOK/t5hnYkI=; b=jGmF9oKYJ0pvBTdgVYu8YF0ry0rm7JpdEpdSl29MJOvlNqtGZxPYrWHT+Kjg97ZUAk 3/d8IOLrb1OM9QZL4i2aMgcYfhzCOcAzxKd4prKIrLd9ol7Fv/tqsjCGoFnxW0PhWKca /tHfCZy8g4ytIWDY66zSGLWZh3r367kf95///PV2O9Qa8L6Cs3y6FkmWwE8H7vdImm39 CUODMf/QM1rtFEzG4QoCvJ2TWXBhH/va18N77FksNHyvLOM6DznCQS7BVdHPjp2nxl74 rxj15EJn7+zZGCAVhPXrmKI2gOGonX8TT3Yod2f4bYZElifK18xfDydg8CT9ufht/gli pj8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pet1fu4e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 06/24] target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state Date: Wed, 23 Oct 2019 11:00:39 -0400 Message-Id: <20191023150057.25731-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::841 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist the computation of some TBFLAG_A32 bits that only apply to M-profile under a single test for ARM_FEATURE_M. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 49 +++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 26 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index d4303420da..296a4b2232 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11194,6 +11194,29 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (arm_feature(env, ARM_FEATURE_M)) { flags = rebuild_hflags_m32(env, fp_el, mmu_idx); + + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) + != env->v7m.secure) { + flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); + } + + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no + * active FP context; we must create a new FP context before + * executing any FP insn. + */ + flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); + } + + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); + } } else { flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); } @@ -11233,32 +11256,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { - flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); - } - - if (arm_feature(env, ARM_FEATURE_M) && - (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || - (env->v7m.secure && - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { - /* - * ASPEN is set, but FPCA/SFPA indicate that there is no active - * FP context; we must create a new FP context before executing - * any FP insn. - */ - flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); - } - - if (arm_feature(env, ARM_FEATURE_M)) { - bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; - - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); - } - } - if (!arm_feature(env, ARM_FEATURE_M)) { int target_el = arm_debug_target_el(env); From patchwork Wed Oct 23 15:00:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177296 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp860876ill; Wed, 23 Oct 2019 08:11:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLfCM6v+F2XFePW+WyZUkLWOFsPnsMFKNMRJJS6OWEKhMQdMKUwNgFzqKSTPgamGZbdpD+ X-Received: by 2002:aed:228e:: with SMTP id p14mr9663034qtc.190.1571843505228; Wed, 23 Oct 2019 08:11:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571843505; cv=none; d=google.com; s=arc-20160816; b=RnoCFpLdHWip1zIgq1sFeEOtObB/TlgHYAIY7tiifr+KIeEbVcHWryzynWPwU5Ym7t uVYykv7bcNfw17BUFAOCaufpSriAI5EqDbs3ImdBqBtWJlc2OGuVmam9bGiq9hDBzLcQ 2epS03Bg3igwl/RWDGA4xfzKk2/tFQyRDW9NYfT+sucVjWnWbhavD8QTfHDr/x3Ey97U s6fw1HSB2j8Cj5A7W9Y4bOH5rINPTpnYGSsqy0utJUEb8jyVP/LM46s5m3dJ8Dx8OoPp 6QTfPaHDtOSBu1mJHsQG0pXfpmDeIIQHKn76Klbrf8rP2UyA1fsvKEI+omL/fsPmLfxQ aMXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IBA+abtZ26hlRDDlZ8eTB3Pn4yNYwZChmFB+u2JQGOM=; b=fdcrPfkBB3AfYcCkOKTO9GUJeN5up0GD2h4Ns4h26Ls9ZS9v1cUAv/odaBE3FfUpIS o5a3JAk2Ud7Uacu/1YQHv39bbj0AWsdmxhJj7gPSPnecw8nLLUpNxj7dtouTnf+4gb8d kcle2BvihZx0m7fCkfigGV/ur2E9PTNOW4B6Ao/AOKqceilRr+psg1Hivej5oKXw88rU mru88bV9Sdi3cb2uBeUvS0jWkEtDa8lHfYys9yn6aaqOFdgEXdUKku561+OnM1jXZgoH lqpazPyH0FFOitUPexFxHp56o6CSAal6lOh+UhoXsx6GJ9jxKoHlYFzMD+2MRIfqK5JS WCpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kl7dFo28; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 07/24] target/arm: Split out rebuild_hflags_a32 Date: Wed, 23 Oct 2019 11:00:40 -0400 Message-Id: <20191023150057.25731-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::843 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently a trivial wrapper for rebuild_hflags_common_32. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 296a4b2232..d1cd54cc93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11106,6 +11106,12 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, + ARMMMUIdx mmu_idx) +{ + return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); +} + static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { @@ -11218,7 +11224,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags = rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + flags = rebuild_hflags_a32(env, fp_el, mmu_idx); } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); From patchwork Wed Oct 23 15:00:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177297 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp864839ill; Wed, 23 Oct 2019 08:14:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqyKPpT36PehypmkaFyXfLWusO2Tcb16qExdIygfFZrV25o7uh98KUr2bYJbQqzF84zZU0VJ X-Received: by 2002:aed:3908:: with SMTP id l8mr1608176qte.383.1571843686909; Wed, 23 Oct 2019 08:14:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571843686; cv=none; d=google.com; s=arc-20160816; b=zDZeEN0W9sJRPUnBR9M1To0Q5un7FcMNPdy2Fjz79ZHUdhjxkcJaPcVLcMceJDkfGl mmMQQfe9PrJrEVu8f1WbldrxpsUJt3cGUphnS3RWnxta+r2nzgniKtenbcHkyP6c4Ohp j2aEg/VBvz2VzKsUYPAoHXIj4PFvzID7EbW28FVKkcbXrSaOCdGkI8zjXSbc/v1wPYFC hSfGGrUPt0exDGQ5y8K0uyp0BxcTOm3MRw5dAOAo8JOW1klZISxNjEtrramNdI07FkOz sMWqJL45FDDHsdD3JiiH4m12GTWBh57LV+K9RLeyQCiDRMfmp/HWbMWfS5fmzsHVHdwH ChfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EExBny+oAa/2RvpDTj0xViQxKJSM6o83jutlTagIpwU=; b=G7Peq5PwtSqd24bpR4HQX+xUG/oI5AT7ClrWVXyDo5CPyA5fX0WwySiKG2MtTERxG9 yV0vJBKb9zLmMtOIKAjSrCnSj/N6dKYw+EHiLKnPi/SkSimA5l8zXSDakWTd2sA9fWnJ 8oIJN/1DWX9dsgaOnjMmRAK9qkCwVNJCYoY8KDU8grmsy0r1FjA7XllRxzujGUxC8XsI VUtFZ1UZ+gWcxAiRyfA0F3gBxx/WjAhYlT00EiG0psaxgI04aodMjISHydnOM824sTgY 9Be7GxOKDlhhCBegavpLjujozNKDM6Svf/64pUtAy5NeOoM9gJwJNEjVk8XvYItytppT jOmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BHgiuslL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 08/24] target/arm: Split out rebuild_hflags_aprofile Date: Wed, 23 Oct 2019 11:00:41 -0400 Message-Id: <20191023150057.25731-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::844 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create a function to compute the values of the TBFLAG_ANY bits that will be cached, and are used by A-profile. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index d1cd54cc93..ddd21edfcf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11106,18 +11106,28 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_aprofile(CPUARMState *env) +{ + int flags = 0; + + flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, + arm_debug_target_el(env)); + return flags; +} + static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - return rebuild_hflags_common_32(env, fp_el, mmu_idx, 0); + uint32_t flags = rebuild_hflags_aprofile(env); + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { + uint32_t flags = rebuild_hflags_aprofile(env); ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - uint32_t flags = 0; uint64_t sctlr; int tbii, tbid; @@ -11262,12 +11272,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } - if (!arm_feature(env, ARM_FEATURE_M)) { - int target_el = arm_debug_target_el(env); - - flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el); - } - *pflags = flags; *cs_base = 0; } From patchwork Wed Oct 23 15:00:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177301 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp877536ill; Wed, 23 Oct 2019 08:24:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqysqG6eMv0aC0FfzVs684bqKwOSTJHB8fDMNM6WoZz3bDrbfzgOdXALL08KL8vRUI230twM X-Received: by 2002:a50:9269:: with SMTP id j38mr19877216eda.5.1571844256012; Wed, 23 Oct 2019 08:24:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844256; cv=none; d=google.com; s=arc-20160816; b=bPHTvC9aXolUkfom2MmAd3Wt2wGl4s6ONiN9crOy5lBIMDEvJrBZ96CoO7teKG5vXi q98mWR8nIDOyTYSafqH9lBkWJdBT5zCInhNMojPOb0FZUg3dIt20j0kMSfhruEUxronp 73AJe9yjCyuWZu+6i4HWmO2nhQu0imwoPWv2D2j/ExwwFnW8kx6YuHqPcpJy+OaTS9N3 /xSDNBJ2HLpLP0LFWehip7A4Onm5kpBLxyCApwbwhCz+tP8al4zhoVvjOxuT1p2f60v8 Cd5Xt/a2P4+p0ftGjoRtsitAlORS63ORIeoA+B6dEDGS1Pfy76UZPoNLZieHwPf0i4z7 4zdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+w+DpqTaqyThsFD3h0g6qTaqlae+kRMVgywC4mwAkDA=; b=ig3JhtiF2abY+pdcIg6aGg18+lMLUw6R8S5DtGVAqpGNGn+M0XsoteufrDNyAtq8y1 BTUs3Z6MljnlyGo2xw9dfd/9gZ0xTInUTa4aVO6Q9nNrvwpbFdMhVcQQanzZXS51hpPe Ux2qh/vzLIXZ968fMc6rR2+CaX/ErFLftfEXjIoLw1J+TjJQYRJLDUbmn/w65cuJDzYI 2u5enmGIcw4xvyHkYRUZ652aQzip5B5LrJyvFjIINv4LiAB4que1i8jeqvFg3dDovbEr zmWxT5Q7ET6gt9/CC90Ghyc3TKIoHY99xpBGd+B1/eG7etTda8kZU0nHUzwLwxYJPnhN WIAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="tnqnVCH/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 09/24] target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state Date: Wed, 23 Oct 2019 11:00:42 -0400 Message-Id: <20191023150057.25731-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::842 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not need to compute any of these values for M-profile. Further, XSCALE_CPAR overlaps VECSTRIDE so obviously the two sets must be mutually exclusive. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index ddd21edfcf..e2a62cf19a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11235,21 +11235,28 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } else { flags = rebuild_hflags_a32(env, fp_el, mmu_idx); + + /* + * Note that XSCALE_CPAR shares bits with VECSTRIDE. + * Note that VECLEN+VECSTRIDE are RES0 for M-profile. + */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + flags = FIELD_DP32(flags, TBFLAG_A32, + XSCALE_CPAR, env->cp15.c15_cpar); + } else { + flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, + env->vfp.vec_len); + flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, + env->vfp.vec_stride); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); - flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } - /* Note that XSCALE_CPAR shares bits with VECSTRIDE */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - flags = FIELD_DP32(flags, TBFLAG_A32, - XSCALE_CPAR, env->cp15.c15_cpar); - } } /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine From patchwork Wed Oct 23 15:00:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177304 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp882233ill; Wed, 23 Oct 2019 08:28:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3OTHcBFkJOEN5IH9MhGjV4XN6snMjlTu/o+yivYfJrzAgLZvHO/I3qPSBFH7fMSZGE9Pn X-Received: by 2002:a17:907:105c:: with SMTP id oy28mr6386139ejb.299.1571844488597; Wed, 23 Oct 2019 08:28:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844488; cv=none; d=google.com; s=arc-20160816; b=xzBpWUuPJvH+Iv890AqaeMwTM1iqDo1Yhl3wIAPh2EgjDZ4R88dvvC8J00NXLCDId2 nb6lfVcUyqpylcj4qe0+fFHzMQDvc39P1jjyW4iTM9zHJJTGCx9qGg1w9E1G2RF6zEld mnhr8bpcD1DSKR+e0LehKo8jIZlq8S7eYoS2p9tjegfJfrHN3ahkeIa3hmvHCJRZTxvj hpJ147Iw90j2zwt1CXN74q0cko5BaRyWd6SzXBH272jC1tMnVJ9wvCK0GciVyu+zLcyf VqI3utRUsObnCTjlgjXeRMawG3a7hSfnmMMETDSsX3dHeMQv208OoEwPp/HJefuHzD9f x4Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v4LDoKiCDj8UEOXKdxGeWLogI6gqriKirwE9ruJcfe0=; b=oNV6okRLr6Ygoq4k1DEsfQKOycHehg1sAWlOfCCrOBulKBe/n1F/FJHVhcws/xcZSX gkKpwCBVybSdlWCuBVZxzcj5MZk/xj9K0ktI0Wmq09kihrmeWJBIGncjtypkskIMV8Aw dIvDVlXwGYJeqYiGoR30yD2VKFvJwNY9PfrawncmqYD2xt90F0p1KK3ZP+Rm6iTh8omw 7pOD0jP1zSUGrn/CoYY4yfx7yVd+EZMnY1NklxTdAwC19fOaptKvaQFKXFHJDq38IRcf dBSETTxSN/lD83UFNIOsmuEgRnnhRC/E4fDhR7pjNMInvY5jPhbeLrfG6V+c7KMvg7hN h3DQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pch7YEBH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 19si1682566edz.85.2019.10.23.08.28.08 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 23 Oct 2019 08:28:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pch7YEBH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNIYQ-00062o-S8 for patch@linaro.org; Wed, 23 Oct 2019 11:28:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35253) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNI8u-00089O-BZ for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iNI8r-0001GF-L7 for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:44 -0400 Received: from mail-qt1-x843.google.com ([2607:f8b0:4864:20::843]:44402) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iNI8r-00014z-Ei for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:41 -0400 Received: by mail-qt1-x843.google.com with SMTP id z22so12216025qtq.11 for ; Wed, 23 Oct 2019 08:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v4LDoKiCDj8UEOXKdxGeWLogI6gqriKirwE9ruJcfe0=; b=pch7YEBHcbkJ3G36TFQnhM/UL9PaTpFqbBNyr18NhZ9em5c89l9FC5BbzzErrpaL/x twr46E3i15KySqyHLzMRFVaf6iSlYbZLJ9nQGULn7jQLP9uhiHoXmTaMdJpVToNd3H0t 7g9+sFi1vDVcLv2tt5hXDcvxhseEyrhak1iX4WM2dCgplwaXNbbyX9mRCtUrXSpNYhu2 Zh88iWomFGJ1/tmNGyrPVtR0Zvev3oZ8Fixu30Ix2NT9+YpVEUbywr8pvHw6FMw1eIqj MthYRGE7obg14+ryc61LsweJsqQftGUGpTXL+eLzKXmsI5QVFM3ze5lrtEKfOxqos5Ue nKbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v4LDoKiCDj8UEOXKdxGeWLogI6gqriKirwE9ruJcfe0=; b=bE6Uc/r2NfAAHLprWiTwUUv59eCB03p0JJ68UpvYcrDjVQYAK3EJBGflHQvjJtU3co D/pUoCcZLnIHk/PGQwOgkpYQzK+rhQGKU5Ep1JW4Fnfz561oLKZymACla0dMlVetJqJ4 +SkB+OW1ACfub1PpphkML2sO9ccV3DudIt7OCurKREOgq8eY9zEm0jDDTuAnvFMz4Ygt TCymwF3twJKQWY8toKidjU5TzLiTl3X8xvoZyP9Q4tgSsrtf0Gwm+O0HiXLPvCpXqOph JluiuWhGeTiQwpnCvGZBh18XHIAjd3linAXiK79az0Cglt1uly+Tyt7DkiFYoXzznvdH z7xg== X-Gm-Message-State: APjAAAUjIPJ9sIyuRfBJBWWf5/va5QQ5AwhGhkvzdwzz3oL5yGj53bXZ lQME0nh65oAhSF5hDEZw9bj9nrevE84= X-Received: by 2002:ac8:542:: with SMTP id c2mr9880986qth.338.1571842875633; Wed, 23 Oct 2019 08:01:15 -0700 (PDT) Received: from localhost.localdomain (198-4-20-64.static.cosmoweb.net. [64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 10/24] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state Date: Wed, 23 Oct 2019 11:00:43 -0400 Message-Id: <20191023150057.25731-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::843 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist the variable load for PSTATE into the existing test vs is_a64. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index e2a62cf19a..398e5f5d6d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11197,7 +11197,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, ARMMMUIdx mmu_idx = arm_mmu_idx(env); int current_el = arm_current_el(env); int fp_el = fp_exception_el(env, current_el); - uint32_t flags; + uint32_t flags, pstate_for_ss; if (is_a64(env)) { *pc = env->pc; @@ -11205,6 +11205,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; @@ -11257,9 +11258,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); } + pstate_for_ss = env->uncached_cpsr; } - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State * 0 x Inactive (the TB flag for SS is always 0) @@ -11267,16 +11270,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, * 1 1 Active-not-pending * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. */ - if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) { - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && + (pstate_for_ss & PSTATE_SS)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); } *pflags = flags; From patchwork Wed Oct 23 15:00:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177300 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp875869ill; Wed, 23 Oct 2019 08:22:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJs5mUVn7o4RLqdBaB7xGYrCGZfr+QqM8sW21wSFqNElDl+TD++/eDs1zPdByC7u3pRnvJ X-Received: by 2002:a50:ff19:: with SMTP id a25mr10422420edu.181.1571844178382; Wed, 23 Oct 2019 08:22:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844178; cv=none; d=google.com; s=arc-20160816; b=G9+0hLAn8ueR/Kx+Ofl+1rw5dyWChCX1BDsAZBmOL9ojHv9DaFDZ1qIq2SkcFB2kQ1 BHiB1I/kyMl3Y+iXjMAh5RDd2lyLVVI3pzWlew8inXrRhnrvzgVmW7XO9xZPHsdXJI/Z ++9FJY8a7mTp+FiKwBQrZdu8cZRlDH5x/BEP+zqdRMinUQa4gJyfFLx/RAWhgmt7NYrp fV0kwnLFUNpDRVyaBafB01230C2hw0JGMPwVT0NE+M1bxUsWS+kaQYY3+Bhs0/y8gTTa mHAJoJTpwfRzdLfDKCiHgDouIifAUvSMJGsbWSDcRtoS5sQfXC7xa5RnHJ4f14VeTYjz BOAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HNW+DKXClNFoWE5mAVnYOdmYoSifNB4F8oskeNBuM9U=; b=nG7nA4m+mSSN+EiMKvJezjG4kstXNfHAtRhKNed2u9BaNUffuzOySgUCXgnsj++GKH 4zkYWN7X97QFDDF5zPCGo323ApF6TQ5oZjsmMvM5tVUrZ4ApJXGfat4+D5nINiDzxPY+ rSzcXkMurBxQO/WfpSTUNvPqvbpZQpze1pDLHd9PFZI5QkNictURTOEAP/WCqRE80bo/ wNvnzhUqOT3ZcXPSOoVtBGYe/iQg/r8Fp6PdDzfrsTJRX1XbH0zb2KTt3F1IdARdknQO xzC5dB4ZjRxZPK1HA3UTslT4r9lrouDj3EVHASB4WSvNOlh4CXqZNzuOj05cM5Ev1fY1 ZxaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NPGPOm9C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s15si5992420eds.217.2019.10.23.08.22.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 23 Oct 2019 08:22:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NPGPOm9C; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNITQ-0000kq-H7 for patch@linaro.org; Wed, 23 Oct 2019 11:22:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35131) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iNI8s-00086d-8t for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iNI8q-0001Dw-OT for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:42 -0400 Received: from mail-qt1-x841.google.com ([2607:f8b0:4864:20::841]:36365) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iNI8o-00015R-LL for qemu-devel@nongnu.org; Wed, 23 Oct 2019 11:01:40 -0400 Received: by mail-qt1-x841.google.com with SMTP id d17so18125848qto.3 for ; Wed, 23 Oct 2019 08:01:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HNW+DKXClNFoWE5mAVnYOdmYoSifNB4F8oskeNBuM9U=; b=NPGPOm9CWTUgQoSl2rMq7xjPhiZsh6cQc40fR2j5H7rxtL7wRftv8sHsrtaFz/L4ud O7VsXruMvHv7l1EDcgNnSbfeRjQtWjMEWVjSci5FMi46J23lCeQ4+7tMn86/whdBwQH2 PmVf+ESWvCXI7XYCVyQkKArDAZ5QtJax4fm85wR8Lp0oY55H/lg2tk8EjPbVSrhRhpFI s9GQVP5pIDvm3c649EnPx95dcYbf+UC5MbP63l4xEQsy6ykGJLs7UK7g7mv2pUy5eSsy oTwDw7rGfxL+8QZ+MnWPuD9mOBmeIf+uJ5RGYg5UH6/YHmgXhu/1rTa8AtEXslUQkqBa Oi4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HNW+DKXClNFoWE5mAVnYOdmYoSifNB4F8oskeNBuM9U=; b=I0sSA721Jo7rab87rtP+TAGMjSCnDCxuez9ZGwtIEKTbK5nVFZPyKVyh6ohxmVjX8p Tsb2o3SFhEYUaQXTNtTaCfqEY20N1mTRzRomFrj/datXMChL2oF5qdoJKl7N4D6O16nN nV+N2ZSM3aG3qEzasyqIEFf6Q4PLOKfTzI2eg8zIfJWhFDv8R9R1qNWcC0Drmf/Th8cu 1NLXeluOQ12o0ttjiFx6acVUTbOIyCR/iODYGC3ojz1VYI0HSC9TojLtNHGjSBNZNC68 ddlNTx9qDkxy/kbmK60/4v2dr8QmboMFC4sEVabE93stRpib0dpBTfzD2lXfDg38SanX xK1Q== X-Gm-Message-State: APjAAAWQyyu///pIfNyB2SrRw9H4r85Z7VDnTBevT02R/MzfbmW8JDto 6ceAfySGic5jgyemRdYMSdIBwhxbgbY= X-Received: by 2002:aed:3f21:: with SMTP id p30mr10025551qtf.236.1571842877297; Wed, 23 Oct 2019 08:01:17 -0700 (PDT) Received: from localhost.localdomain (198-4-20-64.static.cosmoweb.net. [64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 11/24] target/arm: Hoist computation of TBFLAG_A32.VFPEN Date: Wed, 23 Oct 2019 11:00:44 -0400 Message-Id: <20191023150057.25731-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::841 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are 3 conditions that each enable this flag. M-profile always enables; A-profile with EL1 as AA64 always enables. Both of these conditions can easily be cached. The final condition relies on the FPEXC register which we are not prepared to cache. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- target/arm/helper.c | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d961474ce..9909ff89d4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3192,7 +3192,7 @@ FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) * the same thing as the current security state of the processor! */ FIELD(TBFLAG_A32, NS, 6, 1) -FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Not cached. */ +FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* For M profile only, set if FPCCR.LSPACT is set */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 398e5f5d6d..89aa6fd933 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11088,6 +11088,9 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, { uint32_t flags = 0; + /* v8M always enables the fpu. */ + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); } @@ -11119,6 +11122,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { uint32_t flags = rebuild_hflags_aprofile(env); + + if (arm_el_is_aa64(env, 1)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } @@ -11250,14 +11257,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } } flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } pstate_for_ss = env->uncached_cpsr; } From patchwork Wed Oct 23 15:00:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177298 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp867185ill; Wed, 23 Oct 2019 08:16:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqwxDlIsh22b8hkmxm/5M+fin+1/W0a/JiU0sQIG4RD1Kaw/igoyKF5TF9xr7H64/aU7HEEL X-Received: by 2002:a17:906:5e50:: with SMTP id b16mr33179195eju.156.1571843787223; Wed, 23 Oct 2019 08:16:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571843787; cv=none; d=google.com; s=arc-20160816; b=bqF4R1A86eKILiLGZFLlKYGnGtSBiHgsmofVZ3JWczEKa0XiTUpxqQUB5brRRWeqMF FJ6W1yI2sAmrc7a9GKBaKn0E4NFlY/dnvG8/7i9tySsnclQDbcmLw+pAwQ+p2VmwiEsR hugnjH8e3CY/1bYwI0CCt9bnbZ3k/r5AKWuArYL1Xt4wKsnzPxp+58sgk/eFd/9HphLo WnM24W3Q9WVudBnjJ00Ww6+zdVM4xe/0p33w/eDNYI4SAWm4ZPjlr+n/d9UGZPju3+x4 LsVR0CjhmTiXvCvS+rk/UjwmVQoeSMqH78wz41ONYyAF/jTzO3P8EaJFV3dtyz7KAMu5 /OfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PtanC1h+OlQIbLy4htGIe38tBGV1DOrNspWjSEGlJl4=; b=mJ4n8+wHw/F/SuhWP9xiVmGjagWcq6dhPiYEtqDWdBfFssFfHekHFJcGlfxRQsVolb GivHJfc2zDe1+xdWpg1CDmIR8yajsO76sKx3+A1Ng9aJbmpEWXXMEqxCOchbrBbL+Ovf AxZgNfO0XQh9Bi/0cT3ffrm4zLXLjs6FCYZU7Sa0X0JMC+OfHEt3R+bNX/HV/zkDrffO JUdEZBBTJzD1SwzHsiIcyCGRjVMuIxEehhSBPKDPrtE9YfNZntTN+KTeEiLxpFbIN2A4 xssAGOkr6n0ZAd/ZnuFiUhdG7Zxxhh63dcMpQBPfaDjMO48KC2ug/RW6aTNKPk5eL6B8 q4Tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="gT/PMVO8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 12/24] target/arm: Add arm_rebuild_hflags Date: Wed, 23 Oct 2019 11:00:45 -0400 Message-Id: <20191023150057.25731-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::844 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function assumes nothing about the current state of the cpu, and writes the computed value to env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 30 ++++++++++++++++++++++-------- 2 files changed, 28 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9909ff89d4..d844ea21d8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3297,6 +3297,12 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); +/** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/target/arm/helper.c b/target/arm/helper.c index 89aa6fd933..85de96d071 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11198,17 +11198,35 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } +static uint32_t rebuild_hflags_internal(CPUARMState *env) +{ + int el = arm_current_el(env); + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + + if (is_a64(env)) { + return rebuild_hflags_a64(env, el, fp_el, mmu_idx); + } else if (arm_feature(env, ARM_FEATURE_M)) { + return rebuild_hflags_m32(env, fp_el, mmu_idx); + } else { + return rebuild_hflags_a32(env, fp_el, mmu_idx); + } +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + env->hflags = rebuild_hflags_internal(env); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - ARMMMUIdx mmu_idx = arm_mmu_idx(env); - int current_el = arm_current_el(env); - int fp_el = fp_exception_el(env, current_el); uint32_t flags, pstate_for_ss; + flags = rebuild_hflags_internal(env); + if (is_a64(env)) { *pc = env->pc; - flags = rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } @@ -11217,8 +11235,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, *pc = env->regs[15]; if (arm_feature(env, ARM_FEATURE_M)) { - flags = rebuild_hflags_m32(env, fp_el, mmu_idx); - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { @@ -11242,8 +11258,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); } } else { - flags = rebuild_hflags_a32(env, fp_el, mmu_idx); - /* * Note that XSCALE_CPAR shares bits with VECSTRIDE. * Note that VECLEN+VECSTRIDE are RES0 for M-profile. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 13/24] target/arm: Split out arm_mmu_idx_el Date: Wed, 23 Oct 2019 11:00:46 -0400 Message-Id: <20191023150057.25731-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::743 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Avoid calling arm_current_el() twice. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 9 +++++++++ target/arm/helper.c | 12 +++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 232d963875..f5313dd3d4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -949,6 +949,15 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); +/** + * arm_mmu_idx_el: + * @env: The cpu environment + * @el: The EL to use. + * + * Return the full ARMMMUIdx for the translation regime for EL. + */ +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); + /** * arm_mmu_idx: * @env: The cpu environment diff --git a/target/arm/helper.c b/target/arm/helper.c index 85de96d071..3f7d3f257d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11026,15 +11026,12 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) } #endif -ARMMMUIdx arm_mmu_idx(CPUARMState *env) +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { - int el; - if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } - el = arm_current_el(env); if (el < 2 && arm_is_secure_below_el3(env)) { return ARMMMUIdx_S1SE0 + el; } else { @@ -11042,6 +11039,11 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) } } +ARMMMUIdx arm_mmu_idx(CPUARMState *env) +{ + return arm_mmu_idx_el(env, arm_current_el(env)); +} + int cpu_mmu_index(CPUARMState *env, bool ifetch) { return arm_to_core_mmu_idx(arm_mmu_idx(env)); @@ -11202,7 +11204,7 @@ static uint32_t rebuild_hflags_internal(CPUARMState *env) { int el = arm_current_el(env); int fp_el = fp_exception_el(env, el); - ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); if (is_a64(env)) { return rebuild_hflags_a64(env, el, fp_el, mmu_idx); From patchwork Wed Oct 23 15:00:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177305 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp883189ill; Wed, 23 Oct 2019 08:29:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqwFwP/P1VTKpvR17u/EzDFcXqBM03aGcKRcZM2ZsYuasz4Ws0P3+HUnllcYn1Qy1UGoW7Jy X-Received: by 2002:a50:fc8b:: with SMTP id f11mr38138453edq.98.1571844540364; Wed, 23 Oct 2019 08:29:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844540; cv=none; d=google.com; s=arc-20160816; b=UBkrhXbntofsxyWISxVMaQ/+yMbhXhq+9ybZW3SX3GU3ccfccy1djfcx7F7x1OOFr1 xotJmsP4D+Dppc/A36a3OuRJMPJaFw7pTI2WE1OEysx5SxgVLHQQCO5aZn3FTVEvoCIw d5hBqk7hIledAYZ45ecRYMWDnzJAMi/ZXrICPC3AXwi7FutjsbZIfZeyKQ6o/9dEKuzg N9csRZVCBy6hVuzl0FJdcnaPS/d/5GbJjeCRflcpl2xxo3qCrBzR40ISEOJVKMaxS3Q8 2Nejnjn87/0z0eK/lFBkozXiJ91qbHoFN40CV8GO0fgo/yF+tarz/rh55XyFOCiGpiE4 3pZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bIwXZuVFcex8c2gsnRtwJL32LXPTCWgJCQzC/Gsa6O8=; b=qH0L9v+JkH6k5AyJWURQJyycHiDwvHU6oy7hD385zNveP7LZvTFr5ufDBY6RG2C1YP qx7JQSCw6NbU1XpH/3Pkb3psM7HmuSZA51s+81fgk3oeH6GjArJ882UCYPFNVybOlAV2 pYPg9/FprDEWnvfO322wC3oHFnPf2SyoCA0DEpDZHy2CVOMEerqGMIsacTTsZTs2dWFv 1B/DW+hCHZCMNoJaC0EMacd9y4duAcGJHFJlbNGvzOyMsu64wJe899YGJF6GKcBN6fZb mjasmRvp4ODcu2Ybt27WXU5tSWVZbpwN0cq5QORxvz24Z66xLjlIUqCfkMymahIgVkR1 0XeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m2C8Roib; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 14/24] target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state Date: Wed, 23 Oct 2019 11:00:47 -0400 Message-Id: <20191023150057.25731-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::841 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By performing this store early, we avoid having to save and restore the register holding the address around any function calls. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f7d3f257d..37424e3d4d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11225,6 +11225,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { uint32_t flags, pstate_for_ss; + *cs_base = 0; flags = rebuild_hflags_internal(env); if (is_a64(env)) { @@ -11298,7 +11299,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } *pflags = flags; - *cs_base = 0; } #ifdef TARGET_AARCH64 From patchwork Wed Oct 23 15:00:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177302 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp877572ill; Wed, 23 Oct 2019 08:24:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqwdKulJd8AtNkI3aS3rTqTtmcN5qKCfIh6GqrChn5pGdJ1AQw1r+zuKqKfyqO1mfxtbYnrO X-Received: by 2002:aa7:cd68:: with SMTP id ca8mr15621053edb.58.1571844258036; Wed, 23 Oct 2019 08:24:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844258; cv=none; d=google.com; s=arc-20160816; b=YAlNcmRR5HLGEExvDXSGG+zHp4sVbp9mNg7oi6aeEsOUurhkJ+xhHFlP7jUCWkWkHd NAtWEn2K5QUj7qNuMLuTeCqPhHc9byN+PfPJoooPuXWm9ccK9t/FXRDuriSSnEOzBBcE EnkrM4LB0QbTa+3SsNbRfpxj2P4HaIKPgVAhhuLyfJL9e7aHCgDAsPo8N8glypbz2poG 5ZzhOt3WjZgVBAEpfagzTzy0OVNoXlUVNmr0otJvotX/e2/MLiMwhqBbimxVIzXC+/Yx YzsKJw1G2oRWdPyveCqBmqYx9rebb6qPAeBoT1W+Jus+0qnEY2zPoQLsk1gx+1iJzrps FNsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ksJ29EsO4EC0RqRT/ptTGb/nh233vty3hFHL48/i7gI=; b=CwUVOuYoePTc4r/zY5gUMtqOm+7hgVqmAbqyZyCqQgLk2C7GGNhuoBb2OX1bTKWsk8 Wxhf/A8nBGoP5RtOiU7HK0h6pl2Pqdfumsx8pWyUMMZOFvyrGnyzDE+LYKeLLccxh5ix T6HF6Q9vhhburKJfto9aAC9eqpzaWFGE/SwBUoaeHBeZAM0xwkBocQcz2OwqOJ3StZDP Si/A86RBiiQx6MGLyrBMdlFcnSCtRT6SxgZYiEXcnyoPm5mP0lS7OIFEG0zObdbjLnr2 0Wf6X1M2EDYjebLwVJKihLDzhBA8kD8hFT4VvDnk/6bLaf3Jp52rqFSZJ5GPZjpQOS+h Qv3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ToQyPTDt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 15/24] target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32}) Date: Wed, 23 Oct 2019 11:00:48 -0400 Message-Id: <20191023150057.25731-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::844 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This functions are given the mode and el state of the cpu and writes the computed value to env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.h | 4 ++++ target/arm/helper.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+) -- 2.17.1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 1fb2cb5a77..3d4ec267a2 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -90,6 +90,10 @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32) DEF_HELPER_2(get_user_reg, i32, env, i32) DEF_HELPER_3(set_user_reg, void, env, i32, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) + DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_2(vfp_set_fpscr, void, env, i32) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37424e3d4d..b2d701cf00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11220,6 +11220,30 @@ void arm_rebuild_hflags(CPUARMState *env) env->hflags = rebuild_hflags_internal(env); } +void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) +{ + int fp_el = fp_exception_el(env, el); + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); + + env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { From patchwork Wed Oct 23 15:00:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177299 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp874680ill; Wed, 23 Oct 2019 08:22:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqyP0G+H8ORxoGcJrmXLPCaWjrXeSsBiLPBias2p8BJVPW5ow8kpbEAAJ3SSFU6RWsaB2Xnq X-Received: by 2002:a37:e01:: with SMTP id 1mr1495346qko.197.1571844126577; Wed, 23 Oct 2019 08:22:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844126; cv=none; d=google.com; s=arc-20160816; b=luJfdHv2tzsqGqncet25n3PL6ZanPUz62yRRZlN4qTMNg2DtaHIZa9mXDmBhgXfMAc RnwryYzuBj8iiW6SEWrF1x0GZQTxkPCWKh16ZiHA9qUzVaFey7guHpthFTPVPctk0VV6 y1S8n0mfo4SUswd41DL0jiH+ehrtKuR6U7sJ+Pw7Kl57G6zQB+ZsarEjS470fcNx1Y4o QJwcgaPb/w51vRNKjpTP4qrjsVJjqT0aRXYmzMO+q77xjBLIm7Y2YqbABYmAYiKQs6tE Voc2nW5KgCrPVDXj7hrBnNccojVO5SiwLJYSxbm1wt58MDQ9jls/v7vm19Z91CDUYWWd NdFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SiowrkM/1iAKWki4Ii968zkKQyJbLh4wL5XVrtx3P7c=; b=nnlHpv+J/BBokOw4qCQaQ+rXEjqhPnc5FLxUZeyr1UwB3F32yh58cW7IEOpMG49Jix 29tP/zvjci5ztesfTtR14kNbj4K1LxvRUveWTSqsBRhmGSxl6oeIVERHOpC7EqJl4AG4 uOHlM/K083LiDLOlrn8JtN4HFryaETNK2QqQcFYOLT+BDum18tVsliU+6+N2MV14lhn0 yqf+g0/5PjFIrd6t2i4RkB+NBo4s1dvw4MviGV9wqJwnigWxhjn+AVhS4eLoFmlUQGLt wTydjFw6Zt1a6dp0GmqYI/EuWlirrnOQZ3t+pTXi3NAFCCXTU4khafOsfXR4kmLuAHf+ ldtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I4xTugx1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 16/24] target/arm: Rebuild hflags at EL changes Date: Wed, 23 Oct 2019 11:00:49 -0400 Message-Id: <20191023150057.25731-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::744 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Begin setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 2 ++ target/arm/machine.c | 1 + target/arm/op_helper.c | 1 + 6 files changed, 9 insertions(+) -- 2.17.1 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index f1ab81b917..530c843303 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9984,6 +9984,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, aarch64_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); ret = vq * 16; } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 13813fb213..ab3e1a0361 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -406,6 +406,7 @@ static void arm_cpu_reset(CPUState *s) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bca80bdc38..b4cd680fc4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1025,6 +1025,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } else { env->regs[15] = new_pc & ~0x3; } + helper_rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1036,10 +1037,12 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc = new_pc; + helper_rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index b2d701cf00..aae7b62458 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7998,6 +7998,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->regs[14] = env->regs[15] + offset; } env->regs[15] = newpc; + arm_rebuild_hflags(env); } static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -8345,6 +8346,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); + helper_rebuild_hflags_a64(env, new_el); env->pc = addr; diff --git a/target/arm/machine.c b/target/arm/machine.c index 5c36707a7c..eb28b2381b 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -756,6 +756,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0fd4bd0238..ccc2cecb46 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -404,6 +404,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) * state. Do the masking now. */ env->regs[15] &= (env->thumb ? ~1 : ~3); + arm_rebuild_hflags(env); qemu_mutex_lock_iothread(); arm_call_el_change_hook(env_archcpu(env)); From patchwork Wed Oct 23 15:00:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177306 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp885464ill; Wed, 23 Oct 2019 08:30:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqwqBDbGSBlhE9SWPOiYLxEp7DUQGBifzlciAOy30Jgn1JSvy7Vso7yt9PiNLIsNo3p/rDak X-Received: by 2002:a05:6402:1511:: with SMTP id f17mr38116076edw.232.1571844635483; Wed, 23 Oct 2019 08:30:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844635; cv=none; d=google.com; s=arc-20160816; b=eiVKV5sbcCKg+yM0dzjYLMZIFPJCRkeIKtfowNHgkoMn6orI6ckwM0LX8weD2+MslN 27ViUlPLEvR4WnGDU07jVuK1PbBkhJR5GobUUQoHoJc0+7a/lColFOqU/17wh7mQ1rRA gKQRhWenW4vTNt0QyTOMei3MZeW9lw60/QNHCqOxW16gxo+D+JJQ10J5x5mM6q11tGSp +JzzFCopAcIuFzEk3fspKfiNAc43nwqkDwe8SoBoW7HXYrlo+/55Y+tecSvuYZig5EE4 o9VORMbugIQJqWoJEWBipzsM24YDezxEEuabIaMOQAauzvh/UpBqknizJKg9d128GtQ3 19uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LNnrsVkwlgJ6QoJB/sOp9/3FjmMcP/pJsCavmGVFX6A=; b=IAh4JcZNxU4Yr/tAclgcsquGvzsebD8q1UGQDc8ACbqA8PCcg+pduw+NId5V60UZQH ZisQbLJh5VghErg70PLawwZs+b+RSGesKJavFJ5LRn0dlcbH1PWbuYTNiQyUUr8Rlje5 Xc3l3o6kodOY/bGtzkNZdzLYRJGBT3YaKyHraS5rhzoPGk+F6xRoRAjs9fiX4UJNV1Cg ysA2bgLXhGLogk99s6u8eHj0FcFhfkSdRpBl+R7pXU6BfLy4iyWFsOLe6yZyVt4vg+yf x1dvIQ/0mq+LhhMMSesegAjrLQ73pWxXV93nzAwE1X1lAmPA6BgVZ7WtxR1mJIrBEDMj bnIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PI8SmEt0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 17/24] target/arm: Rebuild hflags at MSR writes Date: Wed, 23 Oct 2019 11:00:50 -0400 Message-Id: <20191023150057.25731-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::844 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 13 +++++++++++-- target/arm/translate.c | 28 +++++++++++++++++++++++----- 2 files changed, 34 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2d6cd09634..d4bebbe629 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1789,8 +1789,17 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ s->base.is_jmp = DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 96340520ee..46a0bf51c9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6890,6 +6890,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -7068,14 +7070,30 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { - /* I/O operations must end the TB here (whether read or write) */ - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { - /* We default to ending the TB on a coprocessor register write, + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && + (ri->type & ARM_CP_IO)); + + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + /* + * A write to any coprocessor regiser that ends a TB + * must rebuild the hflags for the next TB. + */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } + tcg_temp_free_i32(tcg_el); + /* + * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + need_exit_tb = true; + } + if (need_exit_tb) { gen_lookup_tb(s); } From patchwork Wed Oct 23 15:00:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177318 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp902859ill; Wed, 23 Oct 2019 08:44:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqxZM+DZMvyWZs3LdXhtx0ngY7YEVNvktmbI1wgxPizyKmQBiy8+azGoEabjvaFOQSwoufac X-Received: by 2002:ac8:70ce:: with SMTP id g14mr9614933qtp.215.1571845471566; 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 18/24] target/arm: Rebuild hflags at CPSR writes Date: Wed, 23 Oct 2019 11:00:51 -0400 Message-Id: <20191023150057.25731-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::742 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/op_helper.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ccc2cecb46..b529d6c1bf 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -224,6 +224,7 @@ uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift) void HELPER(setend)(CPUARMState *env) { env->uncached_cpsr ^= CPSR_E; + arm_rebuild_hflags(env); } /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped. @@ -387,6 +388,8 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) { cpsr_write(env, val, mask, CPSRWriteByInstr); + /* TODO: Not all cpsr bits are relevant to hflags. */ + arm_rebuild_hflags(env); } /* Write the CPSR for a 32-bit exception return */ From patchwork Wed Oct 23 15:00:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177320 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp908303ill; Wed, 23 Oct 2019 08:49:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqz4PdW5QXYgmJV08vG6aAx5oj6ZSnQ1wLiYwMFXnnG6GZplf7F4U/7l+/3UGBVmeY7fyCKg X-Received: by 2002:a37:84c3:: with SMTP id g186mr8934903qkd.398.1571845742665; Wed, 23 Oct 2019 08:49:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845742; cv=none; d=google.com; s=arc-20160816; b=gRu/wBTxpVGH0wX7BFfsFmXq2pL386OI2PfLzl5qBe5CuouamSoGMmsxS+CMMZN0Kb 8k3vw4jWGd5DbzW7I+iYjWt60+5x42+bDhpD+GGHmVm7KCQYvbwCWgeYy1Qcosm2e7Na bZQ4AeZVxF+CBMRks+YnuRjESHuY4pztQOPZordYITpZzjyESg6mNFqXevnuhtoBj5Gf iXr7YDeazjtDcBsg0LJz5SrB3lpxn++rRpvI2W/jpRDZ4zK3Efu93BSFyqyTy0SKb2mP IQkY2y0Ukx1MNqqQdf7/jFnaeqTf31H8NXjeTBnLRcvk4avxhbLUAkx94ydLSOQ1aO52 3GQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=4z2zPWedOviyKqg3qmIWn8g3R8jv2yS1u67ka41eHWc=; b=FY99pX+pwnisi8JPwtvJvcNsrqOTh0o2JbOwd7EwLdnbUDMvRJqpbINcOx9ZT+IA4a LKSu4RV8t7M2iZSJd3uKELzIiGC+jzEQd7vAYLqxXIXk+Dp+5ptvHagOAY/dQret5bWM vwqyJqkw5X8PGdDqjY2mn8neuyfytcRmC1MeJkFT4Y5yd4Es478bIOTMXv+7oGJjqwQG WI9wbrkmYBQyHrFD9iuf46hvDwYDIDUWcAkLNpDUfMrangmIYujJEejP5m4NvmZav1kh A8f6Xe1aTKr9UrC3inDcYNTpuI3qb3+gwgWEXHpGXF7uFRnWdOu4V4uhZ8tygbIqLOVp WYpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="kRI/7Vjd"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 19/24] target/arm: Rebuild hflags at Xscale SCTLR writes Date: Wed, 23 Oct 2019 11:00:52 -0400 Message-Id: <20191023150057.25731-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::744 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- target/arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index aae7b62458..c55783e540 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4174,6 +4174,16 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ tlb_flush(CPU(cpu)); + + if (ri->type & ARM_CP_SUPPRESS_TB_END) { + /* + * Normally we would always end the TB on an SCTLR write; see the + * comment in ARMCPRegInfo sctlr initialization below for why Xscale + * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild + * of hflags from the translator, so do it here. + */ + arm_rebuild_hflags(env); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Wed Oct 23 15:00:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177313 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp896654ill; Wed, 23 Oct 2019 08:39:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqxzqjg8sNjVLdEwXMjsbzVI4wBJeTa775gH9RfO15SYHoh9qfZq/kP6rGpp8DihgG9iBryh X-Received: by 2002:ac8:cc3:: with SMTP id o3mr9924941qti.239.1571845167830; Wed, 23 Oct 2019 08:39:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845167; cv=none; d=google.com; s=arc-20160816; b=xLfcR83ZphKKX3VB1g5F6T1lF6wRnopvjfqsMNyG9IKpgPOwmqHgJwaQs6w7Vhm3Zh vfIJbK6CZtE7/VQ1Fy7tTClQem1eGd3idxdW2iUidWpCfSJbhgD8dWBCwu/d18VMMpgc 4g/gmxuzR0Ro+ZgE5Bn83LIrkyNY+i4sij13IawMSBB74sidSHLdQll4Fz3e7wMT2Wfp 6BcvsmHMdd8HP+H3kqzYQWOwSGvgaWl1hz6UowAr3gEbgfP8cMcf8/RpsnRc1aJSx4vH O0mmybcne8XKv5MqIbn04nU1B9BgJ4YxAoHeTX7znfbC0zcCsrAHDOZvOfUeK1hauFux +ygQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rIJBgOSYgiSfbsgLfenw64t9SfwWSxf6NKjgwJPoM10=; b=S9okI6gRITzb/Wd0lPteTBdLgojSvOKdjxyiRUzIfpwHIzJIXibMxtyqjCyuo9psBF /zWtjRbkevYKFG6JLYBC1mfR+FJrwSytrjlUzy34XGc/Cxw99VdpD4ghAr/4OLkszRpb E/2GpFIhgwjpzkB0ABaegGV3nrRj3iEH4AUHg6rQXBMmk8VW7uALI0jaPgctx/8fgmlJ oFuNpzpBCQHVDqEN39PAEH2TiFrrLP88pJzETeJkX4uOD3PW2Aeo5KMOjZVTnb69NKBZ aeEtLUAggcjaWCs7fYQ9c0X1vRbJ3aU7VP4LM3fHmnCj1D8ScKLHxeDn+9BUX8Qzy2Ue xXtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=frskiv1c; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 20/24] target/arm: Rebuild hflags for M-profile Date: Wed, 23 Oct 2019 11:00:53 -0400 Message-Id: <20191023150057.25731-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::829 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v7: Add rebuilds for v7m_msr and nvic_writel to v7m.ccr. v8: Split nvic update to a new patch and generalize location. --- target/arm/m_helper.c | 6 ++++++ target/arm/translate.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 27cd2f3f96..f2512e448e 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -494,6 +494,7 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, dest & 1); env->thumb = 1; env->regs[15] = dest & ~1; + arm_rebuild_hflags(env); } void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) @@ -555,6 +556,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) switch_v7m_security_state(env, 0); env->thumb = 1; env->regs[15] = dest; + arm_rebuild_hflags(env); } static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, @@ -895,6 +897,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, env->regs[14] = lr; env->regs[15] = addr & 0xfffffffe; env->thumb = addr & 1; + arm_rebuild_hflags(env); } static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, @@ -1765,6 +1768,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Otherwise, we have a successful exception exit. */ arm_clear_exclusive(env); + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } @@ -1837,6 +1841,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) xpsr_write(env, 0, XPSR_IT); env->thumb = newpc & 1; env->regs[15] = newpc & ~1; + arm_rebuild_hflags(env); qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); return true; @@ -1959,6 +1964,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4; + arm_rebuild_hflags(env); return true; gen_invep: diff --git a/target/arm/translate.c b/target/arm/translate.c index 46a0bf51c9..2ea9da7637 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8327,7 +8327,7 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) { - TCGv_i32 addr, reg; + TCGv_i32 addr, reg, el; if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; @@ -8337,6 +8337,9 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) gen_helper_v7m_msr(cpu_env, addr, reg); tcg_temp_free_i32(addr); tcg_temp_free_i32(reg); + el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_m32(cpu_env, el); + tcg_temp_free_i32(el); gen_lookup_tb(s); return true; } From patchwork Wed Oct 23 15:00:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177317 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp901574ill; Wed, 23 Oct 2019 08:43:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqz36RzbsSL5SnUUPxDyXuFJ5p7+8PUF3AfHyRwjz/AbfO42uJpBqDUgdXnnxGg1oQdD22Sf X-Received: by 2002:ac8:2653:: with SMTP id v19mr9963502qtv.278.1571845402560; Wed, 23 Oct 2019 08:43:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845402; cv=none; d=google.com; s=arc-20160816; b=eM0ey40M2sNKZB9y3tpH32VP/cspKrzFqQ2icTe3mo5suG+Qzno5PjsP/cYksB2VTv L40c+QuPJ4HUmFjfsthWqeRDCXIyI0QtjJZA+Mikxwx+dlH3ISZzmFGzJ8LvA95yXyOw pV2VePSM3mjGKV6eTC/tqtNZ9HmqgtY+o9q3hVT1wRDU6DcLfdr4UhLRnBjAHGMacpQS WsR118CiUKmvdwjPCC1RJ2eqOL+SN9qBcFtImHCCXV7EZ4hoSEA73qUcMu8Vd+/Rk8pq qVKnp1TfBY/C0lAgxzxJma/DvQjCK4EcDnsxKKUKQOZ5M/MupwPbIupVZ88q8Nx9nBaN NpEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=X22okviioTNDt7zI04Hhn7/Ba9cdRHpUwnG0LrTV7qc=; b=GG5MoSSmmx1JGgdCiQnKxQOn9wNv1K9XWv/Z4Qa5CxUdLZmbYhJF8h1Xc66z5ce/Za 4jThaDn6gBbApciBetpikrh58hQ5Cn8A/WfUt75v9M7n2DU1gUJ111cqm+pPWZEMPeOA 7KlPb+lKDkMZ2wvnFsXNoedf3k174KPWPKliXZCtiNFS9pCaV9IrLSwbXojiAlAndF+t h+HK3tnq/hR+rKYKLKUWB/VgjlXTyfPwubcWjMGcXz5iFbb3fxCIQN+FUCq0uug59C4l 3Do42BuN+2iKSFANLaLuiqNg4xfuZNU9YgUbW91UbSSQ1p3Y3WnElUqUTsshRkyLWrcb b7wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W7hUYkvB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 21/24] target/arm: Rebuild hflags for M-profile NVIC Date: Wed, 23 Oct 2019 11:00:54 -0400 Message-Id: <20191023150057.25731-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::844 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 8e93e51e81..e8c74f9eba 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2251,7 +2251,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0x200 ... 0x23f: /* NVIC Set pend */ /* the special logic in armv7m_nvic_set_pending() * is not needed since IRQs are never escalated @@ -2269,9 +2269,9 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0x300 ... 0x33f: /* NVIC Active */ - return MEMTX_OK; /* R/O */ + goto exit_ok; /* R/O */ case 0x400 ... 0x5ef: /* NVIC Priority */ startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ @@ -2281,10 +2281,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, } } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { - return MEMTX_OK; + goto exit_ok; } /* fall through */ case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ @@ -2299,10 +2299,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, set_prio(s, hdlidx, sbank, newprio); } nvic_irq_update(s); - return MEMTX_OK; + goto exit_ok; case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { - return MEMTX_OK; + goto exit_ok; } /* All bits are W1C, so construct 32 bit value with 0s in * the parts not written by the access size @@ -2322,15 +2322,19 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, */ s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); } - return MEMTX_OK; + goto exit_ok; } if (size == 4) { nvic_writel(s, offset, value, attrs); - return MEMTX_OK; + goto exit_ok; } qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); /* This is UNPREDICTABLE; treat as RAZ/WI */ + + exit_ok: + /* Ensure any changes made are reflected in the cached hflags. */ + arm_rebuild_hflags(&s->cpu->env); return MEMTX_OK; } From patchwork Wed Oct 23 15:00:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177316 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp897806ill; Wed, 23 Oct 2019 08:40:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqyOaHyCfj8bbVqHkPOERLbspEkAbYu8IZejeMRMtHNj/Kxum7iyRpf+zh2RQDc6ezWPCTtm X-Received: by 2002:a0c:f7c9:: with SMTP id f9mr4519732qvo.60.1571845223878; Wed, 23 Oct 2019 08:40:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845223; cv=none; d=google.com; s=arc-20160816; b=CDSGcAb14mT2cEScU/GY2iQqVmNX4A9n3ipQYwax5b5/VYxsdbXIv1sv0u7JAtXSR+ JSqPgOJD/znt5Jn1QsqfdTfL2z0A7bIRvPVFKERBuSMGuNXn8/lzbWMIeYwEPjrWCwfq H5Y+1a90Smlynw2EGsDNDkXLv9UgoK+xzreoaJd9EYOilzzuP6+SCe9zXS/zp/EPznbQ w1oyaJElXsKQLiC2z3VaNC6evOaddlPhG0MkPF47jhCxBw4goWxFU2b73sSHuVIb1Hp5 vztA6M/uJy8f2vYMiYeY8vrTO88/RqJLoTaarDhlhThOBAoRWI6UXAWRp6mcRQAkxq0C QAoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=uBYls1SEkoMOURVj/C3yUJq0TivKPiwCZV3WGA+/blg=; b=Gv2cjcQSqJvSV8ERVtbR2IAaXpKMppzzMaoXjs1ZVhsF7uDEKQcGmCDRZMWb4RqjbK w3WnStCRFz9XADkZi2h3XVfOtkR0bw8CLMcVDrBhbtq17BU1mET/Sx5VetBWTGXs2UZK qxh/ToTJn9VwprrI6CxjFGjFvfXgzbXmubpm003hYbYyd2fnAXmZeLMqO/kTUEahm/9P WmK5muLl6Km0+A1sTblBojZhWKfjYRANEXb1dngON6UQ4X1PGpHp4UzB49fLDMYbp3C7 gw8tks97ZPxQ0ZGvpTbldcPbH6WVT0fg5AYWDWqu1wvMdB79SEQlX82rFtLvM7iGOk4Z skeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jX7BbMZt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 22/24] linux-user/aarch64: Rebuild hflags for TARGET_WORDS_BIGENDIAN Date: Wed, 23 Oct 2019 11:00:55 -0400 Message-Id: <20191023150057.25731-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::743 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 1295fa8531..31c845a70d 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -173,6 +173,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) for (i = 1; i < 4; ++i) { env->cp15.sctlr_el[i] |= SCTLR_EE; } + arm_rebuild_hflags(env); #endif if (cpu_isar_feature(aa64_pauth, cpu)) { From patchwork Wed Oct 23 15:00:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177303 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp882097ill; Wed, 23 Oct 2019 08:28:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqzt0vPZnQvM6v1AX8WOSRcAp2xl524RE64seT1wiwYSVM/EM7j1c7fIW5Pb17cQbW9OlhSN X-Received: by 2002:a50:eb42:: with SMTP id z2mr37876862edp.291.1571844482301; Wed, 23 Oct 2019 08:28:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571844482; cv=none; d=google.com; s=arc-20160816; b=OEK+C4FD9Kle4HcIoVSzTKM8BLJorCYi5VS4hwelZJzdrF6gZJkhS07wmIuQ5xZ/j6 sS2is9RLrScNZHJHM6IQwcr1VSV7/tZmp6u6TJ/Sm2Tq3SFN4FuBh6aLCzNs7gkEqUb6 RxV/fSDUorMuN1DT6oq1acVaCI4+xymqOcicye3VdJCcKGFi/kFZtytqZhAjL+HtRgm+ V9jtGq02iRLdbhcxlQGB3orCjz6H84FCz3M/8PMcU86W3pXmuygaBSHUkMQIkCsXG66K XdhX+g40QTX3I9h0NhcHKmZw2Nyqcf3JfIvznU3BfecK57G7t8hfKT8dWcseyx4O5JvZ C91Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=EixSCP/+s4Pul7ok7q0wZeyo8cfwDyotG9VjfWeZAIo=; b=g+egy4rpiH5qpJ2mIIDpbT2FOyzpns6vqVlfnDeXB6exU50gJwv/vOLTtRUw5X1+9X 5ea9yNedyACOB1bXh/0CtJ3DU9ui7g2EivpLcNd4HTA+ioGNXYzIo9crNAwDiBWSlHU3 wYqQwdqArRpYldkFEcpthLNeakVID7kJW0jVxc+1goWo5ObFiMlptNlCDkRJk9jSGdKf fEzRaplFvYAhg6fzAvAdP/OevCbklp7Y26ISO7U95iHxtSlpg7qBVaTSTSM54hjSzrYr N1TCpXFSFhQbmobJ7J6d6mIzaPgVOiRCyRkmI78sY7zSqClUSbLGk2ExfHuXgUZfsVPt Xwrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GlbSIzeR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 23/24] linux-user/arm: Rebuild hflags for TARGET_WORDS_BIGENDIAN Date: Wed, 23 Oct 2019 11:00:56 -0400 Message-Id: <20191023150057.25731-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::743 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Continue setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index e28c45cd4a..7be4071751 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -440,6 +440,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) } else { env->cp15.sctlr_el[1] |= SCTLR_B; } + arm_rebuild_hflags(env); #endif ts->stack_base = info->start_stack; From patchwork Wed Oct 23 15:00:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 177314 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp896712ill; Wed, 23 Oct 2019 08:39:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwZyAzTVewOcUemdLRD4odl8qtyvXsjo70G1rZVIw6nRhsIm80j7+tgMAtoUMVJusrMGwlR X-Received: by 2002:a0c:fc10:: with SMTP id z16mr5650806qvo.2.1571845171230; Wed, 23 Oct 2019 08:39:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571845171; cv=none; d=google.com; s=arc-20160816; b=kJY9m0VLh7DJcbMIBM0vb2kVnckl0whU5R4WnzR8kwdYIeMJmoPsJwXM74X+QvXT88 IIeoMSKrwjFXUrvbyN8hzgHY7tAaej/Uiq0+cFZsuAJ1SWdI/6EAaoYhaTlSw9KiD5XA YXOzV0dZ1G6XR2R4oh2AJZaPxVepKevKU3lXsj7aznxTHW2ejcldp2NJKOepofWT41v5 gPADUbE0RMkxZXKyw4NIPNBKj+pQI7LSGsYDL7dIlICd56erH6dQWVBJTI7W2AFYEpRm YaKCQhX5JKQUF14OiI5i+JX9i5Avg4tkyKglhUzKRVfZqm64bwp0zGooX3q4mQYr2kJw p8Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xYzA79nlkAAXT+tYBTRBvIlOCILLFnnuEHFTBSl+bu8=; b=et0bTJ4djt8JX35/n5zE+UOcRoUrN9pmww3HEhyTnPbMfXMfMovNQSr1Q+TigD9iGb EKdaMCfdPsxvBll5YUN7ZCGyhcOIybHa+rvNCHhrPTK8mJzZz6rMxn5TgtL1rDwaFVvh Z7NFjGuvNIs4Y8U0P/N+/ZEHmFa33X5YUbB2tAEi8eIUC5p3wH5UcQU2pTNT9M0Gz+c/ J0kvhe+R0BfsFpbBW3mgm3Qf2QEJb0rrl7Xx9RSceSGElBUx+bb6Clw2Xh3tRDIpJWBw Mdn/B8ssF1pDg6L7Io5yB1+PB7ynjZM/P61LtwCwhRu9OYLJQ0K4VLoXjN6W274ogybZ rMLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZivIxCUw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[64.20.4.198]) by smtp.gmail.com with ESMTPSA id l189sm11030168qke.69.2019.10.23.08.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2019 08:01:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v9 24/24] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state Date: Wed, 23 Oct 2019 11:00:57 -0400 Message-Id: <20191023150057.25731-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023150057.25731-1-richard.henderson@linaro.org> References: <20191023150057.25731-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::742 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the payoff. >From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both 0.55% fp_exception_el - 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state - 6.96% cpu_get_tb_cpu_state 3.63% aa64_va_parameters_both 0.60% fp_exception_el 0.53% sve_exception_el AFTER: - 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr - 13.03% helper_lookup_tb_ptr + 11.19% tb_htable_lookup 0.55% cpu_get_tb_cpu_state 0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state 0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64 Before, helper_lookup_tb_ptr is the second hottest function in the application, consuming almost a quarter of the runtime. Within the entire execution, cpu_get_tb_cpu_state consumes about 12%. After, helper_lookup_tb_ptr has dropped to the fourth hottest function, with consumption dropping to a sixth of the runtime. Within the entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the supporting function to rebuild hflags also consumes about 1%. Assertions are retained for --enable-debug-tcg. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v2: Retain asserts for future debugging. --- target/arm/helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index c55783e540..63815fc4cf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11259,12 +11259,15 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - uint32_t flags, pstate_for_ss; + uint32_t flags = env->hflags; + uint32_t pstate_for_ss; *cs_base = 0; - flags = rebuild_hflags_internal(env); +#ifdef CONFIG_DEBUG_TCG + assert(flags == rebuild_hflags_internal(env)); +#endif - if (is_a64(env)) { + if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { *pc = env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);