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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57c8492fb96sm3503740a12.11.2024.06.11.09.08.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 09:08:00 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Tue, 11 Jun 2024 17:07:59 +0100 Subject: [PATCH] arm64: dts: exynos: gs101: reorder properties as per guidelines Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240611-gs101-dts-cleanup-v1-1-877358cd6536@linaro.org> X-B4-Tracking: v=1; b=H4sIAF52aGYC/x2MQQqAIBAAvxJ7TlDJpL4SHUS3WggTtyII/550G ZjDzAuMmZBhbF7IeBPTEauotgG/ubiioFAdtNSdNFKJlVVlOFn4HV28kpDaLn2waui9gdqljAs 9/3OaS/kABH6ev2MAAAA= To: Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr?= =?utf-8?q?=C3=A9_Draszik?= X-Mailer: b4 0.13.0 * 'interrupts' & 'cpus' & 'clocks' are standard/common properties as per the Devicetree Sources (DTS) Coding Style and therefore should be sorted alphabetically within the standard/common section * vendor properties should be last * reg / ranges should be 2nd/3rd (after compatible) * status should be last Do so. Note: I've left the cpus{} node untouched to keep the grouping of relatedd properties. Signed-off-by: AndrĂ© Draszik --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 2 +- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 12 deletions(-) --- base-commit: d35b2284e966c0bef3e2182a5c5ea02177dd32e4 change-id: 20240501-gs101-dts-cleanup-027f6d7196c5 Best regards, diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 5e8ffe065081..b10bde2ec716 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -131,9 +131,9 @@ &ufs_0_phy { }; &usbdrd31 { - status = "okay"; vdd10-supply = <®_placeholder>; vdd33-supply = <®_placeholder>; + status = "okay"; }; &usbdrd31_dwc3 { diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index a66e996666b8..eadb8822e6d4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -213,9 +213,9 @@ pmu-2 { pmu-3 { compatible = "arm,dsu-pmu"; - interrupts = ; cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + interrupts = ; }; psci { @@ -288,6 +288,8 @@ timer@10050000 { compatible = "google,gs101-mct", "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; + clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; + clock-names = "fin_pll", "mct"; interrupts = , , , @@ -300,17 +302,15 @@ timer@10050000 { , , ; - clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; - clock-names = "fin_pll", "mct"; }; watchdog_cl0: watchdog@10060000 { compatible = "google,gs101-wdt"; reg = <0x10060000 0x100>; - interrupts = ; clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, <&ext_24_5m>; clock-names = "watchdog", "watchdog_src"; + interrupts = ; samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <0>; status = "disabled"; @@ -319,10 +319,10 @@ watchdog_cl0: watchdog@10060000 { watchdog_cl1: watchdog@10070000 { compatible = "google,gs101-wdt"; reg = <0x10070000 0x100>; - interrupts = ; clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, <&ext_24_5m>; clock-names = "watchdog", "watchdog_src"; + interrupts = ; samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <1>; status = "disabled"; @@ -776,12 +776,12 @@ hsi2c_8: i2c@10970000 { compatible = "google,gs101-hsi2c", "samsung,exynosautov9-hsi2c"; reg = <0x10970000 0xc0>; - interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; pinctrl-0 = <&hsi2c8_bus>; pinctrl-names = "default"; status = "disabled"; @@ -831,10 +831,10 @@ usi_uart: usi@10a000c0 { serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - interrupts = ; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; + interrupts = ; pinctrl-0 = <&uart0_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <256>; @@ -1157,12 +1157,12 @@ hsi2c_12: i2c@10d50000 { compatible = "google,gs101-hsi2c", "samsung,exynosautov9-hsi2c"; reg = <0x10d50000 0xc0>; - interrupts = ; #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; pinctrl-0 = <&hsi2c12_bus>; pinctrl-names = "default"; status = "disabled"; @@ -1277,13 +1277,14 @@ usbdrd31_phy: phy@11100000 { <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; - samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; + samsung,pmu-syscon = <&pmu_system_controller>; status = "disabled"; }; usbdrd31: usb@11110000 { compatible = "google,gs101-dwusb3"; + ranges = <0x0 0x11110000 0x10000>; clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, @@ -1291,14 +1292,13 @@ usbdrd31: usb@11110000 { clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x11110000 0x10000>; status = "disabled"; usbdrd31_dwc3: usb@0 { compatible = "snps,dwc3"; + reg = <0x0 0x10000>; clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; clock-names = "ref"; - reg = <0x0 0x10000>; interrupts = ; phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; phy-names = "usb2-phy", "usb3-phy";