From patchwork Thu Jun 15 03:03:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105610 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595281qgd; Wed, 14 Jun 2017 20:05:29 -0700 (PDT) X-Received: by 10.98.3.132 with SMTP id 126mr3047262pfd.133.1497495929283; Wed, 14 Jun 2017 20:05:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497495929; cv=none; d=google.com; s=arc-20160816; b=NNmU1UJmIlg2PQRi7vrOTFM7+gRrpVyqQX04guixzUmj7Wmrlx9ytfGUn2bi5/6qfd EkBlGEwTaemPs3iDaNpzStUC4dJrM2PWoyVNWDbT3dH49LqOsxlyofAdgZNoFNQWqMvE NTMVIBGikIh4kVa5w93lBOu1vgIOd8wUj+eQ/gAf6MOS++OHslaSZCxxUNFyywmusv9a 1MNkE/HhX6xTHhqXE2KDOprsl4hKZq75WqX0CR5d3J9MTRa/Eg65657G+wC5DrGe19Rv ljvoKRdXMqlhgLW48a78dsneTGlbjhAbyxMgGkDNE4opkfEt6rt42g7r0s1LMV2rRBsk x46w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=xmMM2WJG38NPfhr/SWKW/L8WVq/lGxJnRa8pzOOVc78=; b=yzJBYHHauTGLdhaKne7IYpoFryqcQFjvMXUqw0n7O1priRNbU+DiVt0YCIIMeo9VgD WFS/iMwZEpa/iGBmbVFw/LpTK3A0dnlsUj2aE5vNOZCmhFX7NQW3pqS2KKWQj3/bI7C3 F4KTk4zzg0guHUqPZ9s3F8bdzikVhiIpPt3mIUGLVPJvf82A7oIE2C2pBm5a/DBeBxSX 3QOdwEeDExB9m+8Te4O04r+zE2zF79GzLEsswUzPEirSA1202ELgu5QlD1UkotD++kgT zWTrl6V8VScerb/dQ2EuwoLa1k60VoctQ+XtfLxYCtEXukUcwKdr9F9j9IbEF1/R7FjJ ImXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=CsQrGwrG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z8si1303997pgs.455.2017.06.14.20.05.28; Wed, 14 Jun 2017 20:05:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=CsQrGwrG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752371AbdFODFL (ORCPT + 25 others); Wed, 14 Jun 2017 23:05:11 -0400 Received: from mail-pg0-f48.google.com ([74.125.83.48]:34892 "EHLO mail-pg0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752051AbdFODFK (ORCPT ); Wed, 14 Jun 2017 23:05:10 -0400 Received: by mail-pg0-f48.google.com with SMTP id k71so1245149pgd.2 for ; Wed, 14 Jun 2017 20:05:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xmMM2WJG38NPfhr/SWKW/L8WVq/lGxJnRa8pzOOVc78=; b=CsQrGwrG9ouipKxZQ5v7C9o4uzZz8jJW5M1Rj1dkzIgG420vz8Yw6TEaXCpKEF9eSl 0MtWmgwO7U8REj9DCzqX4URoLNwJJEjKdY5PCs8cfSyrwvPhNTI8cpZQLO2COQZ6aJhG wWIZwlu9UEAVAd6MOnUgFQHAZedSaad2Ljuyw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xmMM2WJG38NPfhr/SWKW/L8WVq/lGxJnRa8pzOOVc78=; b=WxBgzpcNccG33Hy6wwuiTGUo1xIwdy15nPUd/YUzGHutaW05re8LP90ivtEQg/fIVQ wC/HYBGyyGOn883qD9OBhxnywKhbivh2/520YEpdmMjKfJxrAZUOSFmZsg5PLba3Cuy2 Sq/Lcspx8AvJ/CHuxqjWOTrMgqa8NTBxVAbgR3lh2mxgrpH76JRcREQOB7O7Q1zJf5nC J1i/2BtwRYIUdupmkzFiijcY4JSl83z2EJlsuN0KgBhidGgBX5vQl5JfpmjTU2B2+CiE AI2VPNkNgmRModgh/a/9S2MAMO6NVMmpSZ07L3qHBEYrWvt+/tr1S5ODIosUZ86hwEdU 1nkA== X-Gm-Message-State: AKS2vOwQTp4WlYK/lQwcr6ZVdseTPjC27n7TPmXcJzUXyZAQAMZS9+XO G+W9PAQBxbTGP6Jj X-Received: by 10.84.172.1 with SMTP id m1mr3637805plb.134.1497495909514; Wed, 14 Jun 2017 20:05:09 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.05.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:05:08 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Guodong Xu Subject: [PATCH v4 01/20] dt-bindings: arm: hisilicon: add bindings for HiKey960 board Date: Thu, 15 Jun 2017 11:03:58 +0800 Message-Id: <20170615030417.14059-2-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for HiKey960 Board. Signed-off-by: Guodong Xu Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.10.2 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 2e73215..7111fbc8 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -4,6 +4,10 @@ Hi3660 SoC Required root node properties: - compatible = "hisilicon,hi3660"; +HiKey960 Board +Required root node properties: + - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; + Hi3798cv200 SoC Required root node properties: - compatible = "hisilicon,hi3798cv200"; From patchwork Thu Jun 15 03:04:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105612 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595400qgd; Wed, 14 Jun 2017 20:05:53 -0700 (PDT) X-Received: by 10.84.231.134 with SMTP id g6mr3641464plk.86.1497495952919; Wed, 14 Jun 2017 20:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497495952; cv=none; d=google.com; s=arc-20160816; b=sljfzK/T9FDDMhmEXEUGOhSvuj+xa/5EsT41I1a7m6DHIFgON90wvli0tfPTzmqzuF SykpvOjWaqDK62nwPOF1JQwsKxamgLnLinkwD8cV1uSIkRagkt3d9+5tR6A0GrWsv61j QYEvnD+riPrKbt/PEdJtdvhaaHDVBV21pIDkU/ISYzvb3EVIrCkoANdJ9UJL0pXOEMdw u20nP6zxW/zg45JKfnFhDQV3jV9ez3tvWoc5Lgtu400LBGMrGvVQP4f+NaM3Golw3Dt0 0FYQKBTHTHoI3pib8BHKyV6NAv6srsNX1XSKS5Rir1cmjityffWSrsfNoH/HpSwussDi NCIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=k2rEOj59VAxOOTppfiW15cc433btNtSPCWjUihdJ1nk=; b=xevsnAQd65L+i3ZGSwI0fkxwJ2APUszY9dKuKiLuntJFOfxd0/fZamXn9trF76wAYn BLWbB/hvK2v/g3jS5ugLZR4dhck8YgFEX1CIeOC6ctwrwT60vz8hXoEggsjGhlo2X48x 5WJrlzT2lcTsttAzyeLyucQdLnLT1qDOC7d71mMc7Y69mP1IzK+wvWnfCoqJ4C48mWTp PIjCQ+vuF2BdU18CNFQHdPcKTIHROej1D/Mkgb9FoTg+/Hu+JsaE9xKEAJEODsMhNPIL ZDEgHYcQDWfGIMduQovEZHc0Nq8wLPVFd32gMSYU/yuMzkqlNZM+SGd9+2qHP973NzJv pyuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=bJZ/HyNW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Wang Xiaoyin Signed-off-by: Chen Jun Signed-off-by: Guodong Xu Acked-by: Rob Herring --- .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 778 +++++++++++++++++++-- 1 file changed, 715 insertions(+), 63 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi index 719c4bc..7e542d2 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi @@ -24,6 +24,27 @@ &range 0 7 0 &range 8 116 0>; + pmu_pmx_func: pmu_pmx_func { + pinctrl-single,pins = < + 0x008 MUX_M1 /* PMU1_SSI */ + 0x00c MUX_M1 /* PMU2_SSI */ + 0x010 MUX_M1 /* PMU_CLKOUT */ + 0x100 MUX_M1 /* PMU_HKADC_SSI */ + >; + }; + + csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M0 /* CSI0_PWD_N */ + >; + }; + + csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x04c MUX_M0 /* CSI1_PWD_N */ + >; + }; + isp0_pmx_func: isp0_pmx_func { pinctrl-single,pins = < 0x058 MUX_M1 /* ISP_CLK0 */ @@ -40,6 +61,12 @@ >; }; + pwr_key_pmx_func: pwr_key_pmx_func { + pinctrl-single,pins = < + 0x080 MUX_M0 /* GPIO_034 */ + >; + }; + i2c3_pmx_func: i2c3_pmx_func { pinctrl-single,pins = < 0x02c MUX_M1 /* I2C3_SCL */ @@ -67,21 +94,10 @@ >; }; - spi1_pmx_func: spi1_pmx_func { - pinctrl-single,pins = < - 0x034 MUX_M1 /* SPI1_CLK */ - 0x038 MUX_M1 /* SPI1_DI */ - 0x03c MUX_M1 /* SPI1_DO */ - 0x040 MUX_M1 /* SPI1_CS_N */ - >; - }; - uart0_pmx_func: uart0_pmx_func { pinctrl-single,pins = < 0x0cc MUX_M2 /* UART0_RXD */ 0x0d0 MUX_M2 /* UART0_TXD */ - 0x0d4 MUX_M2 /* UART0_RXD_M */ - 0x0d8 MUX_M2 /* UART0_TXD_M */ >; }; @@ -138,6 +154,18 @@ 0x0d8 MUX_M1 /* UART6_TXD */ >; }; + + cam0_rst_pmx_func: cam0_rst_pmx_func { + pinctrl-single,pins = < + 0x0c8 MUX_M0 /* CAM0_RST */ + >; + }; + + cam1_rst_pmx_func: cam1_rst_pmx_func { + pinctrl-single,pins = < + 0x124 MUX_M0 /* CAM1_RST */ + >; + }; }; /* [IOMG_MMC0_000, IOMG_MMC0_005] */ @@ -174,6 +202,13 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; + ufs_pmx_func: ufs_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* UFS_REF_CLK */ + 0x004 MUX_M1 /* UFS_RST_N */ + >; + }; + spi3_pmx_func: spi3_pmx_func { pinctrl-single,pins = < 0x008 MUX_M1 /* SPI3_CLK */ @@ -248,17 +283,17 @@ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c7_pmx_func: i2c7_pmx_func { pinctrl-single,pins = < - 0x024 MUX_M1 /* I2C2_SCL */ - 0x028 MUX_M1 /* I2C2_SDA */ + 0x024 MUX_M3 /* I2C7_SCL */ + 0x028 MUX_M3 /* I2C7_SDA */ >; }; - i2c7_pmx_func: i2c7_pmx_func { + pcie_pmx_func: pcie_pmx_func { pinctrl-single,pins = < - 0x024 MUX_M3 /* I2C7_SCL */ - 0x028 MUX_M3 /* I2C7_SDA */ + 0x084 MUX_M1 /* PCIE_CLKREQ_N */ + 0x088 MUX_M1 /* PCIE_WAKE_N */ >; }; @@ -271,15 +306,6 @@ >; }; - spi4_pmx_func: spi4_pmx_func { - pinctrl-single,pins = < - 0x08c MUX_M4 /* SPI4_CLK */ - 0x090 MUX_M4 /* SPI4_DI */ - 0x094 MUX_M4 /* SPI4_DO */ - 0x098 MUX_M4 /* SPI4_CS0_N */ - >; - }; - i2s0_pmx_func: i2s0_pmx_func { pinctrl-single,pins = < 0x034 MUX_M1 /* I2S0_DI */ @@ -290,17 +316,18 @@ }; }; - pmx5: pinmux@ff3fd800 { + pmx5: pinmux@e896c800 { compatible = "pinconf-single"; - reg = <0x0 0xff3fd800 0x0 0x18>; + reg = <0x0 0xe896c800 0x0 0x200>; #pinctrl-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; + pinctrl-single,register-width = <0x20>; - sdio_clk_cfg_func: sdio_clk_cfg_func { + pmu_cfg_func: pmu_cfg_func { pinctrl-single,pins = < - 0x000 0x0 /* SDIO_CLK */ + 0x010 0x0 /* PMU1_SSI */ + 0x014 0x0 /* PMU2_SSI */ + 0x018 0x0 /* PMU_CLKOUT */ + 0x10c 0x0 /* PMU_HKADC_SSI */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -315,18 +342,35 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK + DRIVE7_06MA DRIVE6_MASK >; }; - sdio_cfg_func: sdio_cfg_func { + i2c3_cfg_func: i2c3_cfg_func { pinctrl-single,pins = < - 0x004 0x0 /* SDIO_CMD */ - 0x008 0x0 /* SDIO_DATA0 */ - 0x00c 0x0 /* SDIO_DATA1 */ - 0x010 0x0 /* SDIO_DATA2 */ - 0x014 0x0 /* SDIO_DATA3 */ + 0x038 0x0 /* I2C3_SCL */ + 0x03c 0x0 /* I2C3_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* CSI0_PWD_N */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -335,29 +379,64 @@ PULL_DOWN >; pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x058 0x0 /* CSI1_PWD_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK + DRIVE7_04MA DRIVE6_MASK >; }; - }; - pmx6: pinmux@ff37e800 { - compatible = "pinconf-single"; - reg = <0x0 0xff37e800 0x0 0x18>; - #pinctrl-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; + isp0_cfg_func: isp0_cfg_func { + pinctrl-single,pins = < + 0x064 0x0 /* ISP_CLK0 */ + 0x070 0x0 /* ISP_SCL0 */ + 0x074 0x0 /* ISP_SDA0 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK>; + }; - sd_clk_cfg_func: sd_clk_cfg_func { + isp1_cfg_func: isp1_cfg_func { pinctrl-single,pins = < - 0x000 0x0 /* SD_CLK */ + 0x068 0x0 /* ISP_CLK1 */ + 0x078 0x0 /* ISP_SCL1 */ + 0x07c 0x0 /* ISP_SDA1 */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -372,18 +451,37 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK + DRIVE7_04MA DRIVE6_MASK >; }; - sd_cfg_func: sd_cfg_func { + pwr_key_cfg_func: pwr_key_cfg_func { pinctrl-single,pins = < - 0x004 0x0 /* SD_CMD */ - 0x008 0x0 /* SD_DATA0 */ - 0x00c 0x0 /* SD_DATA1 */ - 0x010 0x0 /* SD_DATA2 */ - 0x014 0x0 /* SD_DATA3 */ + 0x08c 0x0 /* GPIO_034 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart1_cfg_func: uart1_cfg_func { + pinctrl-single,pins = < + 0x0b4 0x0 /* UART1_RXD */ + 0x0b8 0x0 /* UART1_TXD */ + 0x0bc 0x0 /* UART1_CTS_N */ + 0x0c0 0x0 /* UART1_RTS_N */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -392,14 +490,568 @@ PULL_DOWN >; pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART2_CTS_N */ + 0x0cc 0x0 /* UART2_RTS_N */ + 0x0d0 0x0 /* UART2_TXD */ + 0x0d4 0x0 /* UART2_RXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART5_RXD */ + 0x0cc 0x0 /* UART5_TXD */ + 0x0d0 0x0 /* UART5_CTS_N */ + 0x0d4 0x0 /* UART5_RTS_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam0_rst_cfg_func: cam0_rst_cfg_func { + pinctrl-single,pins = < + 0x0d4 0x0 /* CAM0_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart0_cfg_func: uart0_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART0_RXD */ + 0x0dc 0x0 /* UART0_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart6_cfg_func: uart6_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART6_CTS_N */ + 0x0dc 0x0 /* UART6_RTS_N */ + 0x0e0 0x0 /* UART6_RXD */ + 0x0e4 0x0 /* UART6_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x0e8 0x0 /* UART3_CTS_N */ + 0x0ec 0x0 /* UART3_RTS_N */ + 0x0f0 0x0 /* UART3_RXD */ + 0x0f4 0x0 /* UART3_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x0f8 0x0 /* UART4_CTS_N */ + 0x0fc 0x0 /* UART4_RTS_N */ + 0x100 0x0 /* UART4_RXD */ + 0x104 0x0 /* UART4_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam1_rst_cfg_func: cam1_rst_cfg_func { + pinctrl-single,pins = < + 0x130 0x0 /* CAM1_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + }; + + pmx6: pinmux@ff3b6800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3b6800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + ufs_cfg_func: ufs_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* UFS_REF_CLK */ + 0x004 0x0 /* UFS_RST_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_08MA DRIVE6_MASK + >; + }; + + spi3_cfg_func: spi3_cfg_func { + pinctrl-single,pins = < + 0x008 0x0 /* SPI3_CLK */ + 0x0 /* SPI3_DI */ + 0x010 0x0 /* SPI3_DO */ + 0x014 0x0 /* SPI3_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + }; + + pmx7: pinmux@ff3fd800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3fd800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SDIO_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA DRIVE6_MASK + >; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SDIO_CMD */ + 0x008 0x0 /* SDIO_DATA0 */ + 0x00c 0x0 /* SDIO_DATA1 */ + 0x010 0x0 /* SDIO_DATA2 */ + 0x014 0x0 /* SDIO_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA DRIVE6_MASK + >; + }; + }; + + pmx8: pinmux@ff37e800 { + compatible = "pinconf-single"; + reg = <0x0 0xff37e800 0x0 0x18>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SD_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA + DRIVE6_MASK + >; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SD_CMD */ + 0x008 0x0 /* SD_DATA0 */ + 0x00c 0x0 /* SD_DATA1 */ + 0x010 0x0 /* SD_DATA2 */ + 0x014 0x0 /* SD_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA + DRIVE6_MASK + >; + }; + }; + + pmx9: pinmux@fff11800 { + compatible = "pinconf-single"; + reg = <0x0 0xfff11800 0x0 0xbc>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <0x20>; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x01c 0x0 /* I2C0_SCL */ + 0x020 0x0 /* I2C0_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x024 0x0 /* I2C1_SCL */ + 0x028 0x0 /* I2C1_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c7_cfg_func: i2c7_cfg_func { + pinctrl-single,pins = < + 0x02c 0x0 /* I2C7_SCL */ + 0x030 0x0 /* I2C7_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + slimbus_cfg_func: slimbus_cfg_func { + pinctrl-single,pins = < + 0x034 0x0 /* SLIMBUS_CLK */ + 0x038 0x0 /* SLIMBUS_DATA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s0_cfg_func: i2s0_cfg_func { + pinctrl-single,pins = < + 0x040 0x0 /* I2S0_DI */ + 0x044 0x0 /* I2S0_DO */ + 0x048 0x0 /* I2S0_XCLK */ + 0x04c 0x0 /* I2S0_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s2_cfg_func: i2s2_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* I2S2_DI */ + 0x054 0x0 /* I2S2_DO */ + 0x058 0x0 /* I2S2_XCLK */ + 0x05c 0x0 /* I2S2_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + pcie_cfg_func: pcie_cfg_func { + pinctrl-single,pins = < + 0x094 0x0 /* PCIE_CLKREQ_N */ + 0x098 0x0 /* PCIE_WAKE_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + spi2_cfg_func: spi2_cfg_func { + pinctrl-single,pins = < + 0x09c 0x0 /* SPI2_CLK */ + 0x0a0 0x0 /* SPI2_DI */ + 0x0a4 0x0 /* SPI2_DO */ + 0x0a8 0x0 /* SPI2_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + usb_cfg_func: usb_cfg_func { + pinctrl-single,pins = < + 0x0ac 0x0 /* GPIO_219 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK >; }; }; From patchwork Thu Jun 15 03:04:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105613 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595401qgd; Wed, 14 Jun 2017 20:05:53 -0700 (PDT) X-Received: by 10.84.232.198 with SMTP id x6mr3690927plm.245.1497495953298; Wed, 14 Jun 2017 20:05:53 -0700 (PDT) ARC-Seal: i=1; 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Wed, 14 Jun 2017 20:05:34 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.05.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:05:33 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Zhangfei Gao Subject: [PATCH v4 04/20] arm64: dts: hi3660: add resources for clock and reset Date: Thu, 15 Jun 2017 11:04:01 +0800 Message-Id: <20170615030417.14059-5-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhangfei Gao Add some resource nodes for clock and reset Signed-off-by: Zhangfei Gao Acked-by: Rob Herring --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 7 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3983086..f55710a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { compatible = "hisilicon,hi3660"; @@ -141,18 +142,56 @@ #size-cells = <2>; ranges; - fixed_uart5: fixed_19_2M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "fixed:uart5"; + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; }; - uart5: uart@fdf05000 { + crg_rst: crg_rst_controller { + compatible = "hisilicon,hi3660-reset"; + #reset-cells = <2>; + hisi,rst-syscon = <&crg_ctrl>; + }; + + + pctrl: pctrl@e8a09000 { + compatible = "hisilicon,hi3660-pctrl", "syscon"; + reg = <0x0 0xe8a09000 0x0 0x2000>; + #clock-cells = <1>; + }; + + pmuctrl: crg_ctrl@fff34000 { + compatible = "hisilicon,hi3660-pmuctrl", "syscon"; + reg = <0x0 0xfff34000 0x0 0x1000>; + #clock-cells = <1>; + }; + + sctrl: sctrl@fff0a000 { + compatible = "hisilicon,hi3660-sctrl", "syscon"; + reg = <0x0 0xfff0a000 0x0 0x1000>; + #clock-cells = <1>; + }; + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + #clock-cells = <1>; + + }; + + iomcu_rst: reset { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = ; - clocks = <&fixed_uart5 &fixed_uart5>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, + <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; From patchwork Thu Jun 15 03:04:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105614 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595406qgd; Wed, 14 Jun 2017 20:05:54 -0700 (PDT) X-Received: by 10.84.238.137 with SMTP id v9mr3750009plk.154.1497495954096; Wed, 14 Jun 2017 20:05:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497495954; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id e6si1293791plk.0.2017.06.14.20.05.53; Wed, 14 Jun 2017 20:05:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=OBDlTtAh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752583AbdFODFr (ORCPT + 25 others); Wed, 14 Jun 2017 23:05:47 -0400 Received: from mail-pf0-f180.google.com ([209.85.192.180]:34835 "EHLO mail-pf0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752105AbdFODFn (ORCPT ); Wed, 14 Jun 2017 23:05:43 -0400 Received: by mail-pf0-f180.google.com with SMTP id l89so1381740pfi.2 for ; Wed, 14 Jun 2017 20:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jXFtgFIjDk5tb4iZZTJ1ZCyrIT65KjYJF6ztgq0q2pk=; b=OBDlTtAhecZ0a5FXuychFJNRYaevdrILueB3jIq6WoHdgawa+OenYBD1FV0ynJjLUn Eavs2DAdjx9VqrPTNF4BjRaMAsF2DOAirT6eYv4YUcXs04Qfk58f/Thy2tzxgznEwMYN bptHauuxdpW/QfgXVxj5fR8Y5p23xLkgfZdVc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jXFtgFIjDk5tb4iZZTJ1ZCyrIT65KjYJF6ztgq0q2pk=; b=B2df7qlcMENggYgBy0q6rJA1QWD5q6XfyqinKxMvsnfnKH/pToWrgrZK1fzV1ioB5Y RVZL0h4/gZmyfXCuT9Anx9xMph8wGBTkTVtePWe/C42SUcx/c+frbUIlVPl2eXvbD7xt zUGuQNYDSL8yL2o9e6WUocDIKR8ef3TwoJBRcmIizfv42AOU9k9UFP1bsIaQK3Di7cYn k0CYtf/xHCtHSRgpx2+Z4sW6WOb41ZvQXSBb3XzSwYGUTAsLG52mGX6DfQq5lPUhWfE4 FfD+x02Eb7IAk+8jMwU/+aGTviEpz/8UFOBVk2rCOXvWWsS9UwS2KrurhugXykSc/UMb 3+Ew== X-Gm-Message-State: AKS2vOwlhWZO0D5kVFHJDcBk1T8rrtBxSFAQzsuyCT0Y1LgOVj1Lg0Ft ePiTIfs+Yv93YTqR X-Received: by 10.84.172.1 with SMTP id m1mr3640189plb.134.1497495942737; Wed, 14 Jun 2017 20:05:42 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.05.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:05:42 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Zhangfei Gao , Jarkko Nikula , Guodong Xu Subject: [PATCH v4 05/20] arm64: dts: Add I2C nodes for Hi3660 Date: Thu, 15 Jun 2017 11:04:02 +0800 Message-Id: <20170615030417.14059-6-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhangfei Gao Add I2C nodes for Hi3660-hikey960. On HiKey960, I2C0, I2C7 are connected to Low Speed Expansion Connector. I2C1 is connected to ADV7535. I2C3 is connected to USB5734. Cc: Jarkko Nikula Signed-off-by: Zhangfei Gao Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 22 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 56 +++++++++++++++++++++++ 2 files changed, 78 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 64875a5..1a4d6c5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -29,6 +29,28 @@ }; }; +&i2c0 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + adv7533: adv7533@39 { + status = "ok"; + compatible = "adi,adv7533"; + reg = <0x39>; + }; +}; + +&i2c7 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; +}; + &uart5 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index f55710a..9abe84e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,62 @@ #reset-cells = <2>; }; + i2c0: i2c@ffd71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd71000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@ffd72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xffd72000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@fdf0c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0c000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c7: i2c@fdf0b000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xfdf0b000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; + resets = <&crg_rst 0x60 14>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; + status = "disabled"; + }; + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; From patchwork Thu Jun 15 03:04:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105616 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595488qgd; Wed, 14 Jun 2017 20:06:11 -0700 (PDT) X-Received: by 10.99.111.201 with SMTP id k192mr3087488pgc.192.1497495971136; Wed, 14 Jun 2017 20:06:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497495971; cv=none; d=google.com; s=arc-20160816; b=J0H3D02sW7lOplEz8PgJxS5FCkXU2eipsA3YYUuKLiw2dfqxr9BR7tHrrabvVD2nv6 eTtDUU2f6HVjOtNdyQoQyQmW8yQVghY+QFt9JH4Ds41Hc4VcybbOVLPno1uD8K32MiO5 Wh9SmBJvtnS8EVaA9C/Xg69aVkjL1VETtX1MjxU4ZEjfKN19kejRPP+z2uT/9vikkF/C dZR7Mz1rvt2SpsHcMGlrib+D0z9vSh6ptPkHcJGZeU60cthF9icBzMeCjdL29kOmiRHn mC10ojcJ6Ctv4EIhv66ccN4Q5qVKoBVlG4NW4ABRwLiYFbl5k/kHmGe+xsLSue5zkC8k fZag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=k8Ua5NW6C9wPym9b09CPYTT3lEpYCLQ1o8b+snEe/0M=; b=Er+AgnfKbUblEXJYSNoZ0KFgluogA85yRtssZHrGS9t4FWp+7BwVE6Ti7392W3Wv87 IleczOjsVYwQmlLjIUMYq/7SOFjyhAxzgpXcpZI2lQ/gSd7/qT0ISjHZBS1Ph6a+/HCE r3CqoshPwHuc8ePbKrWGtv0cOzk4O0gvmiKdymQWgekmUCWY3lT2H2H1yi4x0WviuUPH ItuY9ltaDzt0TCs8j63AhnpNS5Qaye9lI59eWmLPQVuByiTvsRBRvCKYMHirDKcfpEfs RlSIOp7iSxQwXa5u4kQhZbj0gc/IKESOzQOTxmEaXw2whasRv2NH/m3RkeJXm4kafPdG gySQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=h9mZz7h4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l3si1276519pld.259.2017.06.14.20.06.10; Wed, 14 Jun 2017 20:06:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=h9mZz7h4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752624AbdFODGD (ORCPT + 25 others); Wed, 14 Jun 2017 23:06:03 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:33271 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752094AbdFODF7 (ORCPT ); Wed, 14 Jun 2017 23:05:59 -0400 Received: by mail-pf0-f181.google.com with SMTP id 83so1414408pfr.0 for ; Wed, 14 Jun 2017 20:05:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k8Ua5NW6C9wPym9b09CPYTT3lEpYCLQ1o8b+snEe/0M=; b=h9mZz7h4InDTguDWR7v/Y5UObS9qgYg4EHkItuJdjnGSG8LfT5LR1wkCvpIUklI8jg PvsUKekvSkTs6HY2aC30svhoMC68bQaVGwSMulRlzTMhi6vVKWxsPgsMwtPNaeuf9wbR LOexWbc3mIWLo+PxKiW0auD4JgdFVkRVygvsI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k8Ua5NW6C9wPym9b09CPYTT3lEpYCLQ1o8b+snEe/0M=; b=HRt1IF/anE8IVill1/u2H/Jn9uUkOh6GdZNvpwQ+NGha3d/TzOzyjOFlUWYNlDoT4p RxLGsW3NOlRd+0fa6xv/jBBaO9H0SJI9dbu5kBOif489uArey+enPI0hh0JcAUhuB9/K 0/u3o0iGCIVtxtskG26EhsA0G15mDjZ7gZGKeHMH5IYHmnPxmhVzVAH8iKRRaqz13ji2 ZwHfh4o7sbDyJrOqzjc68F3Im8yeAVeo/lIwDLh5qrZTLlLnznUMK6fpjbKFC7Bd7j+Y gDv3Uc5PvTbhaz/A+0ab0EXcUpnz67yVAkoNU5j6gR7yIfR1RI1uaHmuFyqp1MUrt0Fb scpQ== X-Gm-Message-State: AKS2vOzUSnnqj9vP5ZOPRBqLRzm7z7Jvnu03e24krO5GUTgkXnQoHA0t u6ev/K8nLi/rRCez X-Received: by 10.84.175.65 with SMTP id s59mr3602676plb.20.1497495958907; Wed, 14 Jun 2017 20:05:58 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.05.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:05:58 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Chen Feng , Guodong Xu Subject: [PATCH v4 07/20] arm64: dts: hi3660: Add uarts nodes Date: Thu, 15 Jun 2017 11:04:04 +0800 Message-Id: <20170615030417.14059-8-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Feng Add nodes uart0 to uart4 and uart6 for hi3660 SoC. Enable uart3 and uart6, disable uart5, in hikey960 board dts. On HiKey960: - UART6 is used as default console, and is wired out through low speed expansion connector. - UART3 has RTS/CTS hardware handshake, and is wired out through low speed expansion connector. - UART5 is not used in commercial launched boards. So disable it. - UART4 is connected to Bluetooth, WL1837. Signed-off-by: Chen Feng Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu Reviewed-by: Zhangfei Gao --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 20 +++++- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 74 +++++++++++++++++++++++ 2 files changed, 91 insertions(+), 3 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 1a4d6c5..0a3f2e0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -15,11 +15,17 @@ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; aliases { - serial5 = &uart5; /* console UART */ + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; }; chosen { - stdout-path = "serial5:115200n8"; + stdout-path = "serial6:115200n8"; }; memory@0 { @@ -51,6 +57,14 @@ status = "okay"; }; -&uart5 { +&uart3 { + /* On Low speed expansion */ + label = "LS-UART0"; + status = "okay"; +}; + +&uart6 { + /* On Low speed expansion */ + label = "LS-UART1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index b03be4d..7a90c92 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -242,6 +242,66 @@ status = "disabled"; }; + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; + status = "disabled"; + }; + + uart1: serial@fdf00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf00000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, + <&crg_ctrl HI3660_CLK_GATE_UART1>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; + status = "disabled"; + }; + + uart2: serial@fdf03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf03000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; + status = "disabled"; + }; + + uart3: serial@ffd74000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xffd74000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_FACTOR_UART3>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; + status = "disabled"; + }; + + uart4: serial@fdf01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf01000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, + <&crg_ctrl HI3660_CLK_GATE_UART4>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; + status = "disabled"; + }; + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; @@ -249,6 +309,20 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; + status = "disabled"; + }; + + uart6: serial@fff32000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfff32000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_UART6>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; status = "disabled"; }; From patchwork Thu Jun 15 03:04:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105619 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595605qgd; 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[209.132.180.67]) by mx.google.com with ESMTP id f32si1334027plf.393.2017.06.14.20.06.32; Wed, 14 Jun 2017 20:06:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=BNJq6Mr5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752668AbdFODG0 (ORCPT + 25 others); Wed, 14 Jun 2017 23:06:26 -0400 Received: from mail-pf0-f170.google.com ([209.85.192.170]:34993 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752094AbdFODGY (ORCPT ); Wed, 14 Jun 2017 23:06:24 -0400 Received: by mail-pf0-f170.google.com with SMTP id l89so1389366pfi.2 for ; Wed, 14 Jun 2017 20:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X6/H86AoT9SYw5uZPqpjGBaeqytuolgQzVCEB6Bujm8=; b=BNJq6Mr51UzTg0P2x8AfQ8aqxnzQttgO+vFAVokynyQGygpv03lqah52WBnqueawXh K6c7GnJUmAs1bKB9fSoySdkKUTdqkcB9r7lLNqyNZP8ExdPI51FEXTpXZXwR/wpiy7HX CYaiIPXvKxBm/Rcd+KArItIZ3u+RHPxfpSy+U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X6/H86AoT9SYw5uZPqpjGBaeqytuolgQzVCEB6Bujm8=; b=Wr3CYZ2ws+MH+T4LGf9ip2DJ5mm5IrCXLw0EfZaw9nyQ5DT5r7UnAMtRH0zysEumqc DIkexVrf3GZ6AboDaJTCQKVykHK0sQxeEtleYHh1lduPxg6sflw10Dtlhf2REyAoffRa rWr/3OSiJrtIbGH6UkNvxc3mnc9zhoEu4ewr3rS66kUdFgkPIuqXqcLtWZWKW4pAxHCc 7a1Unzthznr0wHnzwrI7fwtMWjFmvtTXqP+FTVcWYW8avg999yrwyTpokUWXsSW7/U9d XRh4idF6t0FDbz4J+IvkUwM/2m5sCEYwsK4qM7gPcQghV8/l1irMmWfO/NdNWM/Sjej8 2+JA== X-Gm-Message-State: AKS2vOznPZBhflLy0Kp+9tmnnRkIUt4AaeqVf5BtcQNzBr46JQydQcLw NIKCFo6dBpfbaO6S X-Received: by 10.84.175.65 with SMTP id s59mr3604413plb.20.1497495983759; Wed, 14 Jun 2017 20:06:23 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.06.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:06:23 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Chen Jun , John Stultz , Guodong Xu Subject: [PATCH v4 10/20] arm64: dts: hi3660: add power key dts node Date: Thu, 15 Jun 2017 11:04:07 +0800 Message-Id: <20170615030417.14059-11-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Jun We use gpio_034 as power key on hikey960, and set gpio with pull-up state, when key press the voltage on the gpio will come to lower, and power key event will be reported. Signed-off-by: Chen Jun Signed-off-by: John Stultz Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index c25fff9..7aac35b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -10,6 +10,8 @@ #include "hi3660.dtsi" #include "hikey960-pinctrl.dtsi" #include +#include +#include / { model = "HiKey960"; @@ -34,6 +36,19 @@ /* rewrite this at bootloader */ reg = <0x0 0x0 0x0 0x0>; }; + + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>; + + power { + wakeup-source; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + }; + }; }; &i2c0 { From patchwork Thu Jun 15 03:04:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105620 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595673qgd; Wed, 14 Jun 2017 20:06:44 -0700 (PDT) X-Received: by 10.98.58.217 with SMTP id v86mr3008500pfj.115.1497496004062; Wed, 14 Jun 2017 20:06:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497496004; cv=none; d=google.com; s=arc-20160816; b=ELXZvVGlmWYwNfvhNfIe8o0E9/fWqTmvr0N6/PSXneZ+Y1dmXAyiMa1cmJY5DrMo4c keYpDIB7Uo/IMtuRjkH4m+DTjhlV26l0PcR9bw61aB/ZvJB8341mFBmvrmLKak71YZFP 3xk7qP04mSLuQn6/tUe6ePccMdWvBzhieGGSYsZ+DYTWa6DsilAMVGSz7ci2HbZniUk9 oCHnijgYqBn88EGX5lZuDaoHlmxZy3RQBvtvGBjSzGT4FkymzKlcKKnycYJrlPGcT9/x FQ7rrHENXID+ijf338A8dEC0pQ932TDndK9HKuDsIHDAuPUPyM4Zo9e4g0YiUajwvbc+ yhZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=CEk6ak4alSfIGm/cBrYd0NkRqFdpaNL+qzPQmngGnUA=; b=VlfRGoRqFxWOadpS9uMvgoC2lOSwO2xzDA+8oXUVRWl5Y+dCuZnG5ySpoLKgGNw8+t cYdKNP/486qjK5CDSc9n7LSGWf91h1YDVwJa9R3pFJoSIGthfJEgXYg+o6gettAEEPk/ 4ZCFrGPxwZdTkcAYVfZ6YdIqEDzVN+7waYZ8qsjiVwbCaOL0472FEaCZ8u88UVUj9qHm ke5t8gdf0FwislgOUatqM0psw0yG7BT58YCHZxx1ppw63Dc7FkELZaEx4I7bWtapHeyV AvoWY1pxOnRdoBwcqQSOYqabEwkZg0Xm0+z6S2wIDihJJRHNP7xICwkqL6kUPSRPpkOG KrPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=VZ9MK2J3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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All of them are implemented as GPIO. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 48 +++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 7aac35b..9ecf6c6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -49,6 +49,54 @@ linux,code = ; }; }; + + leds { + compatible = "gpio-leds"; + + user_led1 { + label = "user_led1"; + /* gpio_150_user_led1 */ + gpios = <&gpio18 6 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2 { + label = "user_led2"; + /* gpio_151_user_led2 */ + gpios = <&gpio18 7 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3 { + label = "user_led3"; + /* gpio_189_user_led3 */ + gpios = <&gpio23 5 0>; + default-state = "off"; + }; + + user_led4 { + label = "user_led4"; + /* gpio_190_user_led4 */ + gpios = <&gpio23 6 0>; + linux,default-trigger = "cpu0"; + }; + + wlan_active_led { + label = "wifi_active"; + /* gpio_205_wifi_active */ + gpios = <&gpio25 5 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led { + label = "bt_active"; + gpios = <&gpio25 7 0>; + /* gpio_207_user_led1 */ + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; }; &i2c0 { From patchwork Thu Jun 15 03:04:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105621 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595762qgd; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) X-Received: by 10.99.151.1 with SMTP id n1mr3137167pge.255.1497496021136; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497496021; cv=none; d=google.com; s=arc-20160816; b=u/XaUJBL+nnz1WkijcM2+iFGRo78Slvg+JKj1Eww3ioLcWD/Vwe32H1S2e5AVz09ov UkMwVkdupTcisyqGx5C0ONRsk1PlHqnP8nAR4dKLF8Ztk6rGWgbI4j1qr2Jy1i2bGUcG 0Ecz58iwDaaZxkCmjL5t1mNzRGukBU/azbDhHf9x6dV5n1cOZhq7ZQ5mJ0VW9OK48Jts 7rAF25XEVQDQkfULLEelVvrWh1dIp/wrdJMCaYLDmLVuUccmbS07Xqt5960vP60LL/a/ CnvgpROJ4uZhHtjQClE65OU03VZnC7H54vCnsW9xQudbNn8Zj36jaHo3kc0Q/ywwYW/C mTYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=ERloCrgoW7X6+khtCmA5xuILYYSPoxcBcxGp23HuekcQKXJyDYtyY38qSfyv5KxE+b yz2tDKtACWjl2EYZULtDr9VVFO3fQFkemGYBtPBIPzGRZXP5r2lDe6ltbYCoslJjxzoZ dx4E14UBecJvDT8QKckkWJAYzvLy5TL5aBA3aj/Xm0QlMnxir7pBFAAUGob5RE6D9M2L zUox731AKc0+CQ2xU4XmNaSP8deu5d8MV+zvEYFXLszcLHZoDdNyPMx9k54y3ipuINWT vNrN0e8FPxnE2bJnjh8Rz+QJhO3ps4U/RidddweEBp7lJMtbryFk+PGbNJefci6gtenc YDwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=aMvJTNpZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n34si1305188pld.268.2017.06.14.20.07.00; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=aMvJTNpZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752700AbdFODGr (ORCPT + 25 others); Wed, 14 Jun 2017 23:06:47 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:35050 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752140AbdFODGp (ORCPT ); Wed, 14 Jun 2017 23:06:45 -0400 Received: by mail-pf0-f175.google.com with SMTP id l89so1392215pfi.2 for ; Wed, 14 Jun 2017 20:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=aMvJTNpZACKHuAcMIi7cS2M+CwqKdBZgEVeO/4iRM0V5JNJcpi4CkdUKlUIO6hBYrw 1FRX5X2AkMlolWYfVpmwVbPI1VGlsT44NJWyduEGW3NlezUfR23CrcF5Y2CPjjWwqWUk 7C/Qo6O6NeNLI90MmY1rbRDixcEplMXpVQVPg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W4L2d8u22c6yygXQJRk+Sqhtqu9yLqxVCuULdrLlfyQ=; b=FbW2RD2O6GWRXajXmkuV4VS7SEx9Q5PuMUoPLX/mk9+hyV4KMiOnJtj2umRf0X0/uW R6YHsKnanfKFXgxpDC2bbtTgsevuFVuRlK2Ja0lDQOyelKuu4aO9S94YvC8K9XJStPay GRC+lR2A+Q1R7FqhzTDjBzxPf53No4UUxRGYwddStlMabefHlLKvTSK2EUjSfOGoa5jp 2zij78ry3RKe+j9A8/nI7vHGQqP6SHn8VrsT8uloa46R4wYVp214BWSVn7sS8xZIKEnh bTvX0SvhwWIydxdP2u2ykB1vTQJWYVSyg/mebb8s0C72iI2bEih93DTo/ytRfsIfVME7 GAzw== X-Gm-Message-State: AKS2vOy1yFP9p4ShP4EUYzjteS/zKz9sSChCk6PazCNVv8V2UiBR0WMv N9PYjeR8AVVnROqW X-Received: by 10.84.137.165 with SMTP id 34mr3564647pln.167.1497495999816; Wed, 14 Jun 2017 20:06:39 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.06.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:06:39 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Guodong Xu Subject: [PATCH v4 12/20] arm64: dts: hi3660: add spi device nodes Date: Thu, 15 Jun 2017 11:04:09 +0800 Message-Id: <20170615030417.14059-13-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960. On HiKey960: - SPI2 is wired out through low speed expansion connector. - SPI3 is wired out through high speed expansion connector. Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 12 +++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 30 +++++++++++++++++++++++ 2 files changed, 42 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 9ecf6c6..ca448f0 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -142,3 +142,15 @@ label = "LS-UART1"; status = "okay"; }; + +&spi2 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; +}; + +&spi3 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3b2a3a7..a6b91f1 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -713,5 +713,35 @@ clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; clock-names = "apb_pclk"; }; + + spi2: spi@ffd68000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xffd68000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio27 2 0>; + status = "disabled"; + }; + + spi3: spi@ff3b3000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xff3b3000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio18 5 0>; + status = "disabled"; + }; }; }; From patchwork Thu Jun 15 03:04:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105622 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595769qgd; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) X-Received: by 10.99.53.197 with SMTP id c188mr3066649pga.165.1497496021545; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497496021; cv=none; d=google.com; s=arc-20160816; b=a95J0KsSvD3mt+zv1AYEsRDp8pGrkDsY/KyPDcYMggRvIt8+xTpo6wKQsRr1/nsSAH EhTwptk3C69AiWcWxLFihDduuZjAR5GdViWeO4JqjH75qFi7H+HzaEyUDra9BthwFYV1 B9UCTXaDTaesMM+DlUfJv+w/yyVwyNOUolTz91ErmMOsrXu/uOkpQ0DRc9ODeF1tboWh 7lWORfWTgoObGCjyJI5RYgVIufNLjlturti0dhXtcxo0gVcoeqa29pBX7wrHcegDgUxa uAJApCy/4GQUc/ZjNZrN3qSqahSJpkR5oARLa4rvnImbJAu2FapgDSitMLa8MnmvLK2l omWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=BWAVSdple2zbDiMgL2+wnP4CVoOfpE0fcrBK4dNeJwiHUFZNi+xZZ1TNRnTj/Qsec5 GiRyzG1i3dLmrziWGDyjGiV1hL4X2xttFOTvYxsWgl3BI2UbeeRRPabjf0kXW5U2hBea 1lg7jLXJYDtVACGZx1YBlkpT+t/269k9Tq6Hb/5c6Ld2oQeWCJ1O+s0dm9Ok5S6kBX7j avEWZvUegyL+YIUpd+OB5uY5RXg74PS1BYAS+/KYtVBSYf3Qhjpb4VP25P8culzOjg53 DIMsDhbvtmfvTclZpRqgeW6wjJ5UMeIFzgi95i/9yrPfA01Ui6qT1m1A84t7erKQoyyd NMeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=QK7h2rmu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n34si1305188pld.268.2017.06.14.20.07.01; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=QK7h2rmu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752720AbdFODGu (ORCPT + 25 others); Wed, 14 Jun 2017 23:06:50 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:34033 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752140AbdFODGs (ORCPT ); Wed, 14 Jun 2017 23:06:48 -0400 Received: by mail-pg0-f52.google.com with SMTP id v18so1273480pgb.1 for ; Wed, 14 Jun 2017 20:06:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=QK7h2rmuyNnJzQ5RJjN9cg+cX0OHLe3gklkcWiiujrkNRcKt0RfSE6qfATFkSvRvOT /Ccn8kOZtvzko5zuimuZSIFU/GDVInoh2E8Pjyb7p5r1+spIhFKYBII7IEEkwXzl2Hmf 08vDOj/INwMM5yS9+PPeW3rKtsG2ETDieVulg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=aZbFkEXJLWXa57pABg3tsTVlr9w+xt3XmGtbds8Ur+d0sK+lv6dIDhbhoQnunnxBL0 vc+yrv3a2keVpMniLvsLTwrYbAYs+muvTnf+w3Sw9VTjOAFR/FWVgLwV1luHQyC2TMgU n1wgEfv+TjfEZDtJueNFEO/cD9Kh7c9Bcj43cWBIPR3N+ZfspRpzcGdfIrPk4CMiq/c/ leAaqZ0G13nt8Z3PJ9UTSouNgtEizMg2CN/IDV2z3VLYg2KW0VMRKltCJpKKc2e6vx4A FCMTwn2gw5e1ntrTGSfUFca+NQSjXVBbEFVUtCtHlEsyjGwogtEeFpBgYdPLXLnZG6ZU 8djQ== X-Gm-Message-State: AKS2vOzSLPJpvFbR8op0KluHtvefiTiMPjLcBRNwDU/1/+IlXKPVRhc2 ar5BcMyVQZhcKqL2 X-Received: by 10.99.165.17 with SMTP id n17mr1737051pgf.163.1497496007725; Wed, 14 Jun 2017 20:06:47 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.06.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:06:47 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Leo Yan Subject: [PATCH v4 13/20] arm64: dts: hi3660: add sp804 timer node Date: Thu, 15 Jun 2017 11:04:10 +0800 Message-Id: <20170615030417.14059-14-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a6b91f1..e138973 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,17 @@ #reset-cells = <2>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + i2c0: i2c@ffd71000 { compatible = "snps,designware-i2c"; reg = <0x0 0xffd71000 0x0 0x1000>; From patchwork Thu Jun 15 03:04:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105624 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595859qgd; Wed, 14 Jun 2017 20:07:16 -0700 (PDT) X-Received: by 10.84.160.204 with SMTP id v12mr3532657plg.91.1497496036580; Wed, 14 Jun 2017 20:07:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497496036; cv=none; d=google.com; s=arc-20160816; b=U/Saqg1l6mFlEBJZ4gRToHLhjBDM+1PwYl3JZ73zHSu6vCjjMFHzeZ4SywCRqSGN6w cZhMlve6hIq1cL4J3SzWJs0weKSLK6eTrDPH7Ft8hlgEhSp5Zi3ohWfPRNlkKwLeBe9f Y12G7lQWIe4IQOUNkZaCtoVVIws6YjIEn213I2xFGY+iYileojW2l4Kh0CWlG5PEJBLi MPDhgWp9Ka2tQWOU3kLIOiMnIdk0CnTew41aKZVF/w51vV0LQehYjfGU30v+FW9sa+QK iosEy7io2VRekOfRkayKALsQrYtDpLmn5TndpMi8CLkD4NH1B6UH3OrNCAmw9L083zcW TUNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=QmMsa438Vndpt0bSvJ6J+nTkIDX0vLnDog44Prz7oeo=; b=y2QzkvBgoHZ8atv7ls9hxlrlNjvUQQ9DnXrIT3vBnxmk4C9qDOJWu9DDdqfPlezMWS vnUoMSsf0lEQ02k3PGaNH810ogO7V5i7402IaJ37tO9y0PHCYeftSQtUBE7PayBwPmBa ftajsSKUHr8eQINQXhjCA+pTdBVBBD1OATjl2IppAmd/Xk/WTCp9L8OFYivAGIwVEZDO InMdX9eYtOAV+6j6IHUhTE49aW/UMlh5CbypeXrqKZDf9CjtsNYHGAbj9hqs6jBPsqkH JrqX3UeUoRAzMEzK8v9B9DBWHHylGOQ9MZsdK7sBgXVum+xXLOgb+/YoBBPu0v8gu4n+ dbNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=ZGdqPLyx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s2si1341922pgr.230.2017.06.14.20.07.16; Wed, 14 Jun 2017 20:07:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=ZGdqPLyx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752752AbdFODHH (ORCPT + 25 others); Wed, 14 Jun 2017 23:07:07 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:36471 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752379AbdFODHE (ORCPT ); Wed, 14 Jun 2017 23:07:04 -0400 Received: by mail-pf0-f173.google.com with SMTP id x63so1368218pff.3 for ; Wed, 14 Jun 2017 20:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QmMsa438Vndpt0bSvJ6J+nTkIDX0vLnDog44Prz7oeo=; b=ZGdqPLyx+YEgX+C6zeqeRrFWO3KdcGlwMyY5APLzGBNK2ASohfmN5n+JsyG4fLuhlh Qfu6bzi2WEv9OB4tBDW/2FG0sCvvBd+sr/CEDHdbU9UDxktE2cXGsISMIp8mD8bF6Xfw LZXDsj3r/J0eZnqyBv8n/1h3697jYoXfq/TKI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QmMsa438Vndpt0bSvJ6J+nTkIDX0vLnDog44Prz7oeo=; b=SXsICPSRMtUiZG2rQP1u1G8ofCKVDQN3jQLleYZTP75bG4ViPw1Vla/ONRG3gktxiE 8GyDqRLSFDkfHSS3Y+ZVo+osqasgAWiHZZiM5jQEh0RUmAWvlGF44hCyq8NY7WHTDkCL ukbcHzrFZbpVUuocK49yxTc5C2uWeM2t5G6uqKKbkZkZzjtaLQbv5HH62d8dYrIBe13i ebUYMalu3KTh7LbWS2p40bGMA4F1w61+tyrl59sTBjUNOi+dPr+V8ikwp3xucXnJvpcR ux9g5nOFc+ItHKu+gQyDftrCuK5Wk7jv/ijnZosQ2TMbUMSAbW3S2lwKXx/fuseuZ14y dgAw== X-Gm-Message-State: AKS2vOyip27dcP7uRKl8L+4qDmSD54wekAKkhgXxRlNPLIFanO9vMXTk h8x283fHUXhwMl1A X-Received: by 10.98.35.18 with SMTP id j18mr2977721pfj.161.1497496023965; Wed, 14 Jun 2017 20:07:03 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.06.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:07:03 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Xiaowei Song , Guodong Xu Subject: [PATCH v4 15/20] arm64: dts: hisi: add kirin pcie node Date: Thu, 15 Jun 2017 11:04:12 +0800 Message-Id: <20170615030417.14059-16-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaowei Song Add PCIe node for hi3660, and add binding documentation. Cc: Guodong Xu Signed-off-by: Xiaowei Song Acked-by: Arnd Bergmann --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index e138973..529cf08 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -754,5 +754,37 @@ cs-gpios = <&gpio18 5 0>; status = "disabled"; }; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 + 0xf6000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, + <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + status = "ok"; + }; }; }; From patchwork Thu Jun 15 03:04:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105625 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595897qgd; Wed, 14 Jun 2017 20:07:23 -0700 (PDT) X-Received: by 10.84.224.12 with SMTP id r12mr3677091plj.286.1497496043601; Wed, 14 Jun 2017 20:07:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497496043; cv=none; d=google.com; s=arc-20160816; b=K56XsFotgXkivSQUDUmHVB9Ko04G1mzz7v8m2nnnj2l488oBQNSWApgRhnCVmgkjKN 27AbO9vNhcn3riSq0Suyred9MhYnGBHeI+2DqjlIklFfYjsahgVy6hhj4KVafzsC4gBL k+C1Bt6RQt6j2CTHspEAndoAuG4xM74klDjr+4kyDT3omBJ2uZhv2/PKtozuOygVqv2w jhsR1ZTo+JDMKr7ZRdWBky3j6qzBVgo/kjK/Qi7xXqCJXPHR40gN6yRoEz89Ka3LHLEx HtvMPiqCCB6nxkqlY/C+9d65FlhuPAoA/56/OeLANtwjt1ETU0OybYazhQx+ZVRU7TrY p4DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=JAUJSqFgMuH4Te8WDWqpSI0I/XMKqIIz3WeHBUZ7x/E=; b=gyClCBUJ4TyL0tWbJVRrUUTciEsBHj/uo9dXBW+XVvcZE1fGYbqJqID0IQVPaAjLGw mCAc5F7xpwBNYPeRC9IK4Y+MMZtViF/UZoqHrFitMdzw4/z6aslOKAzhuMW7zDPYbazS Io6F6huhDmzXqXFes5Yi5UISAfYLBERbznoZdlrR/F41h0ZthFY0qrU09b/V0JrcPtbb jmIN4kF0EhrMMWM/giqSU0yWOfKC85+GvMG+qNrz6eqdfoFMpd1mo0klw2iyJXoqBbZp xTDSy7JW1ecCkDkTsncNwcnlGYw1ouSzK3oFcy2fHecFRag9TGwxA4N9FVjkkm54+HX2 Kszg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=gsFOAX7+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l12si1294501plc.424.2017.06.14.20.07.23; Wed, 14 Jun 2017 20:07:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=gsFOAX7+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752757AbdFODHQ (ORCPT + 25 others); Wed, 14 Jun 2017 23:07:16 -0400 Received: from mail-pg0-f50.google.com ([74.125.83.50]:34111 "EHLO mail-pg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752072AbdFODHM (ORCPT ); Wed, 14 Jun 2017 23:07:12 -0400 Received: by mail-pg0-f50.google.com with SMTP id v18so1277370pgb.1 for ; Wed, 14 Jun 2017 20:07:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JAUJSqFgMuH4Te8WDWqpSI0I/XMKqIIz3WeHBUZ7x/E=; b=gsFOAX7+tgPZxLH4SZA0cMbhgaMdF+lV8ryI50sHR5JhAKzMc6dJZVpwiszqyT8R2Q v73Vo3ftRjSG4t94Hd3muc0NmKQWr/PBtNHyldxvxYxLiWl0fJ+zqNsV/PUv09DNIXm2 cnyoR4tEa/DsPoWYiUweXA8W+mi83lZtnaf48= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JAUJSqFgMuH4Te8WDWqpSI0I/XMKqIIz3WeHBUZ7x/E=; b=DCDvmBkvyZ1K7P5srjREurY1K0mI2bFVV1EEJOFaPlYkt6IWD3F3zFLtvnwFy1v0wT ycWBXgq32SMXe3zlod9upRhZEboklHc58T8wnOy/FL9Iktg0aH5vjSoCl5GlsAS32lpa MC0NzXYApwi5StacVoHfucQ6mEyDeAyR+GqeTeIkok995fcOMrKO2WD2gYOlN+oOe941 fANL2iCc4hcpoUVzqVe0MeqQLChSX9g5BURtnM+dgKjQiOIZhaUlFgaCzS2v2Kwl7p9X MXdFeA9eZbwand17uFa12isCAPNtjsq9ZLl6SJ0hjD/lntR/mV29K+RBeIKGjpRZ9DRM cfoQ== X-Gm-Message-State: AKS2vOy+yH+trifmZDXvhjZMK9kwZc4WlOfe8fgcGf/aYUiAYlGlhdYn ke53Hy8IcTwN/mbo X-Received: by 10.84.232.73 with SMTP id f9mr3648395pln.28.1497496031956; Wed, 14 Jun 2017 20:07:11 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.07.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:07:11 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Guodong Xu Subject: [PATCH v4 16/20] dt-bindings: mfd: hi6421: Add hi6421v530 compatible string Date: Thu, 15 Jun 2017 11:04:13 +0800 Message-Id: <20170615030417.14059-17-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add compatible string for HiSilicon Hi6421v530 PMIC. Signed-off-by: Guodong Xu Acked-for-mfd-by: Lee Jones Acked-by: Arnd Bergmann --- Documentation/devicetree/bindings/mfd/hi6421.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.10.2 diff --git a/Documentation/devicetree/bindings/mfd/hi6421.txt b/Documentation/devicetree/bindings/mfd/hi6421.txt index 0d5a446..22da96d 100644 --- a/Documentation/devicetree/bindings/mfd/hi6421.txt +++ b/Documentation/devicetree/bindings/mfd/hi6421.txt @@ -1,7 +1,9 @@ * HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd. Required parent device properties: -- compatible : contains "hisilicon,hi6421-pmic"; +- compatible : One of the following chip-specific strings: + "hisilicon,hi6421-pmic"; + "hisilicon,hi6421v530-pmic"; - reg : register range space of hi6421; Supported Hi6421 sub-devices include: From patchwork Thu Jun 15 03:04:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105626 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp595917qgd; Wed, 14 Jun 2017 20:07:26 -0700 (PDT) X-Received: by 10.84.150.130 with SMTP id h2mr3703874plh.152.1497496046536; Wed, 14 Jun 2017 20:07:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497496046; cv=none; d=google.com; s=arc-20160816; b=QfAR4EQBcafNgG+XDzU3xxJJ1Ef3yzt9/cEWUuKIpcYS1kciP1Dyc75x+I4cDYVGb1 npglOOWbDkNYJiMGNqXmsiMahkHBsSwZlG4GryVtAUlEUVO6U239RkGGqetDwNXOsdk/ XCKPYEP91bm9XHGglLajE5fBrsh8npuT7j4WDj61wx331AJV/8c3nwVEkbCV0yL9hRv6 vN8QpdDj+c7ysgodV7x9iG5eU2eaeK6jd9Su62wR1IJQl88r7ufJt+HI75hssjtJGrMM 3PvDAQvbQ23cCd+RaqXc/KJyW8GOJb/a67j0Da+vrMYiMfECi+Xbn3FSBrDGu5OBL1Gi sA2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=8PV3QUvE4/KsHx+LrJUzAofvvlExf85kZV20f2X9des=; b=ZXbe+WNvUHUpqBiz1/hTKvBwKQlCXCVHAPRBGSwEee70JTX4UbrN/g1nSPg/RbKq67 9EYgCqV3ROpfgKjLJMq3awS6g0b+DbDxx85xVPMoWcwNtR50wo31YDMjPBRfI/Xp942O 9FmBgIdRU0vrE87qLbaTwlMrHEtcTLt/CP1YHD4kHvLebyyGR+FAfJ/gzVGtgZFjszoN 4okQ4e8L8832rejcMl4G0gomznIJuyublOCaMmGy42v7t47NItV9h3WpiMcxHO1cngPI ubNEReVAJtLkT+UDnXMB5yNBOJ7Ehsv5FQUmvODSkRUIZZJTZPmuzHIGP2XLW6GsRMH7 ICbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.b=c7hKfxwv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 14 Jun 2017 20:07:19 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.07.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:07:19 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Guodong Xu Subject: [PATCH v4 17/20] arm64: dts: hikey960: add device node for pmic and regulators Date: Thu, 15 Jun 2017 11:04:14 +0800 Message-Id: <20170615030417.14059-18-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin add device node for hi6421 pmic core and hi6421v530 voltage regulator,include LDO(1,3,9,11,15,16) Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 46 +++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index ca448f0..e579333 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -97,6 +97,52 @@ default-state = "off"; }; }; + + pmic: pmic@fff34000 { + compatible = "hisilicon,hi6421v530-pmic"; + reg = <0x0 0xfff34000 0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + ldo3: LDO3 { /* HDMI */ + regulator-name = "VOUT3_1V85"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <120>; + }; + + ldo9: LDO9 { /* SDCARD I/O */ + regulator-name = "VOUT9_1V8_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + ldo11: LDO11 { /* Low Speed Connector */ + regulator-name = "VOUT11_1V8_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <240>; + }; + + ldo15: LDO15 { /* UFS VCC */ + regulator-name = "VOUT15_3V0"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + regulator-enable-ramp-delay = <120>; + }; + + ldo16: LDO16 { /* SD VDD */ + regulator-name = "VOUT16_2V95"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <360>; + }; + }; + }; }; &i2c0 { From patchwork Thu Jun 15 03:04:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 105629 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp596061qgd; Wed, 14 Jun 2017 20:07:52 -0700 (PDT) X-Received: by 10.99.166.18 with SMTP id t18mr3052083pge.218.1497496072646; Wed, 14 Jun 2017 20:07:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497496072; cv=none; d=google.com; s=arc-20160816; b=E/gPuH6/HQkmn8PakLd/CdU7yQLgTgGRkY7dgQSyDBTWFhC2FMxbA+xpSsvhiBiCgd BBinHVsDbtqIllLXbUyTGi5CpZBygZiLVFlBKFFx+75q0R3maNdiyUYDE5mAUt+fh042 gWn0rhxCYeI6vJLRhH4DGYd4k4hJXSbQHc5VzVLug0Lhfik72tB9uRuD3K9Q2lpzS7dy XH9RlBmXHtFwXkFOCoxrDn7A6H4Xw6glnMCMBV2zod9EF9TEwqbRtLgAJTvUPXkKkrtc 3YlgIwssekrd87bIE2/X9lMpRoQxlhD/r2mo9CWhgJfCDMSWAAQbhuxGI4PpxJOL/QUR lh2g== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id d18si466152plj.132.2017.06.14.20.07.52; Wed, 14 Jun 2017 20:07:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=gaMx1crt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752822AbdFODHt (ORCPT + 25 others); Wed, 14 Jun 2017 23:07:49 -0400 Received: from mail-pf0-f176.google.com ([209.85.192.176]:35293 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752520AbdFODHp (ORCPT ); Wed, 14 Jun 2017 23:07:45 -0400 Received: by mail-pf0-f176.google.com with SMTP id l89so1404011pfi.2 for ; Wed, 14 Jun 2017 20:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RJOMtlQz706HpYCjUPrIeGDbOiI8QjXxJMk4XFwLaKc=; b=gaMx1crtbyqiSuzJI3qxJW8gNMauO4nwKlBdEhagQoQaDvrkElhn6VQmh17/eNYY7u jnE9ias5WN0UwOb2aLiqAaVa44R+I/JGR4Ozd7W7xKlhWf9Jt47KzxstInTVlpdNDJQe uIKlfJIQlZfu6wjrDUWm8I6gPwkFWpRfmCO3k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RJOMtlQz706HpYCjUPrIeGDbOiI8QjXxJMk4XFwLaKc=; b=nT9zEDVoQA530go79DfRFFvNBF8dcKcsSY+HjxnhqHMqJ0hVJFchLXxScGVyoWtvdA 4efwb7IudLq2SjhJP5w0K/EUHynrNFj0wMFZZIXjnO59uSjpG9KkTMMUCpa2zKoo5+Mx 7CxGL4HDP9SQC3mrlVyuuEerOBqWqdllZ/LnolScIpx4CVaZ5t3xTRQ9Uz6vvLqFKLNJ j+9h7qRwFiM7uOG8ArRSIZ4q+bG7PxYZeGtCiAGXXhw6BBcFUWBN6q7U9Z2ujW/2DTcl 132KohFdVS/gpYNSDLPJ7KkqTPXkmhEw/Lxvg9TQ4Tc4+OKjBs/QtEO7TKbmW/aAKNgZ UsSw== X-Gm-Message-State: AKS2vOw7cZsVFhVKgxyawxO67wCrWGrL6KLJuvtPrxwJ4YRikl8lotsm GD3UDX0uiPwRzElJ X-Received: by 10.84.224.6 with SMTP id r6mr3579230plj.132.1497496064452; Wed, 14 Jun 2017 20:07:44 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.07.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:07:43 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Guodong Xu Subject: [PATCH v4 20/20] arm64: dts: hi3660-hikey960: add nodes for WiFi Date: Thu, 15 Jun 2017 11:04:17 +0800 Message-Id: <20170615030417.14059-21-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add nodes for WiFi. HiKey960 is using TI WL1837MOD module. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index cec0b60..6609b0f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -145,6 +145,20 @@ }; }; }; + + wlan_en: wlan-en-1-8v { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* GPIO_051_WIFI_EN */ + gpio = <&gpio6 3 0>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; }; &i2c0 { @@ -208,3 +222,22 @@ vqmmc-supply = <&ldo9>; status = "okay"; }; + +&dwmmc2 { /* WIFI */ + broken-cd; + /* WL_EN */ + vmmc-supply = <&wlan_en>; + ti,non-removable; + non-removable; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "ok"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; /* sdio func num */ + /* WL_IRQ, GPIO_179_WL_WAKEUP_AP */ + interrupt-parent = <&gpio22>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + }; +};