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Date: Tue, 18 Jun 2024 15:27:24 +0800 Message-ID: <20240618072726.3767974-2-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618072726.3767974-1-quic_jiegan@quicinc.com> References: <20240618072726.3767974-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 3lSmKs2Mmku8ygoco9e0y7PJcvw0QTFi X-Proofpoint-ORIG-GUID: 3lSmKs2Mmku8ygoco9e0y7PJcvw0QTFi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-18_02,2024-06-17_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 mlxscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406180054 Add binding document for Coresight Slave Register device. Add a new property to TMC, qcom,csr-atid-offset, to indicate which ATID registers will be used by the TMC ETR. Each TMC ETR device is associated with four ATID registers that are continuous in address. Signed-off-by: Jie Gan --- .../bindings/arm/arm,coresight-tmc.yaml | 8 ++ .../bindings/arm/qcom,coresight-csr.yaml | 76 +++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml + }; diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml index cb8dceaca70e..295641a96c21 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -82,6 +82,14 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 15 + qcom,csr-atid-offset: + description: + Offset to the coresight slave register component's ATID register + that is used by specific TMC ETR. The ATID register can be programed according + to the trace id to filter out specific trace data which gets through the ETR + to the downstream components. + $ref: /schemas/types.yaml#/definitions/uint32 + in-ports: $ref: /schemas/graph.yaml#/properties/ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml new file mode 100644 index 000000000000..16f97cbe3d4b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight Slave Register + +maintainers: + - Yuanfang Zhang + - Mao Jinlong + - Jie Gan + +description: + The Coresight Slave Register controls various Coresight behaviors. + Used to enable/disable ETR’s data filter function based on trace ID. + +properties: + compatible: + const: qcom,coresight-csr + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + items: + - const: apb_pclk + + reg-names: + items: + - const: csr-base + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-7])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - in-ports + +additionalProperties: false + +examples: + - | + syscon@10001000 { + compatible = "qcom,coresight-csr"; + reg = <0x0 0x10001000 0x0 0x1000>; + reg-names = "csr-base"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csr_in_port0: endpoint { + remote-endpoint = <&etr0_out_port>; + }; + }; + + port@1 { + reg = <1>; + csr_in_port1: endpoint { + remote-endpoint = <&etr1_out_port>; + }; + }; + }; From patchwork Tue Jun 18 07:27:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Gan X-Patchwork-Id: 805342 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C3CB15B961; Tue, 18 Jun 2024 07:28:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718695714; cv=none; b=exYPMzIb1apa/gtvpVxr9FHo3k6k0Y+i2NlMTIbxi7w1V6UIGpe9jEpDYdMHT6Ub4asHZO/LnMzJRPSLrLV+8dlFwgB30kw7c28oBISQiMUlNodtPkbHdk3oK+Y4UonBxLIhQfHQeumgydVOGd3LQcPt9csagxTL+o+upOlp+1c= ARC-Message-Signature: i=1; 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Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 167 ++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 839c6ec0a957..1154d456c239 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1657,6 +1657,36 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + csr: csr@4001000 { + compatible = "qcom,coresight-csr"; + reg = <0x0 0x4001000 0x0 0x1000>; + reg-names = "csr-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csr_in0: endpoint { + remote-endpoint = + <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + csr_in1: endpoint { + remote-endpoint = + <&etr1_out>; + }; + }; + }; + }; + stm: stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x4002000 0x0 0x1000>, @@ -1860,6 +1890,135 @@ qdss_funnel_in1: endpoint { }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x4046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + qdss_rep_out0: endpoint { + remote-endpoint = + <&etr_rep_in>; + }; + }; + }; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = + <&swao_rep_out0>; + }; + }; + }; + }; + + tmc_etr: tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x4048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + qcom,csr-atid-offset = <0xf8>; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = + <&csr_in0>; + }; + }; + }; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = + <&etr_rep_out0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etr_rep_out0: endpoint { + remote-endpoint = + <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + etr_rep_out1: endpoint { + remote-endpoint = + <&etr1_in>; + }; + }; + }; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = + <&qdss_rep_out0>; + }; + }; + }; + }; + + tmc_etr1: tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + qcom,csr-atid-offset = <0x108>; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = + <&csr_in1>; + }; + }; + }; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = + <&etr_rep_out1>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -1935,6 +2094,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + swao_rep_out0: endpoint { + remote-endpoint = + <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; swao_rep_out1: endpoint {