From patchwork Tue Jun 18 17:48:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 805729 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EDEF74BED; Tue, 18 Jun 2024 17:48:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718732936; cv=none; b=Pk6Ytrf9MDni1sOUZSRMh12lX9tvbEtBfkKwxudWwRTzAl6A1LVm1Mex5dli7z6v34wkTPTZTlj2twcEIIcw7hYpRBbss1RqpNcXnbyloVfCzdsLR+l38e/ff9Ij62YDYP7Is5WtN0CSvjt9wAlgq+YQ1oTIV0hLbwtN2B2Twy8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718732936; c=relaxed/simple; bh=d8MiCPsTsovGTnI/Q5kn39SiBUQCeSWE1hTH3dewO6E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ikGU4Q2MtUh+PlSKUOYhFaS2HTQabDKD9EeSPiDiizdUm11xy9GTDYvsNWtDf+GgaLdBdrLF6oiLcJ3jsg2TeUEdLuFS092iu2abrz1waEFmrSdsPoN11zCiJp/Oaiu09HIxc/UkWymiPpSXmW3PGvsSgyUzYTtu/3pgylTgtag= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UF45Ne/s; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UF45Ne/s" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-35f2c9e23d3so45774f8f.0; Tue, 18 Jun 2024 10:48:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1718732933; x=1719337733; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sqMGpF9MafdhPPbTmf43XMwZfWHpPGtAVPqYCKy47u4=; b=UF45Ne/s5h2qfYWemwvMEhi7ir4NoP1R/CRIIOokFiDijH594X4wpnJ/MEDMzyh8Ek OuJ5zo8WTCIRXxnZ95oIbpn3QXGEuadfV9HAtfZrrsJMkIaXS2qeiPL5rKzGad/lRUnf Z9akP67h4ncZwWAbvANeus5dOKOmN/rGKpNFWyuhpoBnanVFJ67gN1n/IDpLubD6g2c5 nMTOzPTA5SrPYaDJMvLQGqFeQMss2+XgoI+k+4lz68W377OANPpRG9WdX4dAWiNuxbew 25KP4ZD3EENj/L05Dht2Abc1yuC/WdLTe8UCWF/5eCS2oGmOLfUKnitmvtu0W9COIReD JqMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718732933; x=1719337733; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sqMGpF9MafdhPPbTmf43XMwZfWHpPGtAVPqYCKy47u4=; b=MTR8Jxi7ytALza/cIXleFTNye02YJK51plqQenQQ/kYQUxfJd//jzQLXZjVe/E5A4i 6/yUdcIitPiyAebDQlSmRO41+RxY+BzL1Ifry+xBwpJlNTjetiGNn/OSKTkXV47O39kT V9k7TlEQZlF28a25ZJdM1awuRfwUO6AghLypJmTA3defv9qffoVB9ltiWDXl5q+aT1Vf LWqHn4o32JZAUxxf1WXckQUGTcnK8/u0sNsg+ND2JTvstA29rH5oFv2lERmUbnkjJNCi X0lq+SzBycEwK1YqWc0NVh8+9KKY6c0NDeOWKouIw961GbghldXPyV8xU3rgaVfro2Hs 4gdw== X-Forwarded-Encrypted: i=1; AJvYcCU31yX+zVJsjnQd6BKBcYFf2zZOzzA8k1LJAJhJHR/hrfM+FY/XHixagwY+EO6S9cgIt5b0/L4QtmFb/nKCanicju+WqwbuMX96q2MhsnhCc9NPfIs0bQi5LNSz0mgJx99+ZSSCdv+s7w== X-Gm-Message-State: AOJu0YxC8ypBymHgHGe4+G2dfYFkq/9F61IPZYhvv9U3DQ1m3Kc4OWr7 i7fWOW8ZwJdSCtMdxLfcL+OV5Rz40JgkAuZylAT7lJ9Kem2bKoxh X-Google-Smtp-Source: AGHT+IFU2BQNoe5ElKYcuGGZUhS+jx5+G1VSSadIGz9IqSPchK6rXimY4Od4/Mp6yqGMkMjGahQwmA== X-Received: by 2002:a05:6000:248:b0:363:337a:3e0 with SMTP id ffacd0b85a97d-363338946b5mr8521f8f.1.1718732932393; Tue, 18 Jun 2024 10:48:52 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:d6f0:b448:a40c:81a7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36289a4faeasm1253644f8f.95.2024.06.18.10.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:48:51 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 1/4] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide Date: Tue, 18 Jun 2024 18:48:28 +0100 Message-Id: <20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 32945d4c8dc0..bfaeeb00ac4a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -89,7 +89,7 @@ #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55) #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47) -#define PIN_CFG_MASK GENMASK_ULL(46, 0) +#define PIN_CFG_MASK GENMASK_ULL(31, 0) /* * m indicates the bitmap of supported pins, a is the register index @@ -1187,7 +1187,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off; - u64 cfg; + u32 cfg; int ret; u8 bit; @@ -1322,7 +1322,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, u64 *pin_data = pin->drv_data; unsigned int i, arg, index; u32 off, param; - u64 cfg; + u32 cfg; int ret; u8 bit; @@ -2755,9 +2755,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen for (u32 port = 0; port < nports; port++) { bool has_iolh, has_ien; - u64 cfg, caps; + u32 off, caps; u8 pincnt; - u32 off; + u64 cfg; cfg = pctrl->data->port_pin_configs[port]; off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); @@ -2801,7 +2801,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) { struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; - u64 caps; + u32 caps; u32 i; /* From patchwork Tue Jun 18 17:48:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 805437 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E88C3146A88; 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Tue, 18 Jun 2024 10:48:53 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:d6f0:b448:a40c:81a7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36289a4faeasm1253644f8f.95.2024.06.18.10.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:48:52 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/4] pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62) Date: Tue, 18 Jun 2024 18:48:29 +0100 Message-Id: <20240618174831.415583-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Shift the bit masks for `PIN_CFG_PIN_MAP_MASK` and `PIN_CFG_PIN_REG_MASK`, to accommodate `PIN_CFG_VARIABLE` using `BIT(62)`. Previously, these bit masks were placed higher up in the bit range, which did not leave room for `PIN_CFG_VARIABLE` at `BIT(62)`. By adjusting these masks, we ensure that `PIN_CFG_VARIABLE` can occupy `BIT(62)` without any conflicts. The updated masks are now: - `PIN_CFG_PIN_MAP_MASK`: `GENMASK_ULL(61, 54)` (was `GENMASK_ULL(62, 55)`) - `PIN_CFG_PIN_REG_MASK`: `GENMASK_ULL(53, 46)` (was `GENMASK_ULL(54, 47)`) Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index bfaeeb00ac4a..b79dd1ea2616 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -87,8 +87,8 @@ PIN_CFG_FILNUM | \ PIN_CFG_FILCLKSEL) -#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55) -#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47) +#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) +#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) #define PIN_CFG_MASK GENMASK_ULL(31, 0) /* From patchwork Tue Jun 18 17:48:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 805728 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BDE714A08F; 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Tue, 18 Jun 2024 10:48:54 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:d6f0:b448:a40c:81a7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36289a4faeasm1253644f8f.95.2024.06.18.10.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:48:53 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/4] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file Date: Tue, 18 Jun 2024 18:48:30 +0100 Message-Id: <20240618174831.415583-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Define `RZG2L_SINGLE_PIN` at the top of the file to clarify its use for dedicated pins for improved readability. While at it update the comment for `RZG2L_SINGLE_PIN_PACK` macro and place it just above the macro for clarity. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b79dd1ea2616..37a99d33400d 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -64,6 +64,8 @@ #define PIN_CFG_ELC BIT(20) #define PIN_CFG_IOLH_RZV2H BIT(21) +#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ + #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ @@ -105,15 +107,13 @@ */ #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) -/* - * BIT(63) indicates dedicated pin, p is the register index while - * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits - * (b * 8) and f is the pin configuration capabilities supported. - */ -#define RZG2L_SINGLE_PIN BIT_ULL(63) #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) - +/* + * p is the register index while referencing to SR/IEN/IOLH/FILxx + * registers, b is the register bits (b * 8) and f is the pin + * configuration capabilities supported. + */ #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ From patchwork Tue Jun 18 17:48:31 2024 Content-Type: text/plain; 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To better reflect its purpose, move the `PIN_CFG_VARIABLE` macro beside `RZG2L_SINGLE_PIN` and rename it to `RZG2L_CFG_VARIABLE`. Additionally, introduce new macros for packing variable port configurations: - `RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)`: Combines `RZG2L_CFG_VARIABLE` with `RZG2L_GPIO_PORT_PACK` to handle variable pin configurations for a packed port. - `RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)`: Combines `RZG2L_CFG_VARIABLE` with `RZG2L_GPIO_PORT_SPARSE_PACK` to handle variable pin configurations for a sparse port. Due to the above change the configuration macros have been reorganized as follows: - Shift the bit positions of `PIN_CFG_NOGPIO_INT`, `PIN_CFG_NOD`, `PIN_CFG_SMT`, `PIN_CFG_ELC`, and `PIN_CFG_IOLH_RZV2H` down by one to accommodate the removal of `PIN_CFG_VARIABLE`. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 29 +++++++++++++++---------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 37a99d33400d..9a67de960470 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -57,14 +57,14 @@ #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) #define PIN_CFG_OEN BIT(15) -#define PIN_CFG_VARIABLE BIT(16) -#define PIN_CFG_NOGPIO_INT BIT(17) -#define PIN_CFG_NOD BIT(18) /* N-ch Open Drain */ -#define PIN_CFG_SMT BIT(19) /* Schmitt-trigger input control */ -#define PIN_CFG_ELC BIT(20) -#define PIN_CFG_IOLH_RZV2H BIT(21) +#define PIN_CFG_NOGPIO_INT BIT(16) +#define PIN_CFG_NOD BIT(17) /* N-ch Open Drain */ +#define PIN_CFG_SMT BIT(18) /* Schmitt-trigger input control */ +#define PIN_CFG_ELC BIT(19) +#define PIN_CFG_IOLH_RZV2H BIT(20) #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ +#define RZG2L_CFG_VARIABLE BIT_ULL(62) /* Variable cfg for port pins */ #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -100,12 +100,17 @@ #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ FIELD_PREP_CONST(PIN_CFG_MASK, (f))) +#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \ + (RZG2L_CFG_VARIABLE | \ + RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0)) /* * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) +#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_CFG_VARIABLE | \ + RZG2L_GPIO_PORT_PACK(n, a, 0)) #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) @@ -371,7 +376,7 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port && FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin) - return (pincfg & ~PIN_CFG_VARIABLE) | FIELD_GET(PIN_CFG_MASK, cfg); + return (pincfg & ~RZG2L_CFG_VARIABLE) | FIELD_GET(PIN_CFG_MASK, cfg); } return 0; @@ -1835,13 +1840,13 @@ static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ - RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */ RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ - RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */ - RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */ + RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */ + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */ RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | PIN_CFG_NOGPIO_INT), /* P25 */ @@ -1913,7 +1918,7 @@ static const u64 r9a09g057_gpio_configs[] = { PIN_CFG_ELC), /* P8 */ RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */ RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */ - RZG2L_GPIO_PORT_PACK(6, 0x2b, PIN_CFG_VARIABLE), /* PB */ + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */ }; static const struct { @@ -2637,7 +2642,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) if (i && !(i % RZG2L_PINS_PER_PORT)) j++; pin_data[i] = pctrl->data->port_pin_configs[j]; - if (pin_data[i] & PIN_CFG_VARIABLE) + if (pin_data[i] & RZG2L_CFG_VARIABLE) pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, pin_data[i], j,