From patchwork Fri Oct 25 07:30:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 177671 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3282380ill; Fri, 25 Oct 2019 00:30:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqy1C3mQDERWmn61GZyaUOvvxEjMdi0HhZnudF+iwz36pJxp5AYew6xXA1MPHf29QGDifOMI X-Received: by 2002:a05:6402:68b:: with SMTP id f11mr2237328edy.173.1571988621272; Fri, 25 Oct 2019 00:30:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571988621; cv=none; d=google.com; s=arc-20160816; b=WScNVBgaEeHWsbKqc2qOgJSi7NWNsLv4wzNYZexBP6MjrPcIboFA4s7ic8xHC1Vqde 2aS6QFVaHCPcE4FnPu2KfxCA0d3+46KTLXPhwgLAY4I6SZPjYHUD78r6s7itLS4SZMqz moFCy5UDClj7xLNYRGIRQLEYYWcCf4uukWK0q8D5xc0nuQZyAcb7UVinqMXavKku4Eac nWbOFaaX0TuVPClcMHx0+g0fnV5pmUCcfWmesEDkmSzRPxJFlnWOLu3LnrhCZN4o2n/Z HbSByU1bzPfboMxaild4vBxie/9+Ue74X+AkoZjB00B2aQf9qMVP2nwJbAwMF/8fM8NQ vcBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3qESwgK0U+EAwQQL6PAX7MJ+aaVlzVEC8XOoAoFnNlo=; b=fEr/XZZrpAYPU1MPvRrfOGCseFousYkIx1Bp3/hNpeygBmRDNPjHX3KEb/HxZXBgfj 0AFxUWsDujIPV6aLxqoH1shVjDJ1z/Ne9PESL3lk/NQe0pR3k8GkTie8O0KBZRGPEJg4 /uVixuQFjSCopVgDtOPiymfbztiM2GRc2fB8sLmehkebKkxMyjx09HHZ1CzxSi2eA1I/ EXgG/a3GC0KK7Ww8E3/p/2DRbPzcomLLCOYCr2b/XorXbFEUi7BzeZR+D9ciyvDbSvFd cvHAsdiZAnyVmDKofLKewX+AgPUIQfKpBujIFze4mKcWQxNhK/SVETqBbXMmdUTrZt4T SFBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cAifdiSW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i22si685595ejr.267.2019.10.25.00.30.20; Fri, 25 Oct 2019 00:30:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cAifdiSW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437027AbfJYHaQ (ORCPT + 26 others); Fri, 25 Oct 2019 03:30:16 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:41786 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393149AbfJYHaD (ORCPT ); Fri, 25 Oct 2019 03:30:03 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9P7U13n083504; Fri, 25 Oct 2019 02:30:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571988601; bh=3qESwgK0U+EAwQQL6PAX7MJ+aaVlzVEC8XOoAoFnNlo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cAifdiSWMeUuttErMKa1KjLN/dVC0GXLvGV0SibL6sYDkZhMthGoSNTZk8WiXyNNk tUVDT8vDYnmfxXo2cQUxAYUEwWxggineOtpvg0CSQ3sOXUO2yhN43t9LW5kEs4tEMC VVA1pPos/fQ/T2V9kF354Md43jR/RxiB2+7Qpeu0= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9P7U0h9070088; Fri, 25 Oct 2019 02:30:00 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 25 Oct 2019 02:29:49 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 25 Oct 2019 02:29:59 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9P7Tr4H103329; Fri, 25 Oct 2019 02:29:58 -0500 From: Peter Ujfalusi To: , CC: , , , Subject: [PATCH v5 2/3] dt-bindings: dma: ti-edma: Document dma-channel-mask for EDMA Date: Fri, 25 Oct 2019 10:30:55 +0300 Message-ID: <20191025073056.25450-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191025073056.25450-1-peter.ujfalusi@ti.com> References: <20191025073056.25450-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Similarly to paRAM slots, channels can be used by other cores. The common dma-channel-mask property can be used for specifying the available channels. Signed-off-by: Peter Ujfalusi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/dma/ti-edma.txt | 8 ++++++++ 1 file changed, 8 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 4bbc94d829c8..0e1398f93aa2 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -42,6 +42,11 @@ Optional properties: - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by the driver, they are allocated to be used by for example the DSP. See example. +- dma-channel-mask: Mask of usable channels. + Single uint32 for EDMA with 32 channels, array of two uint32 for + EDMA with 64 channels. See example and + Documentation/devicetree/bindings/dma/dma-common.yaml + ------------------------------------------------------------------------------ eDMA3 Transfer Controller @@ -91,6 +96,9 @@ edma: edma@49000000 { ti,edma-memcpy-channels = <20 21>; /* The following PaRAM slots are reserved: 35-44 and 100-109 */ ti,edma-reserved-slot-ranges = <35 10>, <100 10>; + /* The following channels are reserved: 35-44 */ + dma-channel-mask = <0xffffffff /* Channel 0-31 */ + 0xffffe007>; /* Channel 32-63 */ }; edma_tptc0: tptc@49800000 { From patchwork Fri Oct 25 07:30:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 177670 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp3282160ill; Fri, 25 Oct 2019 00:30:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/rbWYg254sQtySBrgxmNnVd8xFYQ1MWr1PKdk5pHCsPHOuFXmr4/ciwq9ejwaPl24Nf+W X-Received: by 2002:a50:9a46:: with SMTP id o64mr2326115edb.191.1571988611768; Fri, 25 Oct 2019 00:30:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571988611; cv=none; d=google.com; s=arc-20160816; b=vZOg4NaO+0Uce7nmpAYcxXpTXn36LOLKaxU4IpzkhcO2IbmNmqdipP74+vYfCIzR7z JIY1dWFAUIdOgVc0EVbYNJ0n040nXhzZ0UkT3UBcTC11E8YWoH6Ip5pW4De0OSjy04oO cI/sk8tt4hZhIehaoWhMrdDoA2j/0MNqcmefQm0tigRBu8Stzmd/7Kx4zFS9TIY248uL kBwrd8K82liTlm7+wmK2EnJgZONo/OknB+uMnk/iVdceABBBqmjg+xdbKrpP7We4zRv5 EcMfkkqslzp5T8USCcH0kmvJmC/BM+4/LXnMgPGSuEa3nME6IBWZ3Nj3CPvh+Un1jd/+ BTuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+YAhSjmgPV3rufoVqLcPsk3D9DaDrrZFgGX+61W6VOQ=; b=Yg0BOU7foWJL8irli9ObJont9jgWrq4HPCiJ6ztF+g0MGk6bUWH3iGhu8Fygj4Mzot AOtwt0i2ItxYR5a7woFrZYroDrnue2BqwdqX0ay6zKbsxX1pajSrsMnu/t96bcccieuj aB96Br7pyXZ24mir6BFnN/vstay/MBmzLXf6UdCMBVC6XOJlmN6Qv3ua8Ew3/UE5OSPV 6RO0YsDGMqjsl95cHB9aqakyaAjBtloLkn0rxp5pCKqLxD7P2NVy6oU40ghpDwc5Hpsd V33CLmDoMlLPeUsS2XQcmdbvWh/3lEZsgAGFo3nosC/6pAGfA6sO4zujzQ3xLbAa3Msd qg+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=A2o0MeOa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Handle the generic dma-channel-mask property to mark channels in a bitmap which can not be used by Linux and convert the legacy rsv_chans if it is provided by platform_data. Signed-off-by: Peter Ujfalusi --- drivers/dma/ti/edma.c | 59 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 53 insertions(+), 6 deletions(-) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index 54fd981e3db5..0ecfc2e1d798 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -260,6 +260,13 @@ struct edma_cc { */ unsigned long *slot_inuse; + /* + * For tracking reserved channels used by DSP. + * If the bit is cleared, the channel is allocated to be used by DSP + * and Linux must not touch it. + */ + unsigned long *channels_mask; + struct dma_device dma_slave; struct dma_device *dma_memcpy; struct edma_chan *slave_chans; @@ -716,6 +723,12 @@ static int edma_alloc_channel(struct edma_chan *echan, struct edma_cc *ecc = echan->ecc; int channel = EDMA_CHAN_SLOT(echan->ch_num); + if (!test_bit(echan->ch_num, ecc->channels_mask)) { + dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n", + echan->ch_num); + return -EINVAL; + } + /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, EDMA_REG_ARRAY_INDEX(channel), EDMA_CHANNEL_BIT(channel)); @@ -2249,7 +2262,7 @@ static int edma_probe(struct platform_device *pdev) { struct edma_soc_info *info = pdev->dev.platform_data; s8 (*queue_priority_mapping)[2]; - const s16 (*rsv_slots)[2]; + const s16 (*reserved)[2]; int i, irq; char *irq_name; struct resource *mem; @@ -2329,15 +2342,32 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slot_inuse) return -ENOMEM; + ecc->channels_mask = devm_kcalloc(dev, + BITS_TO_LONGS(ecc->num_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->channels_mask) + return -ENOMEM; + + /* Mark all channels available initially */ + bitmap_fill(ecc->channels_mask, ecc->num_channels); + ecc->default_queue = info->default_queue; if (info->rsv) { /* Set the reserved slots in inuse list */ - rsv_slots = info->rsv->rsv_slots; - if (rsv_slots) { - for (i = 0; rsv_slots[i][0] != -1; i++) - bitmap_set(ecc->slot_inuse, rsv_slots[i][0], - rsv_slots[i][1]); + reserved = info->rsv->rsv_slots; + if (reserved) { + for (i = 0; reserved[i][0] != -1; i++) + bitmap_set(ecc->slot_inuse, reserved[i][0], + reserved[i][1]); + } + + /* Clear channels not usable for Linux */ + reserved = info->rsv->rsv_chans; + if (reserved) { + for (i = 0; reserved[i][0] != -1; i++) + bitmap_clear(ecc->channels_mask, reserved[i][0], + reserved[i][1]); } } @@ -2389,6 +2419,7 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->legacy_mode) { int lowest_priority = 0; + unsigned int array_max; struct of_phandle_args tc_args; ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, @@ -2410,6 +2441,18 @@ static int edma_probe(struct platform_device *pdev) info->default_queue = i; } } + + /* See if we have optional dma-channel-mask array */ + array_max = DIV_ROUND_UP(ecc->num_channels, BITS_PER_TYPE(u32)); + ret = of_property_read_variable_u32_array(node, + "dma-channel-mask", + (u32 *)ecc->channels_mask, + 1, array_max); + if (ret > 0 && ret != array_max) + dev_warn(dev, "dma-channel-mask is not complete.\n"); + else if (ret == -EOVERFLOW || ret == -ENODATA) + dev_warn(dev, + "dma-channel-mask is out of range or empty\n"); } /* Event queue priority mapping */ @@ -2427,6 +2470,10 @@ static int edma_probe(struct platform_device *pdev) edma_dma_init(ecc, legacy_mode); for (i = 0; i < ecc->num_channels; i++) { + /* Do not touch reserved channels */ + if (!test_bit(i, ecc->channels_mask)) + continue; + /* Assign all channels to the default queue */ edma_assign_channel_eventq(&ecc->slave_chans[i], info->default_queue);