From patchwork Wed Jun 26 12:37:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 807565 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55BF41822CB; Wed, 26 Jun 2024 12:38:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719405497; cv=none; b=jDOKhPPmcfyeHgcE2AoPIiDXhSgsAL4TxtK8ceENmlOc+4RHninVmxnwae7cRuQFy9K5GJo77i3Yuj/w3TbViJcgI1iKpYWQQIbiZh57L8J2TmhJI3TDcBuD69Py+EZ3cjmGOVJahMCj166SrSzHMyqwEMRDi346I/66dtA9jeE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719405497; c=relaxed/simple; bh=fCGQL2xdobFoV3TOvDGNRKzN4TKnBTgn6hF+FGAUroQ=; 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Wed, 26 Jun 2024 12:38:07 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:01 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:50 +0530 Subject: [PATCH RFC 2/7] arm64: dts: qcom: qcs6490-rb3gen2: Add qps615 node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-2-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Once the GPIO's are enabled, switch power will be on. Make all GPIO's as fixed regulators and inter link them so that enabling the regulator will enable power to the switch by enabling GPIO's. Enable i2c0 which is required to configure the switch. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a085ff5b5fb2..5b453896a6c9 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -511,6 +511,61 @@ vreg_bob_3p296: bob { regulator-max-microvolt = <3960000>; }; }; + + qps615_0p9_vreg: qps615-0p9-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_0p9_vreg"; + gpio = <&pm8350c_gpios 2 0>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-enable-ramp-delay = <4300>; + }; + + qps615_1p8_vreg: qps615-1p8-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_1p8_vreg"; + gpio = <&pm8350c_gpios 3 0>; + vin-supply = <&qps615_0p9_vreg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-enable-ramp-delay = <10000>; + }; + + qps615_rsex_vreg: qps615-rsex-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_rsex_vreg"; + gpio = <&pm8350c_gpios 1 0>; + vin-supply = <&qps615_1p8_vreg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-enable-ramp-delay = <10000>; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&pcie1 { + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x01 0xff>; + + qps615@0 { + compatible = "pci1179,0623"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + vdda-supply = <&qps615_rsex_vreg>; + switch-i2c-cntrl = <&i2c0>; + }; + }; }; &gcc { From patchwork Wed Jun 26 12:37:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 807564 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35A76181CF1; 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Wed, 26 Jun 2024 12:38:18 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QCcH35012411 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 12:38:17 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:12 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:52 +0530 Subject: [PATCH RFC 4/7] pci: Add new start_link() & stop_link function ops Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-4-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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As controller driver already enables link training, we need to stop the link training by using stop_link and enable them back after device is configured by using start_link. The stop_link() & start_link() be used to keep the link in D3cold & D0 before turning off the power of the device. Signed-off-by: Krishna chaitanya chundru --- include/linux/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index fb004fd4e889..3892ff7fd536 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -803,6 +803,8 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + int (*start_link)(struct pci_bus *bus); + int (*stop_link)(struct pci_bus *bus); }; /* From patchwork Wed Jun 26 12:37:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 807563 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1616181D1B; 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Wed, 26 Jun 2024 12:38:34 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QCcXlt003018 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 12:38:33 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:28 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:55 +0530 Subject: [PATCH RFC 7/7] pci: pwrctl: Add power control driver for qps615 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-7-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719405471; l=9545; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=GH1ZIcjQdgYwfp8z77xEv6s9RCk4oE8cin2OQE9YM+g=; b=igys+2Y9iLjg6uLmopQAM0IqONOCRY5LiHavrftNwD8fH69dFlEerEAREcFPVbhA32B3A4Rwv 4khExXq9KcxDKjZLwqLfE7f+deIm6Ras3XZQC3UN8iUFfWL/aIKeH5O X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JktbPvjJgskeN9Fb6quZ90PaFemNAWKB X-Proofpoint-GUID: JktbPvjJgskeN9Fb6quZ90PaFemNAWKB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260094 QPS615 switch needs to configured after powering on and before PCIe link was up. As the PCIe controller driver already enables the PCIe link training at the host side, stop the link training. Otherwise the moment we turn on the switch it will participate in the link training and link may come before switch is configured through i2c. The switch can be configured different ways like changing de-emphasis settings of the switch, disabling unused ports etc and these settings can vary from board to board, for that reason the sequence is taken from the firmware file which contains the address of the slave, to address and data to be written to the switch. The driver reads the firmware file and parses them to apply those configurations to the switch. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/pwrctl/Kconfig | 7 + drivers/pci/pwrctl/Makefile | 1 + drivers/pci/pwrctl/pci-pwrctl-qps615.c | 278 +++++++++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) diff --git a/drivers/pci/pwrctl/Kconfig b/drivers/pci/pwrctl/Kconfig index f1b824955d4b..a419b250006d 100644 --- a/drivers/pci/pwrctl/Kconfig +++ b/drivers/pci/pwrctl/Kconfig @@ -14,4 +14,11 @@ config PCI_PWRCTL_PWRSEQ Enable support for the PCI power control driver for device drivers using the Power Sequencing subsystem. +config PCI_PWRCTL_QPS615 + tristate "PCI Power Control driver for QPS615" + select PCI_PWRCTL + help + Enable support for the PCI power control driver for QPS615 and + configures it. + endmenu diff --git a/drivers/pci/pwrctl/Makefile b/drivers/pci/pwrctl/Makefile index d308aae4800c..ac563a70c023 100644 --- a/drivers/pci/pwrctl/Makefile +++ b/drivers/pci/pwrctl/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_PWRCTL) += pci-pwrctl-core.o pci-pwrctl-core-y := core.o obj-$(CONFIG_PCI_PWRCTL_PWRSEQ) += pci-pwrctl-pwrseq.o +obj-$(CONFIG_PCI_PWRCTL_QPS615) += pci-pwrctl-qps615.o diff --git a/drivers/pci/pwrctl/pci-pwrctl-qps615.c b/drivers/pci/pwrctl/pci-pwrctl-qps615.c new file mode 100644 index 000000000000..1f2caf5d7da2 --- /dev/null +++ b/drivers/pci/pwrctl/pci-pwrctl-qps615.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" + +struct qcom_qps615_pwrctl_i2c_setting { + u32 slv_addr; + u32 reg_addr; + u32 val; +}; + +struct qcom_qps615_pwrctl_ctx { + struct i2c_adapter *adapter; + struct pci_pwrctl pwrctl; + struct device_link *link; + struct regulator *vdd; +}; + +/* write 32-bit value to 24 bit register */ +static int qps615_switch_i2c_write(struct qcom_qps615_pwrctl_ctx *ctx, u32 slv_addr, u32 reg_addr, + u32 reg_val) +{ + struct i2c_msg msg; + u8 msg_buf[7]; + int ret; + + msg.addr = slv_addr; + msg.len = 7; + msg.flags = 0; + + /* Big Endian for reg addr */ + msg_buf[0] = (u8)(reg_addr >> 16); + msg_buf[1] = (u8)(reg_addr >> 8); + msg_buf[2] = (u8)reg_addr; + + /* Little Endian for reg val */ + msg_buf[3] = (u8)(reg_val); + msg_buf[4] = (u8)(reg_val >> 8); + msg_buf[5] = (u8)(reg_val >> 16); + msg_buf[6] = (u8)(reg_val >> 24); + + msg.buf = msg_buf; + ret = i2c_transfer(ctx->adapter, &msg, 1); + return ret == 1 ? 0 : ret; +} + +/* read 32 bit value from 24 bit reg addr */ +static int qps615_switch_i2c_read(struct qcom_qps615_pwrctl_ctx *ctx, u32 slv_addr, u32 reg_addr, + u32 *reg_val) +{ + u8 wr_data[3], rd_data[4] = {0}; + struct i2c_msg msg[2]; + int ret; + + msg[0].addr = slv_addr; + msg[0].len = 3; + msg[0].flags = 0; + + /* Big Endian for reg addr */ + wr_data[0] = (u8)(reg_addr >> 16); + wr_data[1] = (u8)(reg_addr >> 8); + wr_data[2] = (u8)reg_addr; + + msg[0].buf = wr_data; + + msg[1].addr = slv_addr; + msg[1].len = 4; + msg[1].flags = I2C_M_RD; + + msg[1].buf = rd_data; + + ret = i2c_transfer(ctx->adapter, &msg[0], 2); + if (ret != 2) + return ret; + + *reg_val = (rd_data[3] << 24) | (rd_data[2] << 16) | (rd_data[1] << 8) | rd_data[0]; + + return 0; +} + +static int qcom_qps615_pwrctl_init(struct qcom_qps615_pwrctl_ctx *ctx) +{ + struct device *dev = ctx->pwrctl.dev; + struct qcom_qps615_pwrctl_i2c_setting *set; + const struct firmware *fw; + const u8 *pos, *eof; + int ret; + u32 val; + + ret = request_firmware(&fw, "qcom/qps615.bin", dev); + if (ret < 0) { + dev_err(dev, "firmware loading failed with ret %d\n", ret); + return ret; + } + + if (!fw) { + ret = -EINVAL; + goto err; + } + + pos = fw->data; + eof = fw->data + fw->size; + + while (pos < (fw->data + fw->size)) { + set = (struct qcom_qps615_pwrctl_i2c_setting *)pos; + + ret = qps615_switch_i2c_write(ctx, set->slv_addr, set->reg_addr, set->val); + if (ret) { + dev_err(dev, + "I2c write failed for slv addr:%x at addr%x with val %x ret %d\n", + set->slv_addr, set->reg_addr, set->val, ret); + goto err; + } + + ret = qps615_switch_i2c_read(ctx, set->slv_addr, set->reg_addr, &val); + if (ret) { + dev_err(dev, "I2c read failed for slv addr:%x at addr%x ret %d\n", + set->slv_addr, set->reg_addr, ret); + goto err; + } + + if (set->val != val) { + dev_err(dev, + "I2c read's mismatch for slv:%x at addr%x exp%d got%d\n", + set->slv_addr, set->reg_addr, set->val, val); + goto err; + } + pos += sizeof(struct qcom_qps615_pwrctl_i2c_setting); + } + +err: + release_firmware(fw); + + return ret; +} + +static int qcom_qps615_power_on(struct qcom_qps615_pwrctl_ctx *ctx) +{ + int ret; + + ret = regulator_enable(ctx->vdd); + if (ret) { + dev_err(ctx->pwrctl.dev, "cannot enable vdda regulator\n"); + return ret; + } + + ret = qcom_qps615_pwrctl_init(ctx); + if (ret) + regulator_disable(ctx->vdd); + + return ret; +} + +static int qcom_qps615_power_off(struct qcom_qps615_pwrctl_ctx *ctx) +{ + return regulator_disable(ctx->vdd); +} + +static int qcom_qps615_pwrctl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct qcom_qps615_pwrctl_ctx *ctx; + struct device_node *adapter_node; + struct pci_host_bridge *bridge; + struct i2c_adapter *adapter; + struct pci_bus *bus; + + bus = pci_find_bus(of_get_pci_domain_nr(dev->parent->of_node), 0); + if (!bus) + return -ENODEV; + + bridge = pci_find_host_bridge(bus); + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + adapter_node = of_parse_phandle(node, "switch-i2c-cntrl", 0); + if (adapter_node) { + adapter = of_get_i2c_adapter_by_node(adapter_node); + __free(adapter_node); + if (!adapter) + return dev_err_probe(dev, -EPROBE_DEFER, + "failed to parse switch-i2c-cntrl\n"); + } + + ctx->pwrctl.dev = dev; + ctx->adapter = adapter; + ctx->vdd = devm_regulator_get(dev, "vdd"); + if (IS_ERR(ctx->vdd)) + return dev_err_probe(dev, PTR_ERR(ctx->vdd), + "failed to get vdd regulator\n"); + + ctx->link = device_link_add(&bridge->dev, dev, DL_FLAG_AUTOREMOVE_CONSUMER); + + platform_set_drvdata(pdev, ctx); + + bridge->ops->stop_link(bus); + qcom_qps615_power_on(ctx); + bridge->ops->start_link(bus); + + return devm_pci_pwrctl_device_set_ready(dev, &ctx->pwrctl); +} + +static const struct of_device_id qcom_qps615_pwrctl_of_match[] = { + { + .compatible = "pci1179,0623", + }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_qps615_pwrctl_of_match); + +static int pci_pwrctl_suspend_noirq(struct device *dev) +{ + struct pci_bus *bus = pci_find_bus(of_get_pci_domain_nr(dev->parent->of_node), 0); + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct qcom_qps615_pwrctl_ctx *ctx = dev_get_drvdata(dev); + + bridge->ops->stop_link(bus); + qcom_qps615_power_off(ctx); + + return 0; +} + +static int pci_pwrctl_resume_noirq(struct device *dev) +{ + struct pci_bus *bus = pci_find_bus(of_get_pci_domain_nr(dev->parent->of_node), 0); + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct qcom_qps615_pwrctl_ctx *ctx = dev_get_drvdata(dev); + + qcom_qps615_power_on(ctx); + bridge->ops->start_link(bus); + + return 0; +} + +static void qcom_qps615_pwrctl_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct qcom_qps615_pwrctl_ctx *ctx = dev_get_drvdata(dev); + + device_link_del(ctx->link); + pci_pwrctl_suspend_noirq(dev); +} + +static const struct dev_pm_ops pci_pwrctl_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(pci_pwrctl_suspend_noirq, pci_pwrctl_resume_noirq) +}; + +static struct platform_driver qcom_qps615_pwrctl_driver = { + .driver = { + .name = "pwrctl-qps615", + .of_match_table = qcom_qps615_pwrctl_of_match, + .pm = &pci_pwrctl_pm_ops, + }, + .probe = qcom_qps615_pwrctl_probe, + .remove_new = qcom_qps615_pwrctl_remove, +}; +module_platform_driver(qcom_qps615_pwrctl_driver); + +MODULE_AUTHOR("Krishna chaitanya chundru "); +MODULE_DESCRIPTION("Qualcomm QPS615 power control driver"); +MODULE_LICENSE("GPL");