From patchwork Wed Jun 26 10:39:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 807572 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 095DC17B405; Wed, 26 Jun 2024 10:40:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719398461; cv=none; b=jGSaJnGWlt24VTKHHHjxQPSe+ein8y1mEms1BxKwxx2Ontr251g/YYUlT158UywVk6v5RG5U6bxsPWcN2tsGJnhQAghH2vHYp10nGHq8k/NDY0nY4ZudegpsA6ubw4Toq7hlXXKJihTmJjyQXo3EbNppGF2u1zwvBoceCz7DT9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719398461; c=relaxed/simple; bh=l0R/P3u3PChoGz4XznbcCkh3+RlIqfpt7c5t/vs5eh4=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RN5C65tyPK/ooCYzIN2WQ6NxdSD901AQGigjc5i1KvLU4OvM4VXxmSZUjwXf3+JynLvuOHvuujUPFB++7iMEdUXK6GJroQzNuBN6suhFrO7sOQm20Vn434q4cXmxcDaRiQ9QR0SvQJLK5gdZ1s762JuIlVv5fwV91sOai7Y8AnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=TrO2v3cd; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="TrO2v3cd" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45Q3mmtY002267; Wed, 26 Jun 2024 10:40:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Lrg3yoV9Tnw7Ektyl29stD6ahGhkTypjQWuGqUa+ieA=; b=TrO2v3cd9zNE4/3V YS2TQKikrmQmumgx9Hz2qFsmP7JYLowjs9QeU7KxFtoqD4Wz0u5c+vjpX3tK/TCA uGrIHyxE4gReLN3V59RZvAFs0X9iJ0wbikYUuAf5Gux1lAXxgxS+ddHNHOWyBjcc um9DfI/A6uTlVkg/3cQJmj4Par74H1mEcgEVqn+jD9upKNnEmBSNOCvZg7oi/Jdr Fne8A2OnU5zq8cIHyqpIMTSWi7uSaBasQlj8BMg095yhCqG53jqUXV7Fktbdw+Sq Zbf0eXnuTeq6jeN/UXS1oYeo7S2QbvumX0Jneomfmg441HLwrDqCJ7Ae9reKYRGB CJdPEA== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 400bdq9154-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 10:40:50 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45QAem30029257 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Jun 2024 10:40:48 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 03:40:41 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/9] cpufreq: qcom-nvmem: Add genpd names to match_data_kryo Date: Wed, 26 Jun 2024 16:09:55 +0530 Message-ID: <20240626104002.420535-3-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240626104002.420535-1-quic_varada@quicinc.com> References: <20240626104002.420535-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: t3dW5VTpdlXMGJE2hMp-NIgFm9gco2ys X-Proofpoint-GUID: t3dW5VTpdlXMGJE2hMp-NIgFm9gco2ys X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_05,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 adultscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260081 This is used for tying up the cpu@N nodes with the power domains. Without this, 'cat /sys/kernel/debug/qcom_cpr3/thread0' crashes with NULL pointer access. Signed-off-by: Varadarajan Narayanan --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 939702dfa73f..5e6525c7788c 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -399,6 +399,7 @@ static const char *generic_genpd_names[] = { "perf", NULL }; static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, + .genpd_names = generic_genpd_names, }; static const struct qcom_cpufreq_match_data match_data_krait = { From patchwork Wed Jun 26 10:39:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 807571 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E67EC1662F2; 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Signed-off-by: Varadarajan Narayanan --- v2: Constrained nvmem-cells and the other variant. Removed unnecessary blank line. --- .../bindings/soc/qcom/qcom,cpr3.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml index acf2e294866b..f72addaa0ca2 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml @@ -24,6 +24,7 @@ properties: - const: qcom,cpr4 - items: - enum: + - qcom,ipq9574-cprh - qcom,msm8998-cprh - qcom,sdm630-cprh - const: qcom,cprh @@ -52,9 +53,11 @@ properties: nvmem-cells: description: Cells containing the fuse corners and revision data + minItems: 17 maxItems: 32 nvmem-cell-names: + minItems: 17 maxItems: 32 operating-points-v2: true @@ -74,6 +77,36 @@ required: additionalProperties: false allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-cprh + then: + properties: + nvmem-cells: + maxItems: 17 + nvmem-cell-names: + items: + - const: cpr_speed_bin + - const: cpr_fuse_revision + - const: cpr0_quotient1 + - const: cpr0_quotient2 + - const: cpr0_quotient3 + - const: cpr0_quotient4 + - const: cpr0_quotient_offset2 + - const: cpr0_quotient_offset3 + - const: cpr0_quotient_offset4 + - const: cpr0_init_voltage1 + - const: cpr0_init_voltage2 + - const: cpr0_init_voltage3 + - const: cpr0_init_voltage4 + - const: cpr0_ring_osc1 + - const: cpr0_ring_osc2 + - const: cpr0_ring_osc3 + - const: cpr0_ring_osc4 + - if: properties: compatible: @@ -82,6 +115,8 @@ allOf: - qcom,msm8998-cprh then: properties: + nvmem-cells: + minItems: 32 nvmem-cell-names: items: - const: cpr_speed_bin From patchwork Wed Jun 26 10:39:59 2024 Content-Type: text/plain; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan --- v2: Add GCC_RBCPR_CLK_SRC define. Not adding 'Acked-by: Krzysztof Kozlowski' as the file changed. --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 52123c5a09fa..4c65de04cb7b 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -220,4 +220,6 @@ #define GCC_PCIE1_PIPE_CLK 211 #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 +#define GCC_RBCPR_CLK_SRC 214 +#define GCC_RBCPR_CLK 215 #endif From patchwork Wed Jun 26 10:40:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 807569 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED0DF181CE5; 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Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v3: Fix patch author Included below information in cover letter v2: Fix Signed-off-by order Depends: [1] https://lore.kernel.org/lkml/20230217-topic-cpr3h-v14-0-9fd23241493d@linaro.org/T/ [2] https://github.com/quic-varada/cpr/commits/konrad/ --- drivers/pmdomain/qcom/cpr3.c | 137 +++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c index c28028be50d8..66c8a4bd9adc 100644 --- a/drivers/pmdomain/qcom/cpr3.c +++ b/drivers/pmdomain/qcom/cpr3.c @@ -2056,6 +2056,142 @@ static const struct cpr_acc_desc msm8998_cpr_acc_desc = { .cpr_desc = &msm8998_cpr_desc, }; +static const int ipq9574_silver_scaling_factor[][CPR3_RO_COUNT] = { + /* Fuse Corner 0 */ + { + 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949, + 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332 + }, + /* Fuse Corner 1 */ + { + 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949, + 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332 + }, + /* Fuse Corner 2 */ + { + 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949, + 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332 + }, + /* Fuse Corner 3 */ + { + 2383, 2112, 2250, 1502, 2269, 2055, 2046, 1949, + 2128, 1945, 2282, 2061, 2010, 2216, 2054, 2332 + }, +}; + +static const struct cpr_thread_desc ipq9574_thread_silver = { + .controller_id = 0, + .hw_tid = 0, + .ro_scaling_factor = ipq9574_silver_scaling_factor, + .sensor_range_start = 0, + .sensor_range_end = 6, + .init_voltage_step = 10000, + .init_voltage_width = 6, + .step_quot_init_min = 0, + .step_quot_init_max = 15, + .num_fuse_corners = 4, + .fuse_corner_data = (struct fuse_corner_data[]){ + /* fuse corner 0 */ + { + .ref_uV = 725000, + .max_uV = 725000, + .min_uV = 725000, + .range_uV = 0, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 4, + .max_quot_scale = 10, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 1 */ + { + .ref_uV = 862500, + .max_uV = 862500, + .min_uV = 725000, + .range_uV = 0, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 500, + .max_quot_scale = 800, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + /* fuse corner 2 */ + { + .ref_uV = 987500, + .max_uV = 987500, + .min_uV = 787500, + .range_uV = 0, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 280, + .max_quot_scale = 650, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + + }, + /* fuse corner 3 */ + { + .ref_uV = 1062500, + .max_uV = 1062500, + .min_uV = 850000, + .range_uV = 0, + .volt_cloop_adjust = 0, + .volt_oloop_adjust = 0, + .max_volt_scale = 430, + .max_quot_scale = 800, + .quot_offset = 0, + .quot_scale = 1, + .quot_adjust = 0, + .quot_offset_scale = 5, + .quot_offset_adjust = 0, + }, + }, +}; + +static const struct cpr_desc ipq9574_cpr_desc = { + .cpr_type = CTRL_TYPE_CPR4, + .num_threads = 1, + .apm_threshold = 850000, + .apm_crossover = 880000, + .apm_hysteresis = 0, + .cpr_base_voltage = 700000, + .cpr_max_voltage = 1100000, + .timer_delay_us = 5000, + .timer_cons_up = 0, + .timer_cons_down = 0, + .up_threshold = 2, + .down_threshold = 2, + .idle_clocks = 15, + .count_mode = CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN, + .count_repeat = 1, + .gcnt_us = 1, + .vreg_step_fixed = 12500, + .vreg_step_up_limit = 1, + .vreg_step_down_limit = 1, + .vdd_settle_time_us = 34, + .corner_settle_time_us = 6, + .reduce_to_corner_uV = true, + .hw_closed_loop_en = false, + .threads = (const struct cpr_thread_desc *[]) { + &ipq9574_thread_silver, + }, +}; + +static const struct cpr_acc_desc ipq9574_cpr_acc_desc = { + .cpr_desc = &ipq9574_cpr_desc, +}; + static const int sdm630_gold_scaling_factor[][CPR3_RO_COUNT] = { /* Same RO factors for all fuse corners */ { @@ -2828,6 +2964,7 @@ static void cpr_remove(struct platform_device *pdev) } static const struct of_device_id cpr3_match_table[] = { + { .compatible = "qcom,ipq9574-cprh", .data = &ipq9574_cpr_acc_desc }, { .compatible = "qcom,msm8998-cprh", .data = &msm8998_cpr_acc_desc }, { .compatible = "qcom,sdm630-cprh", .data = &sdm630_cpr_acc_desc }, { }