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Signed-off-by: Suresh Vankadara Signed-off-by: Trishansh Bhardwaj Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 182 +++++++++++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f8256d5a8f6b..9ac251fec262 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4415,6 +4415,188 @@ cci1_i2c1: i2c-bus@1 { }; }; + camss: camss@acaf000 { + compatible = "qcom,sc7280-camss"; + + reg = <0x0 0x0acaf000 0x0 0x5200>, + <0x0 0x0acb6000 0x0 0x5200>, + <0x0 0x0acbd000 0x0 0x5200>, + <0x0 0x0acc4000 0x0 0x5000>, + <0x0 0x0accb000 0x0 0x5000>, + <0x0 0x0ace0000 0x0 0x2000>, + <0x0 0x0ace2000 0x0 0x2000>, + <0x0 0x0ace4000 0x0 0x2000>, + <0x0 0x0ace6000 0x0 0x2000>, + <0x0 0x0ace8000 0x0 0x2000>; + + reg-names = "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK>; + + clock-names = "cam_hf_axi", + "slow_ahb_src", + "cpas_ahb", + "camnoc_axi_src", + "camnoc_axi", + "csiphy0", + "csiphy0_timer", + "csiphy0_timer_src", + "csiphy1", + "csiphy1_timer", + "csiphy1_timer_src", + "csiphy2", + "csiphy2_timer", + "csiphy2_timer_src", + "csiphy3", + "csiphy3_timer", + "csiphy3_timer_src", + "csiphy4", + "csiphy4_timer", + "csiphy4_timer_src", + "vfe0_csid", + "vfe0_cphy_rx", + "vfe0", + "vfe0_axi", + "csiphy_rx_src", + "vfe1_csid", + "vfe1_cphy_rx", + "vfe1", + "vfe1_axi", + "vfe2_csid", + "vfe2_cphy_rx", + "vfe2", + "vfe2_axi", + "vfe0_lite_csid", + "vfe0_lite_cphy_rx", + "vfe0_lite", + "vfe1_lite_csid", + "vfe1_lite_cphy_rx", + "vfe1_lite", + "vfe_lite0", + "vfe_lite1"; + + iommus = <&apps_smmu 0x800 0x4e0>; + + interconnect-names = "cam_ahb", + "cam_hf_0"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc7280-camcc"; reg = <0 0x0ad00000 0 0x10000>; From patchwork Fri Jun 28 18:32:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikram Sharma X-Patchwork-Id: 808321 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ECC11CE095; Fri, 28 Jun 2024 18:33:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719599608; cv=none; b=b0har60lTthKivqVq80AoGr/eCGGtSPxGrz4N/XYDvSNow80bw/UFirX5HAVIU6gqo7pope9LmsjLABL9hLgM1bdn9qGkGd1A1M9HI0mGHjhvm8DoFbFI2yUeT0RspkPMgXAZjMZzn7giECjmpr/s5g429hajLPEWksQn7WHhM0= ARC-Message-Signature: i=1; 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Signed-off-by: Hariram Purushothaman Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 67 ++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index c4cde4328e3d..237231600dca 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -513,6 +513,73 @@ vreg_bob_3p296: bob { }; }; +&camcc { + status = "okay"; +}; + +&camss { + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* The port index denotes CSIPHY id i.e. csiphy2 */ + port@3 { + reg = <3>; + csiphy3_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx412_ep>; + }; + }; + }; +}; + +&cci0 { + status = "okay"; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera@1a { + /* + * rb3gen2 ships with an imx577. qcom treats imx412 + * and imx577 the same way. Absent better data do the same here. + */ + compatible = "sony,imx412"; + reg = <0x1a>; + + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&cam2_default>; + pinctrl-1 = <&cam2_suspend>; + + clocks = <&camcc CAM_CC_MCLK3_CLK>, + <&camcc CAM_CC_MCLK2_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>, + <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates = <24000000>, + <24000000>; + + dovdd-supply = <&vreg_l18b_1p8>; + /* avdd-supply = <&vdc_5v>; + * dvdd-supply = <&vdc_5v>; + */ + + port { + imx412_ep: endpoint { + clock-lanes = <7>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + &gcc { protected-clocks = , , From patchwork Fri Jun 28 18:32:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikram Sharma X-Patchwork-Id: 808320 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA8231CCCB6; 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Fri, 28 Jun 2024 18:33:31 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45SIXUPL019524 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Jun 2024 18:33:30 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 28 Jun 2024 11:33:24 -0700 From: Vikram Sharma Date: Sat, 29 Jun 2024 00:02:40 +0530 Subject: [PATCH 6/6] media: qcom: camss: support for camss driver for sc7280 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240629-camss_first_post_linux_next-v1-6-bc798edabc3a@quicinc.com> References: <20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com> In-Reply-To: <20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com> To: Robert Foss , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kapatrala Syed , Hariram Purushothaman , , Bjorn Andersson , Konrad Dybcio , "Loic Poulain" , Andi Shyti CC: , , , , , Vikram Sharma , Suresh Vankadara , Trishansh Bhardwaj X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719599567; l=15463; i=quic_vikramsa@quicinc.com; s=20240628; h=from:subject:message-id; bh=WWSzn7kQwaw4Vq/+yyLH32fQovF5f8e9Is6rdSr3CgU=; b=zvo8mk6vzs6OgLZYQhUx+iGANtphi9FdybQHH28Tgsq1Np2dKYb7ETYVmDzxtArBTGrM/RFoM tF7IdZ7lLnIBTgqJipn1ut2l1BcEB95EX2qtmOPXa8UYlQXnNiGEiiq X-Developer-Key: i=quic_vikramsa@quicinc.com; a=ed25519; pk=vQBkwZr1Hv+VXogAyTAu7AEx8/6bvkOmgrzYFbNGCDI= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LHi2qpRUA4erHEKF8yEJ-3MeFulWwD1y X-Proofpoint-ORIG-GUID: LHi2qpRUA4erHEKF8yEJ-3MeFulWwD1y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-28_14,2024-06-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406280138 From: Suresh Vankadara This change adds support for camss driver for sc7280 soc. Signed-off-by: Suresh Vankadara Signed-off-by: Trishansh Bhardwaj Signed-off-by: Vikram Sharma --- drivers/media/platform/qcom/camss/camss-csid.c | 16 +- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 + drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 340 +++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 2 + 5 files changed, 359 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 858db5d4ca75..2c622233da6f 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -28,6 +28,7 @@ /* offset of CSID registers in VFE region for VFE 480 */ #define VFE_480_CSID_OFFSET 0x1200 #define VFE_480_LITE_CSID_OFFSET 0x200 +#define VFE_165_CSID_OFFSET 0x4000 #define MSM_CSID_NAME "msm_csid" @@ -1028,8 +1029,8 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, csid->res->hw_ops->subdev_init(csid); /* Memory */ - - if (camss->res->version == CAMSS_8250) { + switch (camss->res->version) { + case CAMSS_8250: /* for titan 480, CSID registers are inside the VFE region, * between the VFE "top" and "bus" registers. this requires * VFE to be initialized before CSID @@ -1040,10 +1041,19 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, else csid->base = csid->res->parent_dev_ops->get_base_address(camss, id) + VFE_480_CSID_OFFSET; - } else { + break; + case CAMSS_7280: + /* for titan 165, CSID registers are inside the VFE region, + * between the VFE "top" and "bus" registers. this requires + * VFE to be initialized before CSID + */ + csid->base = camss->vfe[id].base + VFE_165_CSID_OFFSET; + break; + default: csid->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]); if (IS_ERR(csid->base)) return PTR_ERR(csid->base); + break; } /* Interrupt */ diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index df7e93a5a4f6..c7e507420732 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -510,6 +510,7 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, array_size = ARRAY_SIZE(lane_regs_sdm845[0]); break; case CAMSS_8250: + case CAMSS_7280: r = &lane_regs_sm8250[0][0]; array_size = ARRAY_SIZE(lane_regs_sm8250[0]); break; @@ -560,6 +561,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_7280: ret = true; break; } diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 83c5a36d071f..757e872b8eb8 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -338,6 +338,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_7280: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -1695,6 +1696,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_7280: ret = 16; break; default: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 1f1f44f6fbb2..2b840e2aeb51 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1480,6 +1480,281 @@ static const struct resources_icc icc_res_sc8280xp[] = { }, }; +static const struct camss_subdev_resources csiphy_res_7280[] = { + /* CSIPHY0 */ + { + .regulators = {}, + .clock = { "csiphy0", "csiphy0_timer", "csiphy0_timer_src"}, + .clock_rate = { { 300000000 }, + { 300000000 }, + { 300000000 }}, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0 + } + }, + /* CSIPHY1 */ + { + .regulators = {}, + .clock = { "csiphy1", "csiphy1_timer", "csiphy1_timer_src"}, + .clock_rate = { { 300000000 }, + { 300000000 }, + { 300000000 }}, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0 + } + }, + /* CSIPHY2 */ + { + .regulators = {}, + .clock = { "csiphy2", "csiphy2_timer", "csiphy2_timer_src"}, + .clock_rate = { { 300000000 }, + { 300000000 }, + { 300000000 }}, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0 + } + }, + /* CSIPHY3 */ + { + .regulators = {}, + .clock = { "csiphy3", "csiphy3_timer", "csiphy3_timer_src"}, + .clock_rate = { { 300000000 }, + { 300000000 }, + { 300000000 }}, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0 + } + }, + /* CSIPHY4 */ + { + .regulators = {}, + .clock = { "csiphy4", "csiphy4_timer", "csiphy4_timer_src"}, + .clock_rate = { { 300000000 }, + { 300000000 }, + { 300000000 }}, + .reg = { "csiphy4" }, + .interrupt = { "csiphy4" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0 + } + }, +}; + +static const struct camss_subdev_resources csid_res_7280[] = { + /* CSID0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi", "csiphy_rx_src"}, + .clock_rate = { { 300000000, 0, 380000000, 150000000, 380000000}, + { 400000000, 0, 510000000, 140000000, 510000000}, + { 400000000, 0, 637000000, 320000000, 637000000}, + { 400000000, 0, 760000000, 400000000, 760000000} }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .csid = { + .is_lite = false, + .hw_ops = &csid_ops_gen2, + .formats = &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_axi", "csiphy_rx_src"}, + .clock_rate = { { 300000000, 0, 380000000, 300000000, 380000000}, + { 400000000, 0, 510000000, 400000000, 510000000}, + { 400000000, 0, 637000000, 400000000, 637000000}, + { 400000000, 0, 760000000, 400000000, 760000000} }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .csid = { + .is_lite = false, + .hw_ops = &csid_ops_gen2, + .formats = &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2", "vfe2_axi", "csiphy_rx_src"}, + .clock_rate = { { 300000000, 0, 380000000, 300000000, 380000000}, + { 400000000, 0, 510000000, 400000000, 510000000}, + { 400000000, 0, 637000000, 400000000, 637000000}, + { 400000000, 0, 760000000, 400000000, 760000000} }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .csid = { + .is_lite = false, + .hw_ops = &csid_ops_gen2, + .formats = &csid_formats_gen2 + } + }, + /* CSID3 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe0_lite_csid", "vfe0_lite_cphy_rx", "vfe0_lite", "csiphy_rx_src"}, + .clock_rate = { { 300000000, 0, 320000000, 300000000}, + { 400000000, 0, 400000000, 400000000}, + { 400000000, 0, 480000000, 400000000}, + { 400000000, 0, 600000000, 400000000} }, + .reg = { "csid_lite0" }, + .interrupt = { "csid_lite0" }, + .csid = { + .is_lite = true, + .hw_ops = &csid_ops_gen2, + .formats = &csid_formats_gen2 + } + }, + /* CSID4 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "vfe1_lite_csid", "vfe1_lite_cphy_rx", "vfe1_lite", "csiphy_rx_src"}, + .clock_rate = { { 300000000, 0, 320000000, 300000000}, + { 400000000, 0, 400000000, 400000000}, + { 400000000, 0, 480000000, 400000000}, + { 400000000, 0, 600000000, 400000000} }, + .reg = { "csid_lite1" }, + .interrupt = { "csid_lite1" }, + .csid = { + .is_lite = true, + .hw_ops = &csid_ops_gen2, + .formats = &csid_formats_gen2 + } + }, +}; + +static const struct camss_subdev_resources vfe_res_7280[] = { + /* VFE0 */ + { + .regulators = {}, + .clock = { "vfe0", "vfe0_axi", "cam_hf_axi", + "slow_ahb_src", "cpas_ahb", "camnoc_axi"}, + .clock_rate = { + { 380000000, 0, 0, 80000000, 0, 150000000}, + { 380000000, 0, 0, 80000000, 0, 150000000}, + { 510000000, 0, 0, 80000000, 0, 240000000}, + { 637000000, 0, 0, 80000000, 0, 320000000}, + { 760000000, 0, 0, 80000000, 0, 400000000}, + { 760000000, 0, 0, 80000000, 0, 480000000} }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE1 */ + { + .regulators = {}, + .clock = { "vfe1", "vfe1_axi", "cam_hf_axi", + "slow_ahb_src", "cpas_ahb", "camnoc_axi"}, + .clock_rate = { + { 380000000, 0, 0, 80000000, 0, 150000000}, + { 380000000, 0, 0, 80000000, 0, 150000000 }, + { 510000000, 0, 0, 80000000, 0, 240000000 }, + { 637000000, 0, 0, 80000000, 0, 320000000 }, + { 760000000, 0, 0, 80000000, 0, 400000000 }, + { 760000000, 0, 0, 80000000, 0, 480000000 } }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE2 */ + { + .regulators = {}, + .clock = { "vfe2", "vfe2_axi", "cam_hf_axi", + "slow_ahb_src", "cpas_ahb", "camnoc_axi"}, + .clock_rate = { + { 380000000, 0, 0, 80000000, 0, 150000000}, + { 380000000, 0, 0, 80000000, 0, 150000000, }, + { 510000000, 0, 0, 80000000, 0, 240000000, }, + { 637000000, 0, 0, 80000000, 0, 320000000, }, + { 760000000, 0, 0, 80000000, 0, 400000000, }, + { 760000000, 0, 0, 80000000, 0, 480000000, } }, + .reg = { "vfe2" }, + .interrupt = { "vfe2" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE3 (lite) */ + { + .clock = { "vfe_lite0", "cam_hf_axi", "slow_ahb_src", "cpas_ahb", "camnoc_axi"}, + .clock_rate = { + { 320000000, 0, 80000000, 0, 150000000 }, + { 320000000, 0, 80000000, 0, 150000000 }, + { 400000000, 0, 80000000, 0, 240000000 }, + { 480000000, 0, 80000000, 0, 320000000 }, + { 600000000, 0, 80000000, 0, 400000000 }, + { 600000000, 0, 80000000, 0, 480000000 } }, + .regulators = {}, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE4 (lite) */ + { + .clock = { "vfe_lite1", "cam_hf_axi", "slow_ahb_src", "cpas_ahb", "camnoc_axi"}, + .clock_rate = { + { 320000000, 0, 80000000, 0, 150000000 }, + { 320000000, 0, 80000000, 0, 150000000 }, + { 400000000, 0, 80000000, 0, 240000000 }, + { 480000000, 0, 80000000, 0, 320000000 }, + { 600000000, 0, 80000000, 0, 400000000 }, + { 600000000, 0, 80000000, 0, 480000000 } }, + .regulators = {}, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, +}; + +static const struct resources_icc icc_res_sc7280[] = { + { + .name = "cam_ahb", + .icc_bw_tbl.avg = 38400, + .icc_bw_tbl.peak = 76800, + }, + { + .name = "cam_hf_0", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -1824,6 +2099,57 @@ static int camss_init_subdevices(struct camss *camss) return 0; } +/* + * camss_link_entities_v2 - Register subdev nodes and create links + * @camss: CAMSS device + * + * Return 0 on success or a negative error code on failure + */ +static int camss_link_entities_v2(struct camss *camss) +{ + int i, j; + int ret; + + for (i = 0; i < camss->res->csiphy_num; i++) { + for (j = 0; j < camss->res->csid_num; j++) { + ret = media_create_pad_link(&camss->csiphy[i].subdev.entity, + MSM_CSIPHY_PAD_SRC, + &camss->csid[j].subdev.entity, + MSM_CSID_PAD_SINK, + 0); + if (ret < 0) { + dev_err(camss->dev, + "Failed to link %s->%s entities: %d\n", + camss->csiphy[i].subdev.entity.name, + camss->csid[j].subdev.entity.name, + ret); + return ret; + } + } + } + + for (i = 0; i < camss->res->csid_num; i++) + for (j = 0; j < camss->vfe[i].res->line_num; j++) { + struct v4l2_subdev *csid = &camss->csid[i].subdev; + struct v4l2_subdev *vfe = &camss->vfe[i].line[j].subdev; + + ret = media_create_pad_link(&csid->entity, + MSM_CSID_PAD_FIRST_SRC + j, + &vfe->entity, + MSM_VFE_PAD_SINK, + 0); + if (ret < 0) { + dev_err(camss->dev, + "Failed to link %s->%s entities: %d\n", + csid->entity.name, + vfe->entity.name, + ret); + return ret; + } + } + return 0; +} + /* * camss_link_entities - Register subdev nodes and create links * @camss: CAMSS device @@ -2440,12 +2766,26 @@ static const struct camss_resources sc8280xp_resources = { .link_entities = camss_link_entities }; +static const struct camss_resources sc7280_resources = { + .version = CAMSS_7280, + .csiphy_res = csiphy_res_7280, + .csid_res = csid_res_7280, + .vfe_res = vfe_res_7280, + .icc_res = icc_res_sc7280, + .icc_path_num = ARRAY_SIZE(icc_res_sc7280), + .csiphy_num = ARRAY_SIZE(csiphy_res_7280), + .csid_num = ARRAY_SIZE(csid_res_7280), + .vfe_num = 3, + .link_entities = camss_link_entities_v2 +}; + static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, + { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources }, { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { } }; diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 73c47c07fc30..29dbf93ce9c5 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -79,11 +79,13 @@ enum camss_version { CAMSS_845, CAMSS_8250, CAMSS_8280XP, + CAMSS_7280, }; enum icc_count { ICC_DEFAULT_COUNT = 0, ICC_SM8250_COUNT = 4, + ICC_SM7280_COUNT = 4, }; struct camss_resources {