From patchwork Fri Jun 28 08:01:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrei Simion X-Patchwork-Id: 808430 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC48B47F59; Fri, 28 Jun 2024 08:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719561743; cv=none; b=EBcSHT3AqNhnh2s2w/6BwhjfaGkmiZAdZ4N5hH3ARuALrGYO1yakyjJdHeyIfbKhIwF419TFjfBA6/7rjlepJPfpQghzknPrBpdBFTsqMfjS3VaAfWjrsZa7ECjNMp7E6d3apjaO3VBYgUAj44Xq4KO6xvyDAzs/GXPnxAJZUWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719561743; c=relaxed/simple; bh=ccI8MYfzyEnNqGdmvND7NjZ84ouSXCcAOMy0xM3NMC0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fG8fMz4vvAEcgkcxMcDnmK9RcsI4Zw1vgh13a0mzlhmMtzu2+mMYNP5YD+z2EkZlFTZnP7XpeCcCp3DIhq0yoy7gymXgaRhwFsKQKr/G0ftjcsTkt1iSO+auhVDRoxwLC59pl/7R3XcxBN0A4E4OPB8tqxXsAzaAZoS26gz9RlE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=nj6L//4Q; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="nj6L//4Q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1719561742; x=1751097742; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ccI8MYfzyEnNqGdmvND7NjZ84ouSXCcAOMy0xM3NMC0=; b=nj6L//4QZSz4/oFpwKIFjgqzj7SV5VcOHbzY8Ys0m+U3PCVI7ZctEsqW VsxvsZhxIxIoqppqZ0QGB5/g03D9d69Ul5SsYOMDDkKoQrINf1u6v903z o6ierphrbjyYzAKDf3l3H5BQxqJUZlA/FDJzVOs8i+Cdu/hGiKXO58AbD EP9Lm6EeuX0oPygemyQP7ebSAo92CyAI1W4ixZbnu8ocdHu+vuCbVmLme kQZqRxJbYl9o0jsIoymHK1/MJO/UbCRNBklw97YsGvbwIxO9CxJM52e4a uQg9nSZ/HJPL8Pj1mw6sJDSztHAhOuqnzficaKl880alktJCZ4deCVTe9 w==; X-CSE-ConnectionGUID: yumzE5LRQZWNGcwzrru4aA== X-CSE-MsgGUID: zs6JdCT+TdeFXl7gPhaAIQ== X-IronPort-AV: E=Sophos;i="6.09,168,1716274800"; d="scan'208";a="28620938" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 01:02:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 01:02:05 -0700 Received: from ROB-ULT-M76677.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 01:02:02 -0700 From: Andrei Simion To: , , , , , , , , CC: , , , , Claudiu Beznea , Andrei Simion Subject: [PATCH v3 1/3] eeprom: at24: avoid adjusting offset for 24AA025E{48, 64} Date: Fri, 28 Jun 2024 11:01:44 +0300 Message-ID: <20240628080146.49545-2-andrei.simion@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628080146.49545-1-andrei.simion@microchip.com> References: <20240628080146.49545-1-andrei.simion@microchip.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The EEPROMs could be used only for MAC storage. In this case the EEPROM areas where MACs resides could be modeled as NVMEM cells (directly via DT bindings) such that the already available networking infrastructure to read properly the MAC addresses (via of_get_mac_address()). The previously available compatibles needs the offset adjustment probably for compatibility w/ old DT bindings. Add "microchip,24aa025e48", "microchip,24aa025e64" compatible for the usage w/ 24AA025E{48, 64} type of EEPROMs where "24aa025e48" stands for EUI-48 address and "24aa025e64" stands for EUI-64 address. Signed-off-by: Claudiu Beznea [andrei.simion@microchip.com: Add extended macros to initialize the structure with explicit value to adjusting offset. Add extra description for the commit message.] Signed-off-by: Andrei Simion --- v2 -> v3: - add specific compatible names according with https://ww1.microchip.com/downloads/en/DeviceDoc/24AA02E48-24AA025E48-24AA02E64-24AA025E64-Data-Sheet-20002124H.pdf - add extended macros to initialize the structure with explicit value for adjoff - drop co-developed-by to maintain the commit history (chronological order of modifications) v1 -> v2: - no change --- drivers/misc/eeprom/at24.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c index 4bd4f32bcdab..e2ac08f656cf 100644 --- a/drivers/misc/eeprom/at24.c +++ b/drivers/misc/eeprom/at24.c @@ -121,20 +121,29 @@ struct at24_chip_data { u32 byte_len; u8 flags; u8 bank_addr_shift; + u8 adjoff; void (*read_post)(unsigned int off, char *buf, size_t count); }; -#define AT24_CHIP_DATA(_name, _len, _flags) \ +#define AT24_CHIP_DATA_AO(_name, _len, _flags, _ao) \ static const struct at24_chip_data _name = { \ .byte_len = _len, .flags = _flags, \ + .adjoff = _ao \ } -#define AT24_CHIP_DATA_CB(_name, _len, _flags, _read_post) \ +#define AT24_CHIP_DATA(_name, _len, _flags) \ + AT24_CHIP_DATA_AO(_name, _len, _flags, 0) + +#define AT24_CHIP_DATA_CB_AO(_name, _len, _flags, _ao, _read_post) \ static const struct at24_chip_data _name = { \ .byte_len = _len, .flags = _flags, \ + .adjoff = _ao, \ .read_post = _read_post, \ } +#define AT24_CHIP_DATA_CB(_name, _len, _flags, _read_post) \ + AT24_CHIP_DATA_CB_AO(_name, _len, _flags, 0, _read_post) + #define AT24_CHIP_DATA_BS(_name, _len, _flags, _bank_addr_shift) \ static const struct at24_chip_data _name = { \ .byte_len = _len, .flags = _flags, \ @@ -170,9 +179,13 @@ AT24_CHIP_DATA(at24_data_24cs01, 16, AT24_CHIP_DATA(at24_data_24c02, 2048 / 8, 0); AT24_CHIP_DATA(at24_data_24cs02, 16, AT24_FLAG_SERIAL | AT24_FLAG_READONLY); -AT24_CHIP_DATA(at24_data_24mac402, 48 / 8, +AT24_CHIP_DATA_AO(at24_data_24mac402, 48 / 8, + AT24_FLAG_MAC | AT24_FLAG_READONLY, 1); +AT24_CHIP_DATA_AO(at24_data_24mac602, 64 / 8, + AT24_FLAG_MAC | AT24_FLAG_READONLY, 1); +AT24_CHIP_DATA(at24_data_24aa025e48, 48 / 8, AT24_FLAG_MAC | AT24_FLAG_READONLY); -AT24_CHIP_DATA(at24_data_24mac602, 64 / 8, +AT24_CHIP_DATA(at24_data_24aa025e64, 64 / 8, AT24_FLAG_MAC | AT24_FLAG_READONLY); /* spd is a 24c02 in memory DIMMs */ AT24_CHIP_DATA(at24_data_spd, 2048 / 8, @@ -218,6 +231,8 @@ static const struct i2c_device_id at24_ids[] = { { "24cs02", (kernel_ulong_t)&at24_data_24cs02 }, { "24mac402", (kernel_ulong_t)&at24_data_24mac402 }, { "24mac602", (kernel_ulong_t)&at24_data_24mac602 }, + { "24aa025e48", (kernel_ulong_t)&at24_data_24aa025e48 }, + { "24aa025e64", (kernel_ulong_t)&at24_data_24aa025e64 }, { "spd", (kernel_ulong_t)&at24_data_spd }, { "24c02-vaio", (kernel_ulong_t)&at24_data_24c02_vaio }, { "24c04", (kernel_ulong_t)&at24_data_24c04 }, @@ -270,6 +285,8 @@ static const struct of_device_id __maybe_unused at24_of_match[] = { { .compatible = "atmel,24c1024", .data = &at24_data_24c1024 }, { .compatible = "atmel,24c1025", .data = &at24_data_24c1025 }, { .compatible = "atmel,24c2048", .data = &at24_data_24c2048 }, + { .compatible = "microchip,24aa025e48", .data = &at24_data_24aa025e48 }, + { .compatible = "microchip,24aa025e64", .data = &at24_data_24aa025e64 }, { /* END OF LIST */ }, }; MODULE_DEVICE_TABLE(of, at24_of_match); @@ -690,7 +707,8 @@ static int at24_probe(struct i2c_client *client) at24->read_post = cdata->read_post; at24->bank_addr_shift = cdata->bank_addr_shift; at24->num_addresses = num_addresses; - at24->offset_adj = at24_get_offset_adj(flags, byte_len); + at24->offset_adj = cdata->adjoff ? + at24_get_offset_adj(flags, byte_len) : 0; at24->client_regmaps[0] = regmap; at24->vcc_reg = devm_regulator_get(dev, "vcc"); From patchwork Fri Jun 28 08:01:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrei Simion X-Patchwork-Id: 808551 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C9C2146580; Fri, 28 Jun 2024 08:02:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719561745; cv=none; b=OkEfToitmqqIUsUJ+8yQ4UEA1L/XEj2KwcZMT1SXVxy3TMKT0d3VLstuI1NSXhrjlTGc/W6C5XKiyMmkse+VS0IjbFc2cfSj1mo+yFEPl8OCV+6ZlvjqvSdrcVjLiyD3uGgYzkKlQVZemBjHER4uAByz5RLchEa7fqO6u0kA6To= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719561745; c=relaxed/simple; bh=ZC5GcFCvoF9+YP4CsOoHkV5xsw2QFzOG1jhwWHB4+zw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DtPmgljQkfLUV3tv5Fjt/31SiwONdpwnv40ZX2Yu875AqxnlQlmrTL1VEnkASZpEk418CyWULbEZFje/XCFy2yXwwXndwab9xnBjHYnn7iyao0bvpmr9y1M9ebnuM2bv4w0tJD8xZLJltdrZnAk87ki05rmewh3+NCyqP+5ShYc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=q3ZtBSeM; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="q3ZtBSeM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1719561744; x=1751097744; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZC5GcFCvoF9+YP4CsOoHkV5xsw2QFzOG1jhwWHB4+zw=; b=q3ZtBSeMvEV2azJHvNowgN1BFSvprAkfzYltBL/5anH1iccAdxoiUiPs UErilpGyi7F8SngrMq0C7S8MXRMxHgsTqIn1VP2SsVq+D8CKOEpspAh4X BRU/cQJ3NRCOHzfHpkZFKPycAA2m9dCaoBOKNtvHcD4jzHdUGJPiBoCmg E1s+VLEJgJHdjWRKjYmtD2sIvL9rUNrRTY91WXb49shRIy0EMjU4FD/qG LJFXaRVq9hNt8NbLtK3K97jGM++XFOKZtd5j4HXtlhnjEXNlAevSBAJv7 4AJoWNGz06mV5jaRZj2YgZ0N8ZAPR3P86HrdM53PriXNjo8yPUcRPSNST A==; X-CSE-ConnectionGUID: yumzE5LRQZWNGcwzrru4aA== X-CSE-MsgGUID: fZ26NDPwRgWx82z9wG7gcA== X-IronPort-AV: E=Sophos;i="6.09,168,1716274800"; d="scan'208";a="28620942" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 01:02:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 01:02:09 -0700 Received: from ROB-ULT-M76677.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 01:02:05 -0700 From: Andrei Simion To: , , , , , , , , CC: , , , , Claudiu Beznea , Andrei Simion Subject: [PATCH v3 2/3] ARM: dts: at91: at91-sama7g5ek: add EEPROMs Date: Fri, 28 Jun 2024 11:01:45 +0300 Message-ID: <20240628080146.49545-3-andrei.simion@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628080146.49545-1-andrei.simion@microchip.com> References: <20240628080146.49545-1-andrei.simion@microchip.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add EEPROMs and nvmem-layout to describe eui48 mac address region. Signed-off-by: Claudiu Beznea [andrei.simion@microchip.com: add nvmem-layout to describe eui48 mac region align compatible name with datasheet] Signed-off-by: Andrei Simion --- v2 -> v3: - change from atmel,24mac02e4 to microchip,24aa025e48 to align with the datasheet - drop co-developed-by to maintain the chronological order of the changes v1 -> v2: - remove unnecessary #address-cells #size-cells --- .../arm/boot/dts/microchip/at91-sama7g5ek.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts index 20b2497657ae..40f4480e298b 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -403,6 +403,42 @@ i2c8: i2c@600 { i2c-digital-filter; i2c-digital-filter-width-ns = <35>; status = "okay"; + + eeprom0: eeprom@52 { + compatible = "microchip,24aa025e48"; + reg = <0x52>; + size = <256>; + pagesize = <16>; + vcc-supply = <&vdd_3v3>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom0_eui48: eui48@fa { + reg = <0xfa 0x6>; + }; + }; + }; + + eeprom1: eeprom@53 { + compatible = "microchip,24aa025e48"; + reg = <0x53>; + size = <256>; + pagesize = <16>; + vcc-supply = <&vdd_3v3>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom1_eui48: eui48@fa { + reg = <0xfa 0x6>; + }; + }; + }; }; }; @@ -440,6 +476,8 @@ &pinctrl_gmac0_mdio_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; phy-mode = "rgmii-id"; + nvmem-cells = <&eeprom0_eui48>; + nvmem-cell-names = "mac-address"; status = "okay"; ethernet-phy@7 { @@ -457,6 +495,8 @@ &gmac1 { &pinctrl_gmac1_mdio_default &pinctrl_gmac1_phy_irq>; phy-mode = "rmii"; + nvmem-cells = <&eeprom1_eui48>; + nvmem-cell-names = "mac-address"; status = "okay"; /* Conflict with pdmc0. */ ethernet-phy@0 { From patchwork Fri Jun 28 08:01:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrei Simion X-Patchwork-Id: 808429 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1A6314389A; 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X-CSE-ConnectionGUID: yumzE5LRQZWNGcwzrru4aA== X-CSE-MsgGUID: KD5gqNbzR0+ZM1jMBVwfDA== X-IronPort-AV: E=Sophos;i="6.09,168,1716274800"; d="scan'208";a="28620945" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Jun 2024 01:02:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 28 Jun 2024 01:02:13 -0700 Received: from ROB-ULT-M76677.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 28 Jun 2024 01:02:09 -0700 From: Andrei Simion To: , , , , , , , , CC: , , , , Andrei Simion , Connor Dooley Subject: [PATCH v3 3/3] dt-bindings: eeprom: at24: Add Microchip 24AA025E48/24AA025E64 Date: Fri, 28 Jun 2024 11:01:46 +0300 Message-ID: <20240628080146.49545-4-andrei.simion@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628080146.49545-1-andrei.simion@microchip.com> References: <20240628080146.49545-1-andrei.simion@microchip.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add compatible for Microchip 24AA025E48/24AA025E64 EEPROMs. Reviewed-by: Connor Dooley Signed-off-by: Andrei Simion --- v2 -> v3: - commit subject changed to reference Microchip 24AA025E48/24AA025E64 - drop the pattern: mac02e4$ and mac02e6$ and a-z from regex - add these two devices down at the bottom - added Reviewed-by v1 -> v2: - change pattern into "^atmel,(24(c|cs|mac)[a-z0-9]+|spd)$" to keep simpler --- Documentation/devicetree/bindings/eeprom/at24.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml index 3c36cd0510de..699c2bbc16f5 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.yaml +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -132,6 +132,10 @@ properties: - renesas,r1ex24128 - samsung,s524ad0xd1 - const: atmel,24c128 + - items: + - const: microchip,24aa025e48 + - items: + - const: microchip,24aa025e64 - pattern: '^atmel,24c(32|64)d-wl$' # Actual vendor is st label: