From patchwork Wed Jul 3 22:15:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Cheluvegowda X-Patchwork-Id: 810854 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6336313D638; Wed, 3 Jul 2024 22:16:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720044971; cv=none; b=LW5Uqug29/oS0V0JL4ZmbJCiLOfJRe07Aep0O9SYuD+oDK9EoLJkDZcMXRmFcqAaRP9ylSdOKzmd5dTFpRRQT6dau0zoc5MM3IRiGoef45IE5BZlnFdMwFNLPuWdKK45DkoCNxpWefXf9IUZnjulg0cGOMFs2huokp88ON87hFk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720044971; c=relaxed/simple; bh=8qnEkM1tCQqlFds8Vo++c+Ec0foFAGlgMtXpuV4BuYM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=MZImQ1BM5nMPIHAKmfHTbF7cucQRXUTTROQaPekm07GlbDeg9ZUodAzFHmY1DwYxp4kOO0TtrMlLBE5EQ9DYfoPKR/XlRb3yB+3EjGyK2HBgjefZ/L/VyHt27YaAyhCid2oVuav5sIIu1mtI0uaB4mQbIq1z4tou+4R8K0D7b1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Da5lJRSA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Da5lJRSA" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 463AATXK013681; Wed, 3 Jul 2024 22:15:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 5gx2z++go3lmdlJ7suDIvslktQNjYu4UWvXHRKPW/EM=; b=Da5lJRSAWNEl77gW z5ByX80GtyWtJC9X0cj0EEoBpCsdjlMy7BW5GhuR2WnQz9Oqc5x3iRC+j+Mck5hS Z/JsveEJFVGXzGxVww1zuvRIlBpOGhPb9FWZt8ACFVpMC3gl3vsGMcVmz1W0PdBg O4mI8PhUyv7EGSfUuVxoJn19eB6JgnyeAhw4NEGW+5TwOmLyGrv3C+MP+ZuEGkaZ 8qT8LzaSyX59UqLmwvpNCTq4J0GfHq00hc/At+Vkm1YJC3vv78R5SSF3/tJxZnmW tj3E7SmbytuSzDJ/PD6j7GHyA0jvrpdqkHT3mxqlsB9WoqWf2BIGqrSvS+uo2EWK kH2nOA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4054ndse7r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 Jul 2024 22:15:40 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 463MFdjp006141 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Jul 2024 22:15:39 GMT Received: from hu-scheluve-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 15:15:36 -0700 From: Sagar Cheluvegowda Date: Wed, 3 Jul 2024 15:15:21 -0700 Subject: [PATCH v3 1/2] dt-bindings: net: qcom: ethernet: Add interconnect properties Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240703-icc_bw_voting_from_ethqos-v3-1-8f9148ac60a3@quicinc.com> References: <20240703-icc_bw_voting_from_ethqos-v3-0-8f9148ac60a3@quicinc.com> In-Reply-To: <20240703-icc_bw_voting_from_ethqos-v3-0-8f9148ac60a3@quicinc.com> To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Maxime Coquelin , Russell King , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Bhupesh Sharma CC: , Andrew Halaney , Andrew Lunn , , , , , , , Sagar Cheluvegowda X-Mailer: b4 0.13.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gBmN92ICWt_uSGDvqlxDwp8_EW8QRyEy X-Proofpoint-ORIG-GUID: gBmN92ICWt_uSGDvqlxDwp8_EW8QRyEy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_16,2024-07-03_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 phishscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030166 Add documentation for the interconnect and interconnect-names properties required when voting for AHB and AXI buses. Suggested-by: Andrew Halaney Signed-off-by: Sagar Cheluvegowda --- Documentation/devicetree/bindings/net/qcom,ethqos.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml index 6672327358bc..f0e8eaf51137 100644 --- a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml @@ -63,6 +63,14 @@ properties: dma-coherent: true + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-mac + - const: mac-mem + phys: true phy-names: From patchwork Wed Jul 3 22:15:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sagar Cheluvegowda X-Patchwork-Id: 809376 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DFA913B59A; Wed, 3 Jul 2024 22:16:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720044971; cv=none; b=S72MjwkyVX+fXtp99ZSaiv/j1uAa2YbXMEJ6yCpA7M1u9/IeZPJfSTUWNAOgwAH3MyvOaSNdC63+aiNX/mQBCMDHWI6L+45WabP5CDHneUSq5RfUiNTcfLWW5SYudsNhbitrdAJt1a3eu51hBniD5oTChMF1Ey3NUc2Fv2qtAPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720044971; c=relaxed/simple; bh=UQd0EeHvwuiEjQaFcAKp5z898/9I3p67P2UNvkMBYmQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=D3pYpw/3Jtc3iEVcaApMS1sNUxRI8+esBURP41vXbIMWzwQqi8k/I9iNAcxbsL3ZLGanfJI5w8iZiwZyKdCVosqvsyDaVLD2qy5MY3zKy+fsQ+L1wQrqzXhWIMEnvEdP/eNifFuDxzzezTtasUwqSYOKhZ1pcTl0KlNWXmhehVI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=FNQkNAjV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="FNQkNAjV" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 463K3EdV022467; Wed, 3 Jul 2024 22:15:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= KS606ZWf5wW3Nf/IpnMfTERzoRSsXb3f/8SaJ+eoiwA=; b=FNQkNAjVvuu31Bjl ezcEvUWvV9ywpUEUSNUnI5Xj0We/gsoiDAI/Kxf9fsw2kEp5O+xtCJKGEvHNYqOX T4h2L0vBWgFhFrfEk5WdsNcbKSGSh/rAzvRao8DSXi8q3jURLZpzF6zoOO0Fh23u N2CV3ofBsR1ogvKMzXQOmOIvsqlVTDrZG6YAz8ODcACdPyYVs1qz12Ps3hIQAGUN HTiTrKK9/sjwt+4l+0vcyVsxpakimg//AXxl5eaMfVLg399WpJoRvJNOfJ6tFIZT GyTQ3hT9jgtyL6TSsS6rCjoAdVHT8357Fh15q0owq2q0mZOSzgjutBTcHYmExE4C 8Tlbvg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 405dbe06q1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 Jul 2024 22:15:41 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 463MFeOF007405 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Jul 2024 22:15:40 GMT Received: from hu-scheluve-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 15:15:37 -0700 From: Sagar Cheluvegowda Date: Wed, 3 Jul 2024 15:15:22 -0700 Subject: [PATCH v3 2/2] net: stmmac: Add interconnect support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240703-icc_bw_voting_from_ethqos-v3-2-8f9148ac60a3@quicinc.com> References: <20240703-icc_bw_voting_from_ethqos-v3-0-8f9148ac60a3@quicinc.com> In-Reply-To: <20240703-icc_bw_voting_from_ethqos-v3-0-8f9148ac60a3@quicinc.com> To: Vinod Koul , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Maxime Coquelin , Russell King , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Bhupesh Sharma CC: , Andrew Halaney , Andrew Lunn , , , , , , , Sagar Cheluvegowda X-Mailer: b4 0.13.0 X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KgCNz1_N_5gVeeMPqWskJum1U1lOOxEv X-Proofpoint-GUID: KgCNz1_N_5gVeeMPqWskJum1U1lOOxEv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_16,2024-07-03_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 clxscore=1015 suspectscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030166 Add interconnect support to vote for bus bandwidth based on the current speed of the driver. Adds support for two different paths - one from ethernet to DDR and the other from CPU to ethernet, Vote from each interconnect client is aggregated and the on-chip interconnect hardware is configured to the most appropriate bandwidth profile. Suggested-by: Andrew Halaney Signed-off-by: Sagar Cheluvegowda --- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 ++++++++ drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 ++++++++++++ include/linux/stmmac.h | 2 ++ 4 files changed, 23 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index b23b920eedb1..56a282d2b8cd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index b3afc7cb7d72..ec7c61ee44d4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -985,6 +985,12 @@ static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) } } +static void stmmac_set_icc_bw(struct stmmac_priv *priv, unsigned int speed) +{ + icc_set_bw(priv->plat->axi_icc_path, Mbps_to_icc(speed), Mbps_to_icc(speed)); + icc_set_bw(priv->plat->ahb_icc_path, Mbps_to_icc(speed), Mbps_to_icc(speed)); +} + static void stmmac_mac_link_down(struct phylink_config *config, unsigned int mode, phy_interface_t interface) { @@ -1080,6 +1086,8 @@ static void stmmac_mac_link_up(struct phylink_config *config, if (priv->plat->fix_mac_speed) priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed, mode); + stmmac_set_icc_bw(priv, speed); + if (!duplex) ctrl &= ~priv->hw->link.duplex; else diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 54797edc9b38..201f9dea6da9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -642,6 +642,18 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac) dev_dbg(&pdev->dev, "PTP rate %d\n", plat->clk_ptp_rate); } + plat->axi_icc_path = devm_of_icc_get(&pdev->dev, "mac-mem"); + if (IS_ERR(plat->axi_icc_path)) { + ret = ERR_CAST(plat->axi_icc_path); + goto error_hw_init; + } + + plat->ahb_icc_path = devm_of_icc_get(&pdev->dev, "cpu-mac"); + if (IS_ERR(plat->ahb_icc_path)) { + ret = ERR_CAST(plat->ahb_icc_path); + goto error_hw_init; + } + plat->stmmac_rst = devm_reset_control_get_optional(&pdev->dev, STMMAC_RESOURCE_NAME); if (IS_ERR(plat->stmmac_rst)) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index f92c195c76ed..385f352a0c23 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -283,6 +283,8 @@ struct plat_stmmacenet_data { struct reset_control *stmmac_rst; struct reset_control *stmmac_ahb_rst; struct stmmac_axi *axi; + struct icc_path *axi_icc_path; + struct icc_path *ahb_icc_path; int has_gmac4; int rss_en; int mac_port_sel_speed;