From patchwork Wed Jul 3 09:16:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 809644 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B016B13D2B7; Wed, 3 Jul 2024 09:17:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719998269; cv=none; b=HwQS54isXSbL90faFgMI/LWmxtiIKJz49twanCr526olcPa4cdhQULJzcJG3LwdsVdtmxSE0UUPDGXtVZoO52WZXTnRtWjaQchQkf9qdGo0M1njNBDCkDYsGtzJhZrAi5P1hSYSkZgqyWhlkSmklORiNbDhDSqzmlDmrAipIhK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719998269; c=relaxed/simple; bh=Giq0YZ8UqpivqKH5CEyQKPNid4kcnWD78n3S1MlXmbQ=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lesE7cd5vw9wFO0MmnOrQPnCdQmS7ZG6djAHFuUfE6jWJyEiVtL2SWef2aj4Jkwno/Lhjd6iR4Wk7IDfDTpU0qBQl6jegEglfnNH+Y0Ty1MneSd8XEacst01WXXwMAQCN3+BE2PFTWcPqiZC3DvtRSQo/5Xo2Amua5ydih1NXeI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=h2y/H188; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="h2y/H188" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4637DYa9017281; Wed, 3 Jul 2024 09:17:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4f5DlQItyyZlA7LId3xN7drZuYBh2CJ4GP6ktbkqadA=; b=h2y/H188MfjIhh+s rfuIhenZbn5mUj/gQwVpnxsU2F0NM4YAkJqTY4aNUTBMvs2mwFt0IAD4bfJK3l8z J5qU7oAQiYSJy184QrqenyiSxc5Ohw47cEuLPpXdayTSUrFaL8SCIDYogvEo7U7b GQPd9zFLiBB4EFa4ZQHHEtjBFdH+m0eCq+sK6zrjxee/usJxepB1fuixxp+1Z98W KFJG3C3x5gXPFOUCjxbUfAE1MwGtCaI8ScWdHWdusrcK8rDjsLlkviaxedr5lcC2 K2lk5dP2RIap1dDtuWRASeD0eRO0NyhkOBwtR7ZXN8V1BC1UlMiTdTvSoIIVqoAI LaFJoQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 402an78axe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 03 Jul 2024 09:17:34 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4639HXUF017611 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Jul 2024 09:17:33 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 02:17:25 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 01/10] soc: qcom: cpr3: Fix 'acc_desc' usage Date: Wed, 3 Jul 2024 14:46:42 +0530 Message-ID: <20240703091651.2820236-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240703091651.2820236-1-quic_varada@quicinc.com> References: <20240703091651.2820236-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WLONT5ZvO0_rSTIEmWnqTtM1RORZSecx X-Proofpoint-ORIG-GUID: WLONT5ZvO0_rSTIEmWnqTtM1RORZSecx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_05,2024-07-02_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=718 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030068 cpr3 code assumes that 'acc_desc' is available for SoCs implementing CPR version 4 or less. However, IPQ9574 SoC implements CPRv4 without ACC. This causes NULL pointer accesses resulting in crashes. Hence, check if 'acc_desc' is populated before using it. Signed-off-by: Varadarajan Narayanan --- v4: Undo the acc_desc validation in probe function as that could affect other SoC. --- drivers/pmdomain/qcom/cpr3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/qcom/cpr3.c b/drivers/pmdomain/qcom/cpr3.c index c7790a71e74f..6ceb7605f84d 100644 --- a/drivers/pmdomain/qcom/cpr3.c +++ b/drivers/pmdomain/qcom/cpr3.c @@ -2399,12 +2399,12 @@ static int cpr_pd_attach_dev(struct generic_pm_domain *domain, if (ret) goto exit; - if (acc_desc->config) + if (acc_desc && acc_desc->config) regmap_multi_reg_write(drv->tcsr, acc_desc->config, acc_desc->num_regs_per_fuse); /* Enable ACC if required */ - if (acc_desc->enable_mask) + if (acc_desc && acc_desc->enable_mask) regmap_update_bits(drv->tcsr, acc_desc->enable_reg, acc_desc->enable_mask, acc_desc->enable_mask); From patchwork Wed Jul 3 09:16:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 809643 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B80BA136E3A; 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Wed, 03 Jul 2024 09:17:51 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4639Honc028244 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Jul 2024 09:17:50 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 02:17:41 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v4 03/10] dt-bindings: power: rpmpd: Add IPQ9574 power domains Date: Wed, 3 Jul 2024 14:46:44 +0530 Message-ID: <20240703091651.2820236-4-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240703091651.2820236-1-quic_varada@quicinc.com> References: <20240703091651.2820236-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: QLwJLAohtBkic7jGHIycFu3-p7_UuId4 X-Proofpoint-ORIG-GUID: QLwJLAohtBkic7jGHIycFu3-p7_UuId4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_05,2024-07-02_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=937 priorityscore=1501 impostorscore=0 bulkscore=0 spamscore=0 mlxscore=0 clxscore=1015 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030068 Add the compatibles and indexes for the rpmpd in IPQ9574. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan --- v3 & v4: no changes v2: Add Reviewed-by --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 929b7ef9c1bc..e20ba25fa094 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,ipq9574-rpmpd - qcom,mdm9607-rpmpd - qcom,msm8226-rpmpd - qcom,msm8909-rpmpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 608087fb9a3d..0538370bfbb4 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -402,6 +402,9 @@ #define QCM2290_VDD_LPI_CX 6 #define QCM2290_VDD_LPI_MX 7 +/* IPQ9574 Power Domains */ +#define IPQ9574_VDDAPC 0 + /* RPM SMD Power Domain performance levels */ #define RPM_SMD_LEVEL_RETENTION 16 #define RPM_SMD_LEVEL_RETENTION_PLUS 32 From patchwork Wed Jul 3 09:16:46 2024 Content-Type: text/plain; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- v4: Add Reviewed-by: Dmitry Baryshkov v3: Fix patch author v2: Fix Signed-off-by order --- drivers/pmdomain/qcom/rpmpd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pmdomain/qcom/rpmpd.c b/drivers/pmdomain/qcom/rpmpd.c index 5e6280b4cf70..947d6a9c3897 100644 --- a/drivers/pmdomain/qcom/rpmpd.c +++ b/drivers/pmdomain/qcom/rpmpd.c @@ -38,6 +38,7 @@ static struct qcom_smd_rpm *rpmpd_smd_rpm; #define KEY_FLOOR_CORNER 0x636676 /* vfc */ #define KEY_FLOOR_LEVEL 0x6c6676 /* vfl */ #define KEY_LEVEL 0x6c766c76 /* vlvl */ +#define RPM_KEY_UV 0x00007675 /* "uv" */ #define MAX_CORNER_RPMPD_STATE 6 @@ -644,6 +645,23 @@ static const struct rpmpd_desc mdm9607_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; +static struct rpmpd apc_s1_lvl = { + .pd = { .name = "apc", }, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = RPM_KEY_UV, +}; + +static struct rpmpd *ipq9574_rpmpds[] = { + [IPQ9574_VDDAPC] = &apc_s1_lvl, +}; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- drivers/clk/qcom/gcc-ipq9574.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index e1dc74d04ed1..eac557937fd3 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -3994,6 +3994,43 @@ static struct clk_branch gcc_xo_div4_clk = { }, }; +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_xo_map, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_map), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rbcpr_clk", + .parent_hws = (const struct clk_hw *[]) { + &rbcpr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_hw *gcc_ipq9574_hws[] = { &gpll0_out_main_div2.hw, &gcc_xo_div4_clk_src.hw, @@ -4219,6 +4256,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GCC_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = { From patchwork Wed Jul 3 09:16:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 809640 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A950413D504; Wed, 3 Jul 2024 09:18:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 03 Jul 2024 09:18:41 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 4639IeCw026877 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Jul 2024 09:18:40 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 02:18:32 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 09/10] dt-bindings: opp: v2-qcom-level: Update minItems for oloop-vadj & cloop-vadj Date: Wed, 3 Jul 2024 14:46:50 +0530 Message-ID: <20240703091651.2820236-10-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240703091651.2820236-1-quic_varada@quicinc.com> References: <20240703091651.2820236-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Y_hRHQlQ0taji3iJaRBGba5XLY7AvdQb X-Proofpoint-ORIG-GUID: Y_hRHQlQ0taji3iJaRBGba5XLY7AvdQb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_05,2024-07-02_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030068 Since IPQ9574 has only one CPR thread it will specify only one voltage adjustment value. Hence update min items accordingly for oloop-vadj and cloop-vadj. Without constraining min items, dt_binding_check gives errors opp-table-cpr4:opp-0:qcom,opp-cloop-vadj:0: [0] is too short opp-table-cpr4:opp-0:qcom,opp-oloop-vadj:0: [0] is too short Failed validating 'minItems' in schema . . . {'maxItems': 2, 'minItems': 2} Signed-off-by: Varadarajan Narayanan --- v4: Fix dt_bindings_check error --- Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml index b203ea01b17a..1c1a9e12d57a 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml @@ -39,6 +39,7 @@ patternProperties: An array of per-thread values representing the closed-loop voltage adjustment value associated with this OPP node. $ref: /schemas/types.yaml#/definitions/int32-array + minItems: 1 maxItems: 2 qcom,opp-oloop-vadj: @@ -46,6 +47,7 @@ patternProperties: An array of per-thread values representing the open-loop voltage adjustment value associated with this OPP node. $ref: /schemas/types.yaml#/definitions/int32-array + minItems: 1 maxItems: 2 required: