From patchwork Wed Oct 30 11:41:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 178096 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp1153885ill; Wed, 30 Oct 2019 04:45:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJJ9mysASAoIEzlNng7m5FVEhQQybRcNaWbzmCo+cxTgZF5FM4136qXdycmgYc3i6KwdrA X-Received: by 2002:a50:ff12:: with SMTP id a18mr12920859edu.200.1572435903884; Wed, 30 Oct 2019 04:45:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572435903; cv=none; d=google.com; s=arc-20160816; b=lJW50cyRVUOW4wZTnp6zxMMV2G29xUk2L/SS1DtgvYRHCt9cl8zNRKxgc7ygFlgP/1 Xkr/BWJR+QVS77Y8V3qqocA+xT8UCDtEHb3gFszILz9xHO0H+3BAVx/EjmeLiBayZVt+ RC/fI7WIMyl0dejZV+8GpOGCfUfozx8R2lYrOdmtNzXpxbNczX1fsOepyVjBovxBr851 Htng+Q/bHAcErK9PkHW4dEyL5nnZnsNmXQFATX0Ev8Jh951xOfYNVG6Ql35riKPVk8Z7 rS/SZjs8TESXejZ4uvFyMdgdj9RjTPnRSfJBCubC1Wm80ijgo/eWa6B3g864wgorzooh cg7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=3W+uHv+8epJnZmyi9PrPeH6RKRpKpaZQugvnzd5sLuE=; b=pcnARwhZY4qKsu5uoveoQdTTPeHa6jUHUErtXsGS3cY6+Xf3lAy7mwJ7PhzooMfIuw lp4LKl0ZH+dhVjOppLdVIRlbX7jmhefvvO7DVrv28ZtKNabzLXfFCYgdGoxwg3L4h6AW FNqv07vAMpc3dd/yAqz7F8xMPjmoZr2fDsMqhQ61pUlm0w07rZpC7YvuTgcW22CyZH9H Z2VWf51n4DDU781ufxwe5Qx6d322gTKmtUIbvnVeYGbR/veojPYUKnBE3qJ5KZjMSV6T r9y5ggE+NGa+SPZ5c8vvS+ND719g5eNtYR5KwKWnDcEUHbkcCANIEsxibPMZx3Csnfxv X1tQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q17si959481ejm.165.2019.10.30.04.45.03; Wed, 30 Oct 2019 04:45:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726646AbfJ3LpD (ORCPT + 8 others); Wed, 30 Oct 2019 07:45:03 -0400 Received: from inva020.nxp.com ([92.121.34.13]:50696 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726488AbfJ3LpC (ORCPT ); Wed, 30 Oct 2019 07:45:02 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id F41A21A0065; Wed, 30 Oct 2019 12:45:00 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E1B371A0463; Wed, 30 Oct 2019 12:44:54 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 32EEB402E2; Wed, 30 Oct 2019 19:44:47 +0800 (SGT) From: Shengjiu Wang To: timur@kernel.org, nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, broonie@kernel.org, alsa-devel@alsa-project.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 1/2] ASoC: dt-bindings: fsl_asrc: add compatible string for imx8qm Date: Wed, 30 Oct 2019 19:41:26 +0800 Message-Id: <6465fb7dfaa68b6693584bcfa696894628d45fe9.1572435604.git.shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to support the two asrc modules in imx8qm, we need to add compatible string "fsl,imx8qm-asrc0" and "fsl,imx8qm-asrc1" Signed-off-by: Shengjiu Wang --- Documentation/devicetree/bindings/sound/fsl,asrc.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.21.0 diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt index 1d4d9f938689..cd2bd3daa7e1 100644 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt @@ -8,7 +8,8 @@ three substreams within totally 10 channels. Required properties: - - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc". + - compatible : Contains "fsl,imx35-asrc", "fsl,imx53-asrc", + "fsl,imx8qm-asrc0" or "fsl,imx8qm-asrc1". - reg : Offset and length of the register set for the device. From patchwork Wed Oct 30 11:41:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 178097 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp1154921ill; Wed, 30 Oct 2019 04:45:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqwUyrhosQYs1st0bszL8Zl1qP+iMrYCs9i/8EgnJb+sbvrJ2Ia3yGSjqD+NbW/07j8cHmDq X-Received: by 2002:aa7:cd03:: with SMTP id b3mr30882199edw.95.1572435957351; Wed, 30 Oct 2019 04:45:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572435957; cv=none; d=google.com; s=arc-20160816; b=hLYjyl74zcD3vukqoB1v0dIPJIqvx4N3kG5az8K92FkWNgQ+2ka+8WOE63fMhkVGjN QSiZRklQRcvvOMAtG9+rRkyJLJQiTX+sZSzf1TjMjZ/aLk/F7HHmZe0F78urdmvMjamO g6pIGJS0m0fNLn7DkOvN+R6HnxAqexd9D6Sckr4v8Re189G7dOZgQVst3hndw2b126AJ gHy/6Ig3Wjy4s2fV0F3cH6t5iqLt+Uete835tphlM49tJcXOXDi2P4AeYTDPXwSgVm8Q IHIsE/gUMXtxMl0d1BjBUf/zlqZssYiOAeKg95zIJjBwdpYQGm1QKm1mq7lcXFzLGTCo Qf6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from; bh=gEnn6fxz+yxaLz0V4xHxdZNCPisqoyjHnfDSqzzVq4g=; b=X1thi7CC/dxUFmIbUCyNojEIyJ3z4FrI7tElzIbn6K5jiWBSqkC+/9bIOCS1tBrzBC Q35z8PCItZhvgLbrTr4A7fHwtqMR51Y3JBjRJiZ0p17JSUBqNK0+8HOZbDUAI3uCYkJy afvEjISnXzTtmw/oBUSmJtQaldAokXXl5rgiuv/Q3Lz07P3MAcF6KjnW2IACs714nkHG a/GytVLJ62bwnNuy5pYBjZnOSc+t6JhuJsYeXuVpirSZ1HzksBYTi0L6Uvubb8zwto16 DIoUA5dvhOAuzXFIBlbPMn0/sosdQ0nCozmn+NJfXH669pORAAtGr5Lj0r6lkgFo7mBU pORg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v26si1130953ejg.55.2019.10.30.04.45.57; Wed, 30 Oct 2019 04:45:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726088AbfJ3Lp4 (ORCPT + 8 others); Wed, 30 Oct 2019 07:45:56 -0400 Received: from inva021.nxp.com ([92.121.34.21]:57392 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726065AbfJ3Lp4 (ORCPT ); Wed, 30 Oct 2019 07:45:56 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 2F6E2200481; Wed, 30 Oct 2019 12:45:50 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B18E9200092; Wed, 30 Oct 2019 12:45:43 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 0DD29402B7; Wed, 30 Oct 2019 19:45:35 +0800 (SGT) From: Shengjiu Wang To: timur@kernel.org, nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, broonie@kernel.org, alsa-devel@alsa-project.org, lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 2/2] ASoC: fsl_asrc: Add support for imx8qm Date: Wed, 30 Oct 2019 19:41:27 +0800 Message-Id: <2000eb7ee4c086020157bfc209dd02cf1a1cbffc.1572435604.git.shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <6465fb7dfaa68b6693584bcfa696894628d45fe9.1572435604.git.shengjiu.wang@nxp.com> References: <6465fb7dfaa68b6693584bcfa696894628d45fe9.1572435604.git.shengjiu.wang@nxp.com> In-Reply-To: <6465fb7dfaa68b6693584bcfa696894628d45fe9.1572435604.git.shengjiu.wang@nxp.com> References: <6465fb7dfaa68b6693584bcfa696894628d45fe9.1572435604.git.shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are two asrc module in imx8qm, each module has different clock configuration, and the DMA type is EDMA. So in this patch, we define the new clocks, refine the clock map, and include struct fsl_asrc_soc_data for different soc usage. The EDMA channel is fixed with each dma request, one dma request corresponding to one dma channel. So we need to request dma channel with dma request of asrc module. Signed-off-by: Shengjiu Wang Acked-by: Nicolin Chen --- Changes in v2 - use !use_edma to wrap code in fsl_asrc_dma - add Acked-by: Nicolin Chen sound/soc/fsl/fsl_asrc.c | 91 +++++++++++++++++++++++++++++------- sound/soc/fsl/fsl_asrc.h | 65 +++++++++++++++++++++++++- sound/soc/fsl/fsl_asrc_dma.c | 42 +++++++++++------ 3 files changed, 166 insertions(+), 32 deletions(-) -- 2.21.0 diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c index a3cfceea7d2f..9dc5b5a93fb0 100644 --- a/sound/soc/fsl/fsl_asrc.c +++ b/sound/soc/fsl/fsl_asrc.c @@ -43,24 +43,55 @@ static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = { */ static unsigned char input_clk_map_imx35[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, }; static unsigned char output_clk_map_imx35[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, }; /* i.MX53 uses the same map for input and output */ static unsigned char input_clk_map_imx53[] = { /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, + 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, + 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, }; static unsigned char output_clk_map_imx53[] = { /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, + 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, + 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, }; -static unsigned char *clk_map[2]; +/* i.MX8QM uses the same map for input and output */ +static unsigned char input_clk_map_imx8_0[] = { + 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, + 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, + 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, +}; + +static unsigned char output_clk_map_imx8_0[] = { + 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, + 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, + 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, +}; + +static unsigned char input_clk_map_imx8_1[] = { + 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, + 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, + 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, +}; + +static unsigned char output_clk_map_imx8_1[] = { + 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, + 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, + 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, +}; /** * Select the pre-processing and post-processing options @@ -353,8 +384,8 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate) } /* Validate input and output clock sources */ - clk_index[IN] = clk_map[IN][config->inclk]; - clk_index[OUT] = clk_map[OUT][config->outclk]; + clk_index[IN] = asrc_priv->soc->inclk_map[config->inclk]; + clk_index[OUT] = asrc_priv->soc->outclk_map[config->outclk]; /* We only have output clock for ideal ratio mode */ clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; @@ -398,13 +429,13 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate) /* Set the channel number */ channels = config->channel_num; - if (asrc_priv->channel_bits < 4) + if (asrc_priv->soc->channel_bits < 4) channels /= 2; /* Update channels for current pair */ regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR, - ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits), - ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits)); + ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits), + ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits)); /* Default setting: Automatic selection for processing mode */ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, @@ -531,7 +562,7 @@ static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); /* Odd channel number is not valid for older ASRC (channel_bits==3) */ - if (asrc_priv->channel_bits == 3) + if (asrc_priv->soc->channel_bits == 3) snd_pcm_hw_constraint_step(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2); @@ -964,14 +995,10 @@ static int fsl_asrc_probe(struct platform_device *pdev) } } - if (of_device_is_compatible(np, "fsl,imx35-asrc")) { - asrc_priv->channel_bits = 3; - clk_map[IN] = input_clk_map_imx35; - clk_map[OUT] = output_clk_map_imx35; - } else { - asrc_priv->channel_bits = 4; - clk_map[IN] = input_clk_map_imx53; - clk_map[OUT] = output_clk_map_imx53; + asrc_priv->soc = of_device_get_match_data(&pdev->dev); + if (!asrc_priv->soc) { + dev_err(&pdev->dev, "failed to get soc data\n"); + return -ENODEV; } ret = fsl_asrc_init(asrc_priv); @@ -1113,9 +1140,39 @@ static const struct dev_pm_ops fsl_asrc_pm = { SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) }; +static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = { + .use_edma = false, + .channel_bits = 3, + .inclk_map = input_clk_map_imx35, + .outclk_map = output_clk_map_imx35, +}; + +static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = { + .use_edma = false, + .channel_bits = 4, + .inclk_map = input_clk_map_imx53, + .outclk_map = output_clk_map_imx53, +}; + +static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_0_data = { + .use_edma = true, + .channel_bits = 4, + .inclk_map = input_clk_map_imx8_0, + .outclk_map = output_clk_map_imx8_0, +}; + +static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_1_data = { + .use_edma = true, + .channel_bits = 4, + .inclk_map = input_clk_map_imx8_1, + .outclk_map = output_clk_map_imx8_1, +}; + static const struct of_device_id fsl_asrc_ids[] = { - { .compatible = "fsl,imx35-asrc", }, - { .compatible = "fsl,imx53-asrc", }, + { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data }, + { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data }, + { .compatible = "fsl,imx8qm-asrc0", .data = &fsl_asrc_imx8qm_0_data }, + { .compatible = "fsl,imx8qm-asrc1", .data = &fsl_asrc_imx8qm_1_data }, {} }; MODULE_DEVICE_TABLE(of, fsl_asrc_ids); diff --git a/sound/soc/fsl/fsl_asrc.h b/sound/soc/fsl/fsl_asrc.h index 2b57e8c53728..8decbe670c3e 100644 --- a/sound/soc/fsl/fsl_asrc.h +++ b/sound/soc/fsl/fsl_asrc.h @@ -308,6 +308,29 @@ enum asrc_inclk { INCLK_SSI3_TX = 0x0b, INCLK_SPDIF_TX = 0x0c, INCLK_ASRCK1_CLK = 0x0f, + + /* clocks for imx8 */ + INCLK_AUD_PLL_DIV_CLK0 = 0x10, + INCLK_AUD_PLL_DIV_CLK1 = 0x11, + INCLK_AUD_CLK0 = 0x12, + INCLK_AUD_CLK1 = 0x13, + INCLK_ESAI0_RX_CLK = 0x14, + INCLK_ESAI0_TX_CLK = 0x15, + INCLK_SPDIF0_RX = 0x16, + INCLK_SPDIF1_RX = 0x17, + INCLK_SAI0_RX_BCLK = 0x18, + INCLK_SAI0_TX_BCLK = 0x19, + INCLK_SAI1_RX_BCLK = 0x1a, + INCLK_SAI1_TX_BCLK = 0x1b, + INCLK_SAI2_RX_BCLK = 0x1c, + INCLK_SAI3_RX_BCLK = 0x1d, + INCLK_ASRC0_MUX_CLK = 0x1e, + + INCLK_ESAI1_RX_CLK = 0x20, + INCLK_ESAI1_TX_CLK = 0x21, + INCLK_SAI6_TX_BCLK = 0x22, + INCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, + INCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, }; enum asrc_outclk { @@ -325,6 +348,29 @@ enum asrc_outclk { OUTCLK_SSI3_RX = 0x0b, OUTCLK_SPDIF_RX = 0x0c, OUTCLK_ASRCK1_CLK = 0x0f, + + /* clocks for imx8 */ + OUTCLK_AUD_PLL_DIV_CLK0 = 0x10, + OUTCLK_AUD_PLL_DIV_CLK1 = 0x11, + OUTCLK_AUD_CLK0 = 0x12, + OUTCLK_AUD_CLK1 = 0x13, + OUTCLK_ESAI0_RX_CLK = 0x14, + OUTCLK_ESAI0_TX_CLK = 0x15, + OUTCLK_SPDIF0_RX = 0x16, + OUTCLK_SPDIF1_RX = 0x17, + OUTCLK_SAI0_RX_BCLK = 0x18, + OUTCLK_SAI0_TX_BCLK = 0x19, + OUTCLK_SAI1_RX_BCLK = 0x1a, + OUTCLK_SAI1_TX_BCLK = 0x1b, + OUTCLK_SAI2_RX_BCLK = 0x1c, + OUTCLK_SAI3_RX_BCLK = 0x1d, + OUTCLK_ASRCO_MUX_CLK = 0x1e, + + OUTCLK_ESAI1_RX_CLK = 0x20, + OUTCLK_ESAI1_TX_CLK = 0x21, + OUTCLK_SAI6_TX_BCLK = 0x22, + OUTCLK_HDMI_RX_SAI0_RX_BCLK = 0x24, + OUTCLK_HDMI_TX_SAI0_TX_BCLK = 0x25, }; #define ASRC_CLK_MAX_NUM 16 @@ -387,6 +433,21 @@ struct dma_block { unsigned int length; }; +/** + * fsl_asrc_soc_data: soc specific data + * + * @use_edma: using edma as dma device or not + * @channel_bits: width of ASRCNCR register for each pair + * @inclk_map: clock map for input clock + * @outclk_map: clock map for output clock + */ +struct fsl_asrc_soc_data { + bool use_edma; + unsigned int channel_bits; + unsigned char *inclk_map; + unsigned char *outclk_map; +}; + /** * fsl_asrc_pair: ASRC Pair private data * @@ -431,7 +492,7 @@ struct fsl_asrc_pair { * @asrck_clk: clock sources to driver ASRC internal logic * @lock: spin lock for resource protection * @pair: pair pointers - * @channel_bits: width of ASRCNCR register for each pair + * @soc: soc specific data * @channel_avail: non-occupied channel numbers * @asrc_rate: default sample rate for ASoC Back-Ends * @asrc_width: default sample width for ASoC Back-Ends @@ -450,7 +511,7 @@ struct fsl_asrc { spinlock_t lock; struct fsl_asrc_pair *pair[ASRC_PAIR_MAX_NUM]; - unsigned int channel_bits; + const struct fsl_asrc_soc_data *soc; unsigned int channel_avail; int asrc_rate; diff --git a/sound/soc/fsl/fsl_asrc_dma.c b/sound/soc/fsl/fsl_asrc_dma.c index d6146de9acd2..f871fdb9d1c6 100644 --- a/sound/soc/fsl/fsl_asrc_dma.c +++ b/sound/soc/fsl/fsl_asrc_dma.c @@ -197,21 +197,37 @@ static int fsl_asrc_dma_hw_params(struct snd_soc_component *component, dma_cap_set(DMA_SLAVE, mask); dma_cap_set(DMA_CYCLIC, mask); - /* Get DMA request of Back-End */ - tmp_chan = dma_request_slave_channel(dev_be, tx ? "tx" : "rx"); - tmp_data = tmp_chan->private; - pair->dma_data.dma_request = tmp_data->dma_request; - dma_release_channel(tmp_chan); + /* + * For EDMA DEV_TO_DEV channel, we don't need to configure + * dma_request and dma_request2, we can get dma channel through + * dma_request_slave_channel directly. + * Compare with SDMA channel, EDMA channel is bound with dma + * request event of each peripheral, and it is fixed. Not like SDMA, + * the channel is allocated dynamically. So when DMA is EDMA, we + * can only get EDMA channel through dma-names of Front-End device. + */ + if (!asrc_priv->soc->use_edma) { + /* Get DMA request of Back-End */ + tmp_chan = dma_request_slave_channel(dev_be, tx ? "tx" : "rx"); + tmp_data = tmp_chan->private; + pair->dma_data.dma_request = tmp_data->dma_request; + dma_release_channel(tmp_chan); - /* Get DMA request of Front-End */ - tmp_chan = fsl_asrc_get_dma_channel(pair, dir); - tmp_data = tmp_chan->private; - pair->dma_data.dma_request2 = tmp_data->dma_request; - pair->dma_data.peripheral_type = tmp_data->peripheral_type; - pair->dma_data.priority = tmp_data->priority; - dma_release_channel(tmp_chan); + /* Get DMA request of Front-End */ + tmp_chan = fsl_asrc_get_dma_channel(pair, dir); + tmp_data = tmp_chan->private; + pair->dma_data.dma_request2 = tmp_data->dma_request; + pair->dma_data.peripheral_type = tmp_data->peripheral_type; + pair->dma_data.priority = tmp_data->priority; + dma_release_channel(tmp_chan); + + pair->dma_chan[dir] = + dma_request_channel(mask, filter, &pair->dma_data); + } else { + pair->dma_chan[dir] = + fsl_asrc_get_dma_channel(pair, dir); + } - pair->dma_chan[dir] = dma_request_channel(mask, filter, &pair->dma_data); if (!pair->dma_chan[dir]) { dev_err(dev, "failed to request DMA channel for Back-End\n"); return -EINVAL;