From patchwork Sun Nov 3 01:36:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 178363 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2569976ill; Sat, 2 Nov 2019 18:37:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqyl8HRiQ9D0fTy0Sn6Nqk24dMAp5Oc0xhw16+xi2VvCLxgkrqBZglPve8HrfTJGvf+92bdT X-Received: by 2002:a50:c408:: with SMTP id v8mr21379241edf.140.1572745020272; Sat, 02 Nov 2019 18:37:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572745020; cv=none; d=google.com; s=arc-20160816; b=wpGMNBXKmbOQyda+tIJE5EeM9fQYFzCeBi//l8K72uKqU7nXyBnUcUiXFAJ41A9B3C Oky7Z6imPGvLkE04fafzV5Sc5auy2n6LiG5LzBL3av1bQv2FJLTyr9MoqBpUfneQOVBB gaPMIa3vHLEdUvuaN72miKlGUZa74z45T9t9LElfa0BXzBvPHeP9XDDHnrEG33Lk1nqy sO55JJICN96txLKlYO6BrmlQacGcckgjRDSkiYHv+zYlDyuEohbC0aMFk554RAUml9P7 attAXTuuPo0ZT252GTAMtGPDI94y5W+su50kaJBtGEg4+8LpZXVVoO/HUtygbj9RRW76 aOrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=2h/vyPYQwBocdjH0XFbof7MJkToEY3IHX75DvJh5N3o=; b=RbLKWSq1aXVzH3XTMh2wAnEPb0adY0dmihdm55pni7tgOuicaedPMpHKkwy1rYe8ic fDAHda/04yL600ECOVEFITyW9/mCvhGIxuaud5vb36RYBep2w4NmweZj1u7RKjmneo8p lM36ZboiwXwmK3SHQRkO2/xRdpU3d+rHErShY5M/G7C/XurvFlBzQ+zg3kmT+bA8ZP7J zQhbM/bnpMDTbkj6I6wKbhkNzLfeUnJl2/y5ZXg9O02+z5wV6cgL4aWqE6ty271jK9o0 nh/Ma53B8nD7aAGCO4nK7fi+LLi6fxQb28UTgJoBPBIkdHaIat0pvEqbsmcyCjUexTOS DeNg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r20si3906087edm.17.2019.11.02.18.36.58; Sat, 02 Nov 2019 18:37:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727364AbfKCBgy (ORCPT + 8 others); Sat, 2 Nov 2019 21:36:54 -0400 Received: from mx2.suse.de ([195.135.220.15]:59408 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727346AbfKCBgy (ORCPT ); Sat, 2 Nov 2019 21:36:54 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id DAAC3AF26; Sun, 3 Nov 2019 01:36:52 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [RFC 01/11] dt-bindings: soc: Add Realtek RTD1195 chip info binding Date: Sun, 3 Nov 2019 02:36:35 +0100 Message-Id: <20191103013645.9856-2-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191103013645.9856-1-afaerber@suse.de> References: <20191103013645.9856-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define a binding for RTD1195 and later SoCs' chip info registers. Add the new directory to MAINTAINERS. Signed-off-by: Andreas Färber --- Note: The binding gets extended compatibly later for up to three reg entries. .../bindings/soc/realtek/realtek,rtd1195-chip.yaml | 32 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml -- 2.16.4 diff --git a/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml new file mode 100644 index 000000000000..565ad2419553 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/realtek/realtek,rtd1195-chip.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Realtek RTD1195 chip identification + +maintainers: + - Andreas Färber + +description: | + The Realtek SoCs have some registers to identify the chip and revision. + +properties: + compatible: + const: "realtek,rtd1195-chip" + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + chip-info@1801a200 { + compatible = "realtek,rtd1195-chip"; + reg = <0x1801a200 0x8>; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index f33adc430230..5c61cf5a44cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2188,6 +2188,7 @@ L: linux-realtek-soc@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm64/boot/dts/realtek/ F: Documentation/devicetree/bindings/arm/realtek.yaml +F: Documentation/devicetree/bindings/soc/realtek/ ARM/RENESAS ARM64 ARCHITECTURE M: Geert Uytterhoeven From patchwork Sun Nov 3 01:36:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 178371 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2570225ill; Sat, 2 Nov 2019 18:37:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqz3zCdPtijvAemrScKFb8+UFaoidoCoGbxTNlKv6FKhTzsIr862gg1ufWx+a5zgzAdatlH/ X-Received: by 2002:a17:906:1a47:: with SMTP id j7mr7494692ejf.232.1572745043846; Sat, 02 Nov 2019 18:37:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572745043; cv=none; d=google.com; s=arc-20160816; b=JJCyAInUhiuIRsa9UFkk8rt8U7MABKDgIQSM8DTBO1Y1Ec2KazVOAk3fTmd1I1Kwej lzjFooDqnvVsZwIxdWDtfDBVxNgmy7W/y3lRgTOax8qJL8X6xJ+0WtZHQbf5Q4CyhItj WCk0kjEEpNeJBvfr6kIBws6Rb6WhE4QQ88qYn69XNxbnbDHhpPzY6VCJ0vvHhZ/g3uLQ vFwE/cVELe6ZA4n9xZsoWYbls0oNgsls7EGHpCv3L+woyqATROC9/ZyNF3WYBiKV+eS7 KPKS/rxpbt2AzIxOiu+2SgaQ8L+Z9wpf3ruVcuHpIeTsOPUSUjCXb8Wjdu9xvud+1PrS x4YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=PkeA4+PZs28buwtV5ndDHFaCwC6bydbMW/LIi86Stck=; b=hEuwZZoeyR19klUJDndoBOTtmrimgRXH4FooXOYQzpaJbYE7OuDiU171huL8ul0HzW uEjaUKYgZe5O5z82CgBwmuiyUd6aTxUxrunI98faXQBQ/3KtAbi1vg1RPlR0j/bIvely cRf7eo59aIzSEfbIrkaNxsOx/9rGhcFfgxsgLVoBoNsL19BymwSyz4RQ4IO/YYDuJhM7 FZGOnOqmzfXcMv3Yu/knJXR2n6f5CT59YL8AEqnBAmr4fo+DK2VJPYL9FEbh9SGoUpoQ ninS0g18rvAZH5sIPiXLvcth5+NzFP+uHLf74pnCwg4BkDToacnMHI91v/H9tyZ7OY9t 1VTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id gg4si897767ejb.236.2019.11.02.18.37.23; Sat, 02 Nov 2019 18:37:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727636AbfKCBhR (ORCPT + 8 others); Sat, 2 Nov 2019 21:37:17 -0400 Received: from mx2.suse.de ([195.135.220.15]:59468 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727360AbfKCBg5 (ORCPT ); Sat, 2 Nov 2019 21:36:57 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 8EA30B1F0; Sun, 3 Nov 2019 01:36:55 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [RFC 07/11] arm64: dts: realtek: rtd129x: Extend chip-info reg with CHIP_INFO1 Date: Sun, 3 Nov 2019 02:36:41 +0100 Message-Id: <20191103013645.9856-8-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191103013645.9856-1-afaerber@suse.de> References: <20191103013645.9856-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This additional register is needed to distinguish RTD1296 from RTD1295. Signed-off-by: Andreas Färber --- arch/arm64/boot/dts/realtek/rtd129x.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.16.4 diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 15a7c249155d..fea7c1ed7d08 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -86,7 +86,8 @@ chip-info@9801a200 { compatible = "realtek,rtd1195-chip"; - reg = <0x9801a200 0x8>; + reg = <0x9801a200 0x8>, + <0x98007028 0x4>; }; uart1: serial@9801b200 { From patchwork Sun Nov 3 01:36:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 178369 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2570149ill; Sat, 2 Nov 2019 18:37:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqzCM3iJaelAQFZnfF3T8ni+yy0pvR4ESQEpJDjqfCd+e1a9DJ4ZcjjJ6zsQx+1XRqfbCS85 X-Received: by 2002:a50:9fcb:: with SMTP id c69mr3727518edf.163.1572745038266; Sat, 02 Nov 2019 18:37:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1572745038; cv=none; d=google.com; s=arc-20160816; b=mzPf5KDEalkJSeUodoUl+Pq63LHk1ZoNl+jRGKx6eTnoxfrr/cI37L69Ze3RYq4oRV Dn3vVi6PgqdcOpFOZB0BKzaADw0ipzEl4whRI9Zylbrf7fjFb6T4/zWAlQquPmtZqSJv 1EhB++iWUCYODw/QoUVUg72bt8CpB9PWYu0tmWH0Iy6HGIOsryruzpbBnxmxcOObntnL HCGHSBo2a0qQRKns7P50gyYZBsAO6BPCtFCal9bOCD3J0JVWtitYyJGsgbVmtBUl5YWD 2+4NSObFl9Mcp3lT9U0Co/zmDWHtn0k677OH0S+5j7ugHyqBQdT0tNrx16blIiunMky3 wL9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=1LiH0sOjo8FPXZF1ap29WtKZX+ttl9ESy8SSeKNthmc=; b=oiN20+10QCSvuiF0AfVHhzP67WDJgVp33Em+RItvzH9I+ceFFTHujY8kLvB3/DPJiq SUcTVyHwBXeTXL+tUv98N0v+PvT+3HLAgVnkTMHDTYuAwD7zKSFXPjDqN6sNqvvHDhng Gw24sf+hQ7juuvTxlfx/upAwxAd6FfNrNjCvlIllJv/JuBWhfjts5BnOSbggGZNTvSqX gAvwm5F9++0IOnbeE36UOhSB+2sZ5AJKmYoEP1KBjOzJHejmio3Tne4FXFeopSkJ6YdZ 563nALEiVhHlEvOwGJ3AmAGKYoLDJFogUlwexs7d6x1IHmfdxSI1d23mp7WlhJTHTc2k rD6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g40si4077120edb.369.2019.11.02.18.37.18; Sat, 02 Nov 2019 18:37:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727590AbfKCBhF (ORCPT + 8 others); Sat, 2 Nov 2019 21:37:05 -0400 Received: from mx2.suse.de ([195.135.220.15]:59462 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727488AbfKCBg5 (ORCPT ); Sat, 2 Nov 2019 21:36:57 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 5DFD7B300; Sun, 3 Nov 2019 01:36:56 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [RFC 09/11] dt-bindings: soc: realtek: rtd1195-chip: Extend reg node again Date: Sun, 3 Nov 2019 02:36:43 +0100 Message-Id: <20191103013645.9856-10-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191103013645.9856-1-afaerber@suse.de> References: <20191103013645.9856-1-afaerber@suse.de> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow to optionally specify a third register to identify the chip. Whether needed and which register to specify depends on the family; RTD1295 family will want an efuse register. Signed-off-by: Andreas Färber --- I don't like specifying an efuse register here, which seems its own IP block. .../devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) -- 2.16.4 diff --git a/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml index e431cf559b66..249737e116d7 100644 --- a/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml +++ b/Documentation/devicetree/bindings/soc/realtek/realtek,rtd1195-chip.yaml @@ -19,7 +19,7 @@ properties: reg: minItems: 1 - maxItems: 2 + maxItems: 3 required: - compatible @@ -37,4 +37,11 @@ examples: reg = <0x9801a200 0x8>, <0x98007028 0x4>; }; + - | + chip-info@9801a200 { + compatible = "realtek,rtd1195-chip"; + reg = <0x9801a200 0x8>, + <0x98007028 0x4>, + <0x980171d8 0x4>; + }; ...